Line Coverage for Module :
tlul_err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 38 | 14 | 14 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
37 always_ff @(posedge clk_i or negedge rst_ni) begin
38 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
39 1/1 err_rsp_pending <= 1'b0;
Tests: T1 T2 T3
40 1/1 err_source <= {top_pkg::TL_AIW{1'b0}};
Tests: T1 T2 T3
41 1/1 err_opcode <= Get;
Tests: T1 T2 T3
42 1/1 err_size <= '0;
Tests: T1 T2 T3
43 1/1 err_instr_type <= MuBi4False;
Tests: T1 T2 T3
44 1/1 end else if (err_rsp_pending && tl_h_i.d_ready) begin
Tests: T1 T2 T3
45 1/1 err_rsp_pending <= 1'b0;
Tests: T2 T9 T7
46 1/1 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
Tests: T1 T2 T3
47 1/1 err_rsp_pending <= 1'b1;
Tests: T2 T9 T7
48 1/1 err_source <= tl_h_i.a_source;
Tests: T2 T9 T7
49 1/1 err_opcode <= tl_h_i.a_opcode;
Tests: T2 T9 T7
50 1/1 err_size <= tl_h_i.a_size;
Tests: T2 T9 T7
51 1/1 err_instr_type <= tl_h_i.a_user.instr_type;
Tests: T2 T9 T7
52 end
MISSING_ELSE
53 end
54
55 1/1 assign tl_h_o_int.a_ready = ~err_rsp_pending;
Tests: T1 T2 T3
56 1/1 assign tl_h_o_int.d_valid = err_rsp_pending;
Tests: T1 T2 T3
57 if (ReturnBlankResp) begin : gen_zero_resp
58 assign tl_h_o_int.d_data = '0;
59 end else begin : gen_err_resp
60 1/1 assign tl_h_o_int.d_data = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
Tests: T1 T2 T3
61 DataWhenError;
62 end
63 1/1 assign tl_h_o_int.d_source = err_source;
Tests: T1 T2 T3
64 assign tl_h_o_int.d_sink = '0;
65 assign tl_h_o_int.d_param = '0;
66 1/1 assign tl_h_o_int.d_size = err_size;
Tests: T1 T2 T3
67 1/1 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
Tests: T1 T2 T3
68 assign tl_h_o_int.d_user = '0;
69 assign tl_h_o_int.d_error = ~ReturnBlankResp;
70
71 // Waive unused bits of tl_h_i
72 logic unused_tl_h;
73 1/1 assign unused_tl_h = ^{tl_h_i, err_instr_type};
Tests: T1 T2 T3
Cond Coverage for Module :
tlul_err_resp
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 44
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T12,T13 |
1 | 1 | Covered | T2,T9,T7 |
LINE 46
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T13,T37 |
1 | 1 | Covered | T2,T9,T7 |
LINE 67
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T2,T9,T7 |
1 | Covered | T1,T2,T3 |
LINE 67
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
tlul_err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
67 |
2 |
2 |
100.00 |
IF |
38 |
4 |
4 |
100.00 |
67 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T9,T7 |
38 if (!rst_ni) begin
-1-
39 err_rsp_pending <= 1'b0;
==>
40 err_source <= {top_pkg::TL_AIW{1'b0}};
41 err_opcode <= Get;
42 err_size <= '0;
43 err_instr_type <= MuBi4False;
44 end else if (err_rsp_pending && tl_h_i.d_ready) begin
-2-
45 err_rsp_pending <= 1'b0;
==>
46 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
-3-
47 err_rsp_pending <= 1'b1;
==>
48 err_source <= tl_h_i.a_source;
49 err_opcode <= tl_h_i.a_opcode;
50 err_size <= tl_h_i.a_size;
51 err_instr_type <= tl_h_i.a_user.instr_type;
52 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T9,T7 |
0 |
0 |
1 |
Covered |
T2,T9,T7 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 38 | 14 | 14 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
37 always_ff @(posedge clk_i or negedge rst_ni) begin
38 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
39 1/1 err_rsp_pending <= 1'b0;
Tests: T1 T2 T3
40 1/1 err_source <= {top_pkg::TL_AIW{1'b0}};
Tests: T1 T2 T3
41 1/1 err_opcode <= Get;
Tests: T1 T2 T3
42 1/1 err_size <= '0;
Tests: T1 T2 T3
43 1/1 err_instr_type <= MuBi4False;
Tests: T1 T2 T3
44 1/1 end else if (err_rsp_pending && tl_h_i.d_ready) begin
Tests: T1 T2 T3
45 1/1 err_rsp_pending <= 1'b0;
Tests: T2 T9 T7
46 1/1 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
Tests: T1 T2 T3
47 1/1 err_rsp_pending <= 1'b1;
Tests: T2 T9 T7
48 1/1 err_source <= tl_h_i.a_source;
Tests: T2 T9 T7
49 1/1 err_opcode <= tl_h_i.a_opcode;
Tests: T2 T9 T7
50 1/1 err_size <= tl_h_i.a_size;
Tests: T2 T9 T7
51 1/1 err_instr_type <= tl_h_i.a_user.instr_type;
Tests: T2 T9 T7
52 end
MISSING_ELSE
53 end
54
55 1/1 assign tl_h_o_int.a_ready = ~err_rsp_pending;
Tests: T1 T2 T3
56 1/1 assign tl_h_o_int.d_valid = err_rsp_pending;
Tests: T1 T2 T3
57 if (ReturnBlankResp) begin : gen_zero_resp
58 assign tl_h_o_int.d_data = '0;
59 end else begin : gen_err_resp
60 1/1 assign tl_h_o_int.d_data = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
Tests: T1 T2 T3
61 DataWhenError;
62 end
63 1/1 assign tl_h_o_int.d_source = err_source;
Tests: T1 T2 T3
64 assign tl_h_o_int.d_sink = '0;
65 assign tl_h_o_int.d_param = '0;
66 1/1 assign tl_h_o_int.d_size = err_size;
Tests: T1 T2 T3
67 1/1 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
Tests: T1 T2 T3
68 assign tl_h_o_int.d_user = '0;
69 assign tl_h_o_int.d_error = ~ReturnBlankResp;
70
71 // Waive unused bits of tl_h_i
72 logic unused_tl_h;
73 1/1 assign unused_tl_h = ^{tl_h_i, err_instr_type};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 44
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T12,T52 |
1 | 1 | Covered | T2,T9,T7 |
LINE 46
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T82,T159 |
1 | 1 | Covered | T2,T9,T7 |
LINE 67
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T2,T7,T12 |
1 | Covered | T1,T2,T3 |
LINE 67
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
67 |
2 |
2 |
100.00 |
IF |
38 |
4 |
4 |
100.00 |
67 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T7,T12 |
38 if (!rst_ni) begin
-1-
39 err_rsp_pending <= 1'b0;
==>
40 err_source <= {top_pkg::TL_AIW{1'b0}};
41 err_opcode <= Get;
42 err_size <= '0;
43 err_instr_type <= MuBi4False;
44 end else if (err_rsp_pending && tl_h_i.d_ready) begin
-2-
45 err_rsp_pending <= 1'b0;
==>
46 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
-3-
47 err_rsp_pending <= 1'b1;
==>
48 err_source <= tl_h_i.a_source;
49 err_opcode <= tl_h_i.a_opcode;
50 err_size <= tl_h_i.a_size;
51 err_instr_type <= tl_h_i.a_user.instr_type;
52 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T9,T7 |
0 |
0 |
1 |
Covered |
T2,T9,T7 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 38 | 14 | 14 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
37 always_ff @(posedge clk_i or negedge rst_ni) begin
38 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
39 1/1 err_rsp_pending <= 1'b0;
Tests: T1 T2 T3
40 1/1 err_source <= {top_pkg::TL_AIW{1'b0}};
Tests: T1 T2 T3
41 1/1 err_opcode <= Get;
Tests: T1 T2 T3
42 1/1 err_size <= '0;
Tests: T1 T2 T3
43 1/1 err_instr_type <= MuBi4False;
Tests: T1 T2 T3
44 1/1 end else if (err_rsp_pending && tl_h_i.d_ready) begin
Tests: T1 T2 T3
45 1/1 err_rsp_pending <= 1'b0;
Tests: T9 T12 T13
46 1/1 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
Tests: T1 T2 T3
47 1/1 err_rsp_pending <= 1'b1;
Tests: T9 T12 T13
48 1/1 err_source <= tl_h_i.a_source;
Tests: T9 T12 T13
49 1/1 err_opcode <= tl_h_i.a_opcode;
Tests: T9 T12 T13
50 1/1 err_size <= tl_h_i.a_size;
Tests: T9 T12 T13
51 1/1 err_instr_type <= tl_h_i.a_user.instr_type;
Tests: T9 T12 T13
52 end
MISSING_ELSE
53 end
54
55 1/1 assign tl_h_o_int.a_ready = ~err_rsp_pending;
Tests: T1 T2 T3
56 1/1 assign tl_h_o_int.d_valid = err_rsp_pending;
Tests: T1 T2 T3
57 if (ReturnBlankResp) begin : gen_zero_resp
58 assign tl_h_o_int.d_data = '0;
59 end else begin : gen_err_resp
60 1/1 assign tl_h_o_int.d_data = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
Tests: T1 T2 T3
61 DataWhenError;
62 end
63 1/1 assign tl_h_o_int.d_source = err_source;
Tests: T1 T2 T3
64 assign tl_h_o_int.d_sink = '0;
65 assign tl_h_o_int.d_param = '0;
66 1/1 assign tl_h_o_int.d_size = err_size;
Tests: T1 T2 T3
67 1/1 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
Tests: T1 T2 T3
68 assign tl_h_o_int.d_user = '0;
69 assign tl_h_o_int.d_error = ~ReturnBlankResp;
70
71 // Waive unused bits of tl_h_i
72 logic unused_tl_h;
73 1/1 assign unused_tl_h = ^{tl_h_i, err_instr_type};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 44
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T52,T55 |
1 | 1 | Covered | T9,T12,T13 |
LINE 46
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T151,T277 |
1 | 1 | Covered | T9,T12,T13 |
LINE 67
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T9,T12,T13 |
1 | Covered | T1,T2,T3 |
LINE 67
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
67 |
2 |
2 |
100.00 |
IF |
38 |
4 |
4 |
100.00 |
67 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T9,T12,T13 |
38 if (!rst_ni) begin
-1-
39 err_rsp_pending <= 1'b0;
==>
40 err_source <= {top_pkg::TL_AIW{1'b0}};
41 err_opcode <= Get;
42 err_size <= '0;
43 err_instr_type <= MuBi4False;
44 end else if (err_rsp_pending && tl_h_i.d_ready) begin
-2-
45 err_rsp_pending <= 1'b0;
==>
46 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
-3-
47 err_rsp_pending <= 1'b1;
==>
48 err_source <= tl_h_i.a_source;
49 err_opcode <= tl_h_i.a_opcode;
50 err_size <= tl_h_i.a_size;
51 err_instr_type <= tl_h_i.a_user.instr_type;
52 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T9,T12,T13 |
0 |
0 |
1 |
Covered |
T9,T12,T13 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 38 | 14 | 14 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
37 always_ff @(posedge clk_i or negedge rst_ni) begin
38 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
39 1/1 err_rsp_pending <= 1'b0;
Tests: T1 T2 T3
40 1/1 err_source <= {top_pkg::TL_AIW{1'b0}};
Tests: T1 T2 T3
41 1/1 err_opcode <= Get;
Tests: T1 T2 T3
42 1/1 err_size <= '0;
Tests: T1 T2 T3
43 1/1 err_instr_type <= MuBi4False;
Tests: T1 T2 T3
44 1/1 end else if (err_rsp_pending && tl_h_i.d_ready) begin
Tests: T1 T2 T3
45 1/1 err_rsp_pending <= 1'b0;
Tests: T12 T13 T4
46 1/1 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
Tests: T1 T2 T3
47 1/1 err_rsp_pending <= 1'b1;
Tests: T12 T13 T4
48 1/1 err_source <= tl_h_i.a_source;
Tests: T12 T13 T4
49 1/1 err_opcode <= tl_h_i.a_opcode;
Tests: T12 T13 T4
50 1/1 err_size <= tl_h_i.a_size;
Tests: T12 T13 T4
51 1/1 err_instr_type <= tl_h_i.a_user.instr_type;
Tests: T12 T13 T4
52 end
MISSING_ELSE
53 end
54
55 1/1 assign tl_h_o_int.a_ready = ~err_rsp_pending;
Tests: T1 T2 T3
56 1/1 assign tl_h_o_int.d_valid = err_rsp_pending;
Tests: T1 T2 T3
57 if (ReturnBlankResp) begin : gen_zero_resp
58 assign tl_h_o_int.d_data = '0;
59 end else begin : gen_err_resp
60 1/1 assign tl_h_o_int.d_data = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
Tests: T1 T2 T3
61 DataWhenError;
62 end
63 1/1 assign tl_h_o_int.d_source = err_source;
Tests: T1 T2 T3
64 assign tl_h_o_int.d_sink = '0;
65 assign tl_h_o_int.d_param = '0;
66 1/1 assign tl_h_o_int.d_size = err_size;
Tests: T1 T2 T3
67 1/1 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
Tests: T1 T2 T3
68 assign tl_h_o_int.d_user = '0;
69 assign tl_h_o_int.d_error = ~ReturnBlankResp;
70
71 // Waive unused bits of tl_h_i
72 logic unused_tl_h;
73 1/1 assign unused_tl_h = ^{tl_h_i, err_instr_type};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 44
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T13,T37 |
1 | 1 | Covered | T12,T13,T14 |
LINE 46
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T13,T37 |
1 | 1 | Covered | T12,T13,T14 |
LINE 67
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T12,T13,T37 |
1 | Covered | T1,T2,T3 |
LINE 67
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
67 |
2 |
2 |
100.00 |
IF |
38 |
4 |
4 |
100.00 |
67 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T12,T13,T37 |
38 if (!rst_ni) begin
-1-
39 err_rsp_pending <= 1'b0;
==>
40 err_source <= {top_pkg::TL_AIW{1'b0}};
41 err_opcode <= Get;
42 err_size <= '0;
43 err_instr_type <= MuBi4False;
44 end else if (err_rsp_pending && tl_h_i.d_ready) begin
-2-
45 err_rsp_pending <= 1'b0;
==>
46 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
-3-
47 err_rsp_pending <= 1'b1;
==>
48 err_source <= tl_h_i.a_source;
49 err_opcode <= tl_h_i.a_opcode;
50 err_size <= tl_h_i.a_size;
51 err_instr_type <= tl_h_i.a_user.instr_type;
52 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T12,T13,T4 |
0 |
0 |
1 |
Covered |
T12,T13,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |