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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.aDataKnown_A	0	0	259629986	6395791	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.addrSizeAligned_A	0	0	259629986	7857621	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.contigMask_A	0	0	259629986	5222779	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.dDataKnown_M	0	0	259629986	523763	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.legalAOpcode_A	0	0	259629986	7857621	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.legalAParam_A	0	0	259629986	9240117	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.legalDParam_M	0	0	259629986	1940853	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.pendingReqPerSrc_A	0	0	259629986	9240117	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.respMustHaveReq_M	0	0	259629986	1940853	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.respOpcode_M	0	0	259629986	1940853	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.respSzEqReqSz_M	0	0	259629986	1940853	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.sizeGTEMask_A	0	0	259629986	7857621	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.gen_host.sizeMatchesMask_A	0	0	259629986	7857621	0	0
tb.dut.tlul_assert_device_flash_ctrl__mem.p_dbw.TlDbw_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.aKnown_A	0	0	259629478	2193743	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.aKnown_AKnownEnable	0	0	259629478	259512400	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.aReadyKnown_A	0	0	259629478	259512400	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.dKnown_A	0	0	259629478	492395	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.dKnown_AKnownEnable	0	0	259629478	259512400	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.dReadyKnown_A	0	0	259629478	259512400	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0
tb.dut.tlul_assert_device_flash_ctrl__prim.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	899	899	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	9532	0	222
Category 0	9532	0	222

	ASSERT	PROPERTIES	SEQUENCES
Total	9532	0	222
Severity 0	9532	0	222

	NUMBER	PERCENT
Total Number	9532	100.00
Uncovered	70	0.73
Success	9462	99.27
Failure	0	0.00
Incomplete	24	0.25
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	222	100.00
Uncovered	0	0.00
All Matches	222	100.00
First Matches	222	100.00