Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	175879	1			T1	12		T2	11		T3	8
values[2]	6676	1			T2	1		T11	11		T13	1
values[3]	2394	1			T50	1		T73	87		T74	1
values[4]	1575	1			T73	63		T76	2		T79	35
values[5]	1161	1			T73	48		T76	9		T79	34
values[6]	947	1			T73	25		T76	14		T79	15
values[7]	888	1			T73	7		T76	9		T79	9
values[8]	874	1			T73	12		T76	3		T79	4
values[9]	748	1			T73	1		T76	14		T79	4
values[10]	645	1			T76	20		T79	19		T174	6
values[11]	644	1			T76	17		T79	11		T81	22
values[12]	633	1			T76	14		T79	12		T81	34
values[13]	593	1			T76	7		T79	11		T81	38
values[14]	536	1			T76	10		T79	28		T81	32
values[15]	508	1			T76	4		T79	22		T81	29
values[16]	412	1			T76	2		T79	12		T81	6
values[17]	424	1			T76	4		T79	22		T256	1
values[18]	401	1			T76	9		T79	20		T256	1
values[19]	385	1			T76	18		T79	6		T256	1
values[20]	341	1			T76	30		T79	4		T256	1
values[21]	352	1			T76	49		T79	11		T256	1
values[22]	272	1			T76	20		T79	8		T256	1
values[23]	259	1			T76	14		T79	23		T256	1
values[24]	209	1			T76	7		T79	13		T256	1
values[25]	279	1			T76	37		T79	8		T256	1
values[26]	308	1			T76	27		T79	7		T256	1
values[27]	249	1			T76	19		T79	13		T256	1
values[28]	184	1			T76	10		T79	7		T256	1
values[29]	143	1			T76	7		T79	7		T256	1
values[30]	139	1			T76	2		T79	5		T256	1
values[31]	153	1			T76	3		T79	6		T256	1
values[32]	119	1			T76	4		T79	5		T256	1
values[33]	115	1			T76	3		T79	1		T256	1
values[34]	92	1			T76	10		T256	1		T306	8
values[35]	113	1			T76	17		T256	1		T306	12
values[36]	91	1			T76	5		T256	1		T306	10
values[37]	94	1			T76	6		T256	1		T306	5
values[38]	98	1			T76	8		T256	1		T99	2
values[39]	91	1			T76	6		T256	1		T99	1
values[40]	85	1			T256	1		T99	1		T125	5
values[41]	70	1			T256	1		T99	1		T125	3
values[42]	68	1			T256	1		T99	3		T125	1
values[43]	63	1			T256	1		T99	4		T125	1
values[44]	60	1			T256	1		T99	1		T125	1
values[45]	61	1			T256	1		T99	2		T125	2
values[46]	70	1			T256	1		T99	5		T125	2
values[47]	64	1			T256	1		T99	5		T125	5
values[48]	62	1			T256	1		T99	3		T125	3
values[49]	57	1			T256	1		T99	1		T125	2
values[50]	56	1			T256	1		T99	2		T125	2
values[51]	57	1			T256	1		T99	1		T125	2
values[52]	54	1			T256	1		T99	1		T125	2
values[53]	53	1			T256	1		T99	3		T125	1
values[54]	78	1			T256	1		T99	5		T125	1
values[55]	58	1			T256	1		T99	1		T125	1
values[56]	66	1			T256	1		T99	2		T125	7
values[57]	59	1			T256	1		T99	5		T125	3
values[58]	56	1			T256	1		T99	6		T125	1
values[59]	55	1			T256	1		T99	5		T125	6
values[60]	54	1			T256	1		T99	3		T125	2
values[61]	51	1			T256	1		T99	2		T125	1
values[62]	64	1			T256	1		T99	2		T125	2
values[63]	61	1			T256	1		T99	2		T125	2
values[64]	59	1			T256	1		T99	3		T125	3
values[65]	60	1			T256	1		T99	2		T125	3
values[66]	57	1			T256	1		T99	1		T125	2
values[67]	57	1			T256	1		T99	3		T125	2
values[68]	56	1			T256	1		T99	2		T125	3
values[69]	59	1			T256	1		T99	1		T125	1
values[70]	59	1			T256	1		T99	3		T125	2
values[71]	65	1			T256	1		T99	1		T125	2
values[72]	76	1			T256	1		T99	2		T125	3
values[73]	61	1			T256	1		T99	5		T125	3
values[74]	56	1			T256	1		T99	5		T125	1
values[75]	63	1			T256	1		T99	4		T125	2
values[76]	64	1			T256	1		T99	1		T125	1
values[77]	71	1			T256	1		T99	3		T125	3
values[78]	56	1			T256	1		T99	1		T125	1
values[79]	67	1			T256	1		T99	2		T125	1
values[80]	66	1			T256	1		T99	3		T125	2
values[81]	60	1			T256	1		T99	2		T125	1
values[82]	80	1			T256	1		T99	2		T125	5
values[83]	72	1			T256	1		T99	2		T125	1
values[84]	72	1			T256	1		T99	1		T125	2
values[85]	85	1			T256	1		T99	1		T125	1
values[86]	87	1			T256	6		T99	4		T125	1
values[87]	78	1			T256	2		T99	1		T125	2
values[88]	68	1			T256	1		T99	5		T125	2
values[89]	75	1			T256	3		T99	4		T125	1
values[90]	93	1			T256	3		T99	6		T125	4
values[91]	76	1			T256	6		T99	1		T125	1
values[92]	99	1			T256	2		T99	3		T125	4
values[93]	89	1			T256	5		T99	6		T125	2
values[94]	91	1			T256	1		T99	8		T125	3
values[95]	98	1			T256	4		T99	8		T125	6
values[96]	94	1			T256	2		T99	9		T125	3
values[97]	90	1			T256	1		T99	10		T125	5
values[98]	76	1			T256	2		T99	4		T125	3
values[99]	88	1			T256	3		T99	4		T125	2
values[100]	92	1			T256	2		T99	1		T125	1
values[101]	91	1			T256	1		T99	2		T125	5
values[102]	115	1			T256	5		T99	3		T125	4
values[103]	84	1			T256	2		T99	5		T125	2
values[104]	84	1			T256	2		T99	5		T125	2
values[105]	80	1			T256	4		T99	1		T125	1
values[106]	98	1			T256	1		T99	3		T125	3
values[107]	90	1			T256	2		T99	6		T125	2
values[108]	94	1			T256	4		T99	3		T125	1
values[109]	110	1			T256	3		T99	2		T125	1
values[110]	86	1			T256	1		T99	2		T125	5
values[111]	99	1			T256	1		T99	5		T125	4
values[112]	101	1			T256	1		T99	1		T125	6
values[113]	88	1			T256	3		T99	2		T125	7
values[114]	104	1			T256	2		T99	3		T125	14
values[115]	84	1			T256	1		T99	3		T125	9
values[116]	108	1			T256	3		T99	3		T125	8
values[117]	111	1			T256	4		T99	4		T125	6
values[118]	111	1			T256	2		T99	2		T125	4
values[119]	100	1			T256	1		T99	3		T125	4
values[120]	113	1			T256	2		T99	3		T125	2
values[121]	100	1			T256	2		T99	1		T125	4
values[122]	96	1			T256	2		T99	2		T125	5
values[123]	156	1			T256	1		T99	9		T125	11
values[124]	227	1			T256	1		T99	27		T125	9
values[125]	438	1			T256	1		T99	43		T125	16
values[126]	835	1			T256	13		T99	42		T125	49
values[127]	3208	1			T256	114		T99	33		T125	31
values[128]	5901	1			T256	205		T99	4		T127	4