Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	24	0	24	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	24	0	24	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	490	1			T36	2		T77	1		T79	1
all_values[1]	534	1			T77	1		T324	1		T261	4
all_values[2]	531	1			T49	1		T171	2		T323	1
all_values[3]	495	1			T49	1		T75	1		T171	1
all_values[4]	489	1			T73	2		T49	1		T75	1
all_values[5]	539	1			T49	1		T76	1		T77	2
all_values[6]	536	1			T49	1		T36	1		T76	1
all_values[7]	522	1			T73	1		T77	1		T171	1
all_values[8]	547	1			T8	2		T73	1		T49	2
all_values[9]	510	1			T49	1		T75	1		T36	1
all_values[10]	482	1			T8	1		T73	1		T75	1
all_values[11]	507	1			T36	1		T76	1		T324	1
all_values[12]	515	1			T49	1		T75	1		T36	1
all_values[13]	521	1			T49	3		T36	1		T76	2
all_values[14]	534	1			T73	2		T36	5		T76	1
all_values[15]	527	1			T49	1		T96	1		T36	3
all_values[16]	527	1			T73	2		T49	1		T75	1
all_values[17]	482	1			T36	2		T171	1		T323	1
all_values[18]	506	1			T49	2		T75	1		T36	1
all_values[19]	479	1			T49	1		T75	1		T36	3
all_values[20]	501	1			T49	1		T36	2		T171	2
all_values[21]	549	1			T73	1		T49	1		T36	1
all_values[22]	527	1			T73	1		T76	1		T79	1
all_values[23]	497	1			T73	1		T49	1		T75	2