Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	24	0	24	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	24	0	24	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	515	1			T71	1		T190	1		T108	1
all_values[1]	459	1			T91	1		T210	1		T108	1
all_values[2]	523	1			T73	1		T188	1		T210	1
all_values[3]	498	1			T73	1		T189	1		T190	1
all_values[4]	532	1			T73	1		T189	1		T190	2
all_values[5]	522	1			T189	1		T210	1		T108	1
all_values[6]	498	1			T210	2		T121	1		T97	2
all_values[7]	551	1			T189	1		T190	1		T108	1
all_values[8]	475	1			T73	2		T189	1		T91	1
all_values[9]	483	1			T73	2		T91	1		T230	2
all_values[10]	493	1			T176	1		T91	1		T121	1
all_values[11]	487	1			T121	3		T303	2		T355	2
all_values[12]	516	1			T190	2		T91	1		T115	1
all_values[13]	526	1			T188	1		T190	1		T230	1
all_values[14]	509	1			T73	1		T190	1		T91	2
all_values[15]	463	1			T176	1		T230	1		T115	2
all_values[16]	508	1			T91	2		T230	1		T108	2
all_values[17]	483	1			T73	1		T228	1		T45	1
all_values[18]	518	1			T188	1		T189	1		T190	1
all_values[19]	518	1			T188	2		T190	1		T91	1
all_values[20]	514	1			T190	1		T230	1		T113	1
all_values[21]	525	1			T188	1		T189	1		T190	1
all_values[22]	515	1			T189	1		T91	1		T108	2
all_values[23]	498	1			T189	2		T230	3		T108	2