Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1789	1			T17	1		T18	2		T22	4
all_values[1]	1775	1			T17	3		T18	4		T22	2
all_values[2]	1775	1			T17	2		T22	2		T113	2
all_values[3]	1813	1			T17	2		T18	5		T22	2
all_values[4]	1811	1			T17	5		T18	3		T22	1
all_values[5]	1802	1			T17	3		T18	2		T113	6
all_values[6]	1770	1			T17	2		T18	3		T113	1
all_values[7]	1855	1			T17	4		T18	5		T113	4
all_values[8]	1763	1			T17	2		T18	5		T22	1
all_values[9]	1763	1			T17	2		T18	2		T113	4
all_values[10]	1712	1			T17	3		T18	5		T113	1
all_values[11]	1843	1			T17	1		T18	3		T22	1
all_values[12]	1793	1			T17	5		T18	3		T22	2
all_values[13]	1725	1			T17	4		T18	3		T22	2
all_values[14]	1810	1			T17	6		T18	5		T22	2
all_values[15]	1708	1			T17	3		T18	5		T113	4
all_values[16]	1833	1			T17	6		T18	5		T22	1
all_values[17]	1792	1			T17	2		T18	3		T22	3
all_values[18]	1816	1			T17	3		T18	1		T22	2
all_values[19]	1793	1			T17	2		T18	5		T22	3
all_values[20]	1676	1			T18	2		T22	2		T113	3
all_values[21]	1806	1			T17	3		T18	5		T22	1
all_values[22]	1789	1			T17	2		T18	3		T113	6
all_values[23]	1745	1			T17	5		T18	1		T22	4
all_values[24]	1806	1			T17	2		T22	2		T113	1
all_values[25]	1798	1			T17	3		T18	2		T113	6
all_values[26]	1842	1			T17	2		T18	3		T113	2
all_values[27]	1760	1			T17	2		T18	4		T22	2
all_values[28]	1754	1			T17	2		T18	3		T22	2
all_values[29]	1779	1			T17	3		T18	2		T113	5
all_values[30]	1838	1			T17	3		T18	4		T22	3
all_values[31]	1784	1			T17	1		T18	4		T113	2
all_values[32]	1809	1			T17	1		T18	4		T22	4
all_values[33]	1739	1			T17	5		T18	3		T22	4
all_values[34]	1768	1			T17	2		T18	1		T22	1
all_values[35]	1776	1			T18	4		T113	3		T49	6
all_values[36]	1752	1			T17	7		T18	1		T22	1
all_values[37]	1675	1			T17	5		T18	4		T22	1
all_values[38]	1816	1			T17	8		T18	4		T22	1
all_values[39]	1768	1			T17	4		T18	4		T22	2
all_values[40]	1666	1			T17	3		T18	4		T22	6
all_values[41]	1744	1			T17	5		T18	6		T22	3
all_values[42]	1784	1			T17	3		T18	3		T22	2
all_values[43]	1739	1			T17	1		T18	4		T22	1
all_values[44]	1789	1			T17	6		T18	3		T22	1
all_values[45]	1771	1			T17	3		T18	6		T22	2
all_values[46]	1750	1			T17	1		T18	2		T22	2
all_values[47]	1721	1			T17	3		T18	1		T22	1
all_values[48]	1820	1			T17	3		T18	1		T22	4
all_values[49]	1790	1			T17	3		T113	3		T49	6
all_values[50]	1759	1			T17	3		T18	4		T22	1
all_values[51]	1773	1			T17	4		T18	2		T22	1
all_values[52]	1767	1			T17	1		T18	4		T22	1
all_values[53]	1742	1			T18	3		T22	1		T113	4
all_values[54]	1740	1			T17	2		T18	1		T22	2
all_values[55]	1766	1			T17	7		T18	1		T113	6
all_values[56]	1732	1			T17	2		T113	2		T49	2
all_values[57]	1800	1			T18	5		T113	4		T49	1
all_values[58]	1719	1			T17	5		T18	3		T113	3
all_values[59]	1706	1			T17	7		T18	2		T22	2
all_values[60]	1745	1			T17	4		T18	3		T22	1
all_values[61]	1800	1			T17	1		T18	1		T22	3
all_values[62]	1756	1			T18	4		T22	3		T113	3
all_values[63]	1778	1			T17	1		T18	2		T22	1