Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1817	1			T8	1		T15	1		T49	2
all_values[1]	1816	1			T15	3		T38	3		T39	4
all_values[2]	1821	1			T8	2		T38	1		T39	1
all_values[3]	1758	1			T8	4		T15	3		T38	5
all_values[4]	1740	1			T8	2		T15	3		T49	2
all_values[5]	1786	1			T8	2		T15	6		T38	2
all_values[6]	1880	1			T15	7		T74	1		T38	3
all_values[7]	1766	1			T8	2		T15	3		T74	1
all_values[8]	1807	1			T15	4		T74	2		T39	2
all_values[9]	1666	1			T15	1		T49	1		T74	1
all_values[10]	1788	1			T8	1		T15	3		T49	1
all_values[11]	1752	1			T15	2		T74	1		T38	2
all_values[12]	1742	1			T15	1		T74	1		T38	1
all_values[13]	1770	1			T8	2		T15	3		T49	1
all_values[14]	1871	1			T8	2		T15	1		T74	2
all_values[15]	1772	1			T8	2		T15	1		T74	3
all_values[16]	1750	1			T15	3		T38	3		T188	1
all_values[17]	1834	1			T8	1		T15	3		T74	2
all_values[18]	1807	1			T15	2		T74	2		T38	3
all_values[19]	1804	1			T8	1		T15	3		T49	1
all_values[20]	1771	1			T15	2		T38	1		T76	4
all_values[21]	1845	1			T8	1		T15	1		T74	2
all_values[22]	1865	1			T8	2		T15	6		T38	2
all_values[23]	1789	1			T8	2		T15	5		T49	1
all_values[24]	1757	1			T8	1		T15	3		T38	3
all_values[25]	1716	1			T8	1		T15	2		T49	2
all_values[26]	1783	1			T15	5		T74	1		T38	3
all_values[27]	1800	1			T8	2		T15	4		T38	2
all_values[28]	1796	1			T8	1		T15	2		T49	1
all_values[29]	1748	1			T8	2		T15	2		T38	4
all_values[30]	1759	1			T15	2		T38	1		T188	1
all_values[31]	1804	1			T15	2		T74	2		T38	1
all_values[32]	1802	1			T15	3		T74	1		T38	3
all_values[33]	1784	1			T8	4		T15	4		T74	1
all_values[34]	1819	1			T15	2		T49	1		T74	1
all_values[35]	1796	1			T8	1		T15	4		T38	4
all_values[36]	1797	1			T8	3		T15	2		T74	2
all_values[37]	1794	1			T8	1		T15	4		T74	2
all_values[38]	1814	1			T8	1		T15	2		T49	1
all_values[39]	1881	1			T8	1		T15	5		T49	1
all_values[40]	1714	1			T8	3		T15	1		T49	2
all_values[41]	1822	1			T8	2		T15	7		T49	1
all_values[42]	1811	1			T8	1		T15	4		T74	2
all_values[43]	1773	1			T8	3		T15	6		T74	1
all_values[44]	1841	1			T15	3		T49	1		T74	1
all_values[45]	1859	1			T8	1		T15	1		T74	2
all_values[46]	1793	1			T8	2		T15	3		T74	1
all_values[47]	1812	1			T8	1		T15	2		T38	1
all_values[48]	1808	1			T8	2		T15	1		T74	2
all_values[49]	1790	1			T15	1		T74	1		T38	6
all_values[50]	1745	1			T15	3		T49	1		T74	1
all_values[51]	1863	1			T8	2		T15	3		T38	3
all_values[52]	1845	1			T8	1		T15	1		T74	1
all_values[53]	1758	1			T15	2		T49	1		T74	1
all_values[54]	1706	1			T15	4		T74	1		T38	4
all_values[55]	1793	1			T8	1		T15	4		T74	2
all_values[56]	1814	1			T8	1		T15	3		T38	2
all_values[57]	1799	1			T8	1		T15	2		T49	2
all_values[58]	1783	1			T8	2		T15	5		T49	1
all_values[59]	1730	1			T8	3		T38	2		T188	1
all_values[60]	1776	1			T8	1		T15	5		T49	1
all_values[61]	1821	1			T8	1		T15	6		T49	1
all_values[62]	1756	1			T8	1		T74	1		T38	7
all_values[63]	1806	1			T8	2		T15	1		T74	1