Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2803250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

427900

1

T1

43

T2

579

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1118400	1			T1	202		T2	1458		T3	57
values[0x0]	1049750	1			T1	24		T2	1424		T3	63
values[0x1]	1063000	1			T1	178		T2	1381		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2193050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1038100

1

T1

155

T2

1372

T3

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9900	1			T2	15		T3	3		T7	15
valid_sources[0x01]	8750	1			T1	1		T2	16		T7	16
valid_sources[0x02]	6600	1			T2	18		T7	18		T5	5
valid_sources[0x03]	15850	1			T1	1		T2	15		T7	15
valid_sources[0x04]	14050	1			T1	3		T2	17		T7	17
valid_sources[0x05]	10300	1			T2	18		T3	4		T7	18
valid_sources[0x06]	9400	1			T1	2		T2	18		T7	18
valid_sources[0x07]	12500	1			T1	1		T2	18		T7	18
valid_sources[0x08]	10050	1			T1	1		T2	18		T7	18
valid_sources[0x09]	14200	1			T1	2		T2	16		T3	5
valid_sources[0x0a]	12050	1			T2	17		T7	17		T4	10
valid_sources[0x0b]	11200	1			T1	1		T2	19		T7	19
valid_sources[0x0c]	11700	1			T2	15		T7	15		T4	4
valid_sources[0x0d]	15300	1			T1	5		T2	17		T3	1
valid_sources[0x0e]	10500	1			T2	15		T7	15		T4	21
valid_sources[0x0f]	14250	1			T1	1		T2	17		T7	17
valid_sources[0x10]	12850	1			T1	2		T2	17		T7	17
valid_sources[0x11]	14750	1			T1	1		T2	12		T7	12
valid_sources[0x12]	13100	1			T1	2		T2	17		T7	17
valid_sources[0x13]	10900	1			T1	2		T2	16		T7	16
valid_sources[0x14]	10700	1			T1	2		T2	19		T7	19
valid_sources[0x15]	12950	1			T2	18		T7	18		T4	12
valid_sources[0x16]	11250	1			T2	16		T3	1		T7	16
valid_sources[0x17]	11900	1			T1	1		T2	18		T7	18
valid_sources[0x18]	14500	1			T1	1		T2	17		T7	17
valid_sources[0x19]	14050	1			T2	16		T7	16		T4	16
valid_sources[0x1a]	11400	1			T1	4		T2	19		T7	19
valid_sources[0x1b]	15150	1			T1	1		T2	19		T7	19
valid_sources[0x1c]	16100	1			T1	1		T2	17		T7	17
valid_sources[0x1d]	19350	1			T1	3		T2	18		T3	9
valid_sources[0x1e]	12500	1			T1	2		T2	15		T7	15
valid_sources[0x1f]	10400	1			T1	2		T2	15		T7	15
valid_sources[0x20]	17500	1			T1	1		T2	16		T7	16
valid_sources[0x21]	10600	1			T1	1		T2	18		T3	2
valid_sources[0x22]	11600	1			T1	1		T2	15		T7	15
valid_sources[0x23]	11250	1			T1	1		T2	18		T7	18
valid_sources[0x24]	15350	1			T2	16		T7	16		T4	5
valid_sources[0x25]	10100	1			T1	3		T2	19		T7	19
valid_sources[0x26]	12000	1			T1	2		T2	17		T7	17
valid_sources[0x27]	12650	1			T1	1		T2	16		T7	16
valid_sources[0x28]	12700	1			T1	2		T2	16		T7	16
valid_sources[0x29]	17800	1			T1	3		T2	15		T3	9
valid_sources[0x2a]	16750	1			T1	4		T2	18		T7	18
valid_sources[0x2b]	13550	1			T2	19		T7	19		T4	1
valid_sources[0x2c]	12050	1			T1	2		T2	16		T7	16
valid_sources[0x2d]	9000	1			T2	16		T7	16		T4	7
valid_sources[0x2e]	10350	1			T1	1		T2	16		T7	16
valid_sources[0x2f]	12350	1			T1	1		T2	17		T7	17
valid_sources[0x30]	12850	1			T1	1		T2	17		T7	17
valid_sources[0x31]	10300	1			T1	3		T2	15		T7	15
valid_sources[0x32]	10250	1			T1	1		T2	17		T3	1
valid_sources[0x33]	12050	1			T1	6		T2	18		T7	18
valid_sources[0x34]	14250	1			T1	3		T2	18		T7	18
valid_sources[0x35]	13450	1			T1	1		T2	15		T7	15
valid_sources[0x36]	13350	1			T2	15		T7	15		T5	5
valid_sources[0x37]	14900	1			T1	5		T2	17		T7	17
valid_sources[0x38]	15550	1			T1	1		T2	18		T3	11
valid_sources[0x39]	11650	1			T1	1		T2	16		T3	1
valid_sources[0x3a]	17650	1			T1	2		T2	18		T3	1
valid_sources[0x3b]	13400	1			T1	6		T2	14		T3	3
valid_sources[0x3c]	12850	1			T1	1		T2	17		T7	17
valid_sources[0x3d]	14000	1			T1	3		T2	17		T7	17
valid_sources[0x3e]	10450	1			T1	3		T2	17		T7	17
valid_sources[0x3f]	9150	1			T2	17		T7	17		T4	13
valid_sources[0x40]	15600	1			T1	5		T2	18		T7	18
valid_sources[0x41]	13200	1			T1	5		T2	16		T7	16
valid_sources[0x42]	13950	1			T1	1		T2	17		T7	17
valid_sources[0x43]	15800	1			T1	2		T2	17		T7	17
valid_sources[0x44]	13300	1			T2	16		T3	1		T7	16
valid_sources[0x45]	10000	1			T1	2		T2	17		T3	2
valid_sources[0x46]	17450	1			T2	19		T3	2		T7	19
valid_sources[0x47]	12400	1			T1	2		T2	17		T7	17
valid_sources[0x48]	13700	1			T1	1		T2	16		T7	16
valid_sources[0x49]	11000	1			T2	17		T3	5		T7	17
valid_sources[0x4a]	9300	1			T2	14		T7	14		T4	12
valid_sources[0x4b]	6300	1			T1	1		T2	17		T3	5
valid_sources[0x4c]	11400	1			T1	1		T2	16		T7	16
valid_sources[0x4d]	14250	1			T1	1		T2	15		T7	15
valid_sources[0x4e]	11800	1			T1	1		T2	18		T7	18
valid_sources[0x4f]	15750	1			T2	17		T7	17		T4	22
valid_sources[0x50]	10750	1			T1	3		T2	17		T3	4
valid_sources[0x51]	11200	1			T2	16		T7	16		T4	7
valid_sources[0x52]	10900	1			T1	1		T2	18		T3	1
valid_sources[0x53]	15650	1			T1	1		T2	16		T7	16
valid_sources[0x54]	15300	1			T1	1		T2	17		T7	17
valid_sources[0x55]	13800	1			T1	1		T2	17		T7	17
valid_sources[0x56]	12700	1			T2	18		T7	18		T4	14
valid_sources[0x57]	15600	1			T1	1		T2	15		T7	15
valid_sources[0x58]	13700	1			T2	18		T7	18		T4	5
valid_sources[0x59]	13600	1			T1	1		T2	16		T7	16
valid_sources[0x5a]	13150	1			T1	3		T2	15		T7	15
valid_sources[0x5b]	15050	1			T1	3		T2	15		T7	15
valid_sources[0x5c]	13500	1			T1	1		T2	18		T3	24
valid_sources[0x5d]	11100	1			T1	5		T2	15		T7	15
valid_sources[0x5e]	11650	1			T2	18		T7	18		T4	6
valid_sources[0x5f]	8800	1			T1	1		T2	18		T7	18
valid_sources[0x60]	9050	1			T1	1		T2	18		T7	18
valid_sources[0x61]	12200	1			T1	1		T2	17		T7	17
valid_sources[0x62]	12450	1			T1	1		T2	17		T7	17
valid_sources[0x63]	16300	1			T1	1		T2	13		T7	13
valid_sources[0x64]	13500	1			T1	1		T2	18		T7	18
valid_sources[0x65]	14600	1			T1	2		T2	18		T7	18
valid_sources[0x66]	12000	1			T1	1		T2	19		T7	19
valid_sources[0x67]	10800	1			T1	1		T2	14		T7	14
valid_sources[0x68]	12500	1			T1	1		T2	14		T3	1
valid_sources[0x69]	13650	1			T2	18		T3	4		T7	18
valid_sources[0x6a]	13950	1			T1	3		T2	19		T7	19
valid_sources[0x6b]	14050	1			T2	18		T7	18		T4	6
valid_sources[0x6c]	12550	1			T1	1		T2	17		T7	17
valid_sources[0x6d]	8600	1			T2	17		T7	17		T4	5
valid_sources[0x6e]	9850	1			T1	1		T2	15		T7	15
valid_sources[0x6f]	13700	1			T2	17		T7	17		T4	15
valid_sources[0x70]	13900	1			T1	1		T2	18		T7	18
valid_sources[0x71]	10550	1			T1	2		T2	16		T7	16
valid_sources[0x72]	10650	1			T2	17		T7	17		T5	3
valid_sources[0x73]	13050	1			T1	2		T2	15		T7	15
valid_sources[0x74]	12750	1			T1	1		T2	17		T3	2
valid_sources[0x75]	12850	1			T2	17		T3	2		T7	17
valid_sources[0x76]	8350	1			T1	1		T2	17		T7	17
valid_sources[0x77]	17450	1			T1	1		T2	16		T7	16
valid_sources[0x78]	12000	1			T1	3		T2	17		T7	17
valid_sources[0x79]	14100	1			T1	3		T2	16		T7	16
valid_sources[0x7a]	9800	1			T1	3		T2	16		T7	16
valid_sources[0x7b]	15100	1			T1	1		T2	17		T7	17
valid_sources[0x7c]	18500	1			T1	3		T2	19		T7	19
valid_sources[0x7d]	12950	1			T2	20		T7	20		T4	4
valid_sources[0x7e]	11500	1			T1	3		T2	16		T7	16
valid_sources[0x7f]	8900	1			T1	1		T2	18		T3	4
valid_sources[0x80]	11550	1			T1	2		T2	17		T7	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45300

1

T1

19

T2

52

T3

2

values[0x0]

all_enables

biggest_size

336250

1

T1

9

T2

465

T3

11

values[0x1]

all_enables

biggest_size

46350

1

T1

15

T2

62

T3

6