Unified Coverage Report :: Group :: xbar_env_pkg::max_delay_cg_obj::max_delay_cg

Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_aon	100.00	1	100	1	64	64
alert_handler	100.00	1	100	1	64	64
aon_timer_aon	100.00	1	100	1	64	64
ast	100.00	1	100	1	64	64
clkmgr_aon	100.00	1	100	1	64	64
gpio	100.00	1	100	1	64	64
i2c0	100.00	1	100	1	64	64
i2c1	100.00	1	100	1	64	64
i2c2	100.00	1	100	1	64	64
lc_ctrl	100.00	1	100	1	64	64
main	100.00	1	100	1	64	64
otp_ctrl__core	100.00	1	100	1	64	64
otp_ctrl__prim	100.00	1	100	1	64	64
pattgen	100.00	1	100	1	64	64
pinmux_aon	100.00	1	100	1	64	64
pwm_aon	100.00	1	100	1	64	64
pwrmgr_aon	100.00	1	100	1	64	64
rstmgr_aon	100.00	1	100	1	64	64
rv_timer	100.00	1	100	1	64	64
sensor_ctrl_aon	100.00	1	100	1	64	64
spi_device	100.00	1	100	1	64	64
sram_ctrl_ret_aon__ram	100.00	1	100	1	64	64
sram_ctrl_ret_aon__regs	100.00	1	100	1	64	64
sysrst_ctrl_aon	100.00	1	100	1	64	64
uart0	100.00	1	100	1	64	64
uart1	100.00	1	100	1	64	64
uart2	100.00	1	100	1	64	64
uart3	100.00	1	100	1	64	64

---

Group Instance : adc_ctrl_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance adc_ctrl_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : alert_handler

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance alert_handler

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance alert_handler

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : aon_timer_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance aon_timer_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance aon_timer_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : ast

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance ast

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance ast

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : clkmgr_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance clkmgr_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance clkmgr_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : gpio

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance gpio

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance gpio

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : i2c0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance i2c0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : i2c1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance i2c1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : i2c2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance i2c2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : lc_ctrl

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lc_ctrl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance lc_ctrl

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : main

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance main

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance main

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : otp_ctrl__core

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance otp_ctrl__core

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance otp_ctrl__core

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : otp_ctrl__prim

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance otp_ctrl__prim

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance otp_ctrl__prim

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : pattgen

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance pattgen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance pattgen

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : pinmux_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance pinmux_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance pinmux_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : pwm_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance pwm_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance pwm_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : pwrmgr_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance pwrmgr_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance pwrmgr_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rstmgr_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rstmgr_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rstmgr_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_timer

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_timer

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : sensor_ctrl_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sensor_ctrl_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance sensor_ctrl_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : spi_device

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance spi_device

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance spi_device

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : sram_ctrl_ret_aon__ram

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sram_ctrl_ret_aon__ram

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance sram_ctrl_ret_aon__ram

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : sram_ctrl_ret_aon__regs

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sram_ctrl_ret_aon__regs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance sram_ctrl_ret_aon__regs

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_aon

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_aon

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance sysrst_ctrl_aon

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : uart0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uart0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance uart0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : uart1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uart1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance uart1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : uart2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uart2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance uart2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : uart3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uart3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance uart3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T2	1		T3	1		T7	1
small_delay	550	1			T1	1		T5	1		T6	1
zero	100	1			T8	1		T14	1		T17	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T9	1		T21	1		T45	1
small_delay	700	1			T1	1		T2	1		T3	1
zero	100	1			T8	1		T14	1		T17	1