Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	801153300	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	801153300	0	0
T1	12289928	290895	0	0
T2	23323384	1767156	0	0
T3	9048312	260763	0	0
T4	14417480	1969906	0	0
T5	41348496	932530	0	0
T6	12289928	290895	0	0
T7	23323384	1767156	0	0
T8	323344	14534	0	0
T9	13803048	328341	0	0
T10	4222624	105357	0	0
T11	0	20751	0	0
T12	0	20751	0	0
T13	0	59547	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12289928	12265960	0	0
T2	23323384	23323328	0	0
T3	9048312	9047528	0	0
T4	14417480	14417368	0	0
T5	41348496	41346424	0	0
T6	12289928	12265960	0	0
T7	23323384	23323328	0	0
T8	323344	322560	0	0
T9	13803048	13802264	0	0
T10	4222624	4221840	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12289928	12265960	0	0
T2	23323384	23323328	0	0
T3	9048312	9047528	0	0
T4	14417480	14417368	0	0
T5	41348496	41346424	0	0
T6	12289928	12265960	0	0
T7	23323384	23323328	0	0
T8	323344	322560	0	0
T9	13803048	13802264	0	0
T10	4222624	4221840	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12289928	12265960	0	0
T2	23323384	23323328	0	0
T3	9048312	9047528	0	0
T4	14417480	14417368	0	0
T5	41348496	41346424	0	0
T6	12289928	12265960	0	0
T7	23323384	23323328	0	0
T8	323344	322560	0	0
T9	13803048	13802264	0	0
T10	4222624	4221840	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T7	56	56	0	0
T8	56	56	0	0
T9	56	56	0	0
T10	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	317816350	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	317816350	0	0
T1	219463	107484	0	0
T2	416489	19984	0	0
T3	161577	159798	0	0
T4	257455	254297	0	0
T5	738366	377949	0	0
T6	219463	107484	0	0
T7	416489	19984	0	0
T8	5774	5658	0	0
T9	246483	151131	0	0
T10	75404	27349	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	200705750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	200705750	0	0
T1	219463	60348	0	0
T2	416489	157131	0	0
T3	161577	50110	0	0
T4	257455	851986	0	0
T5	738366	189577	0	0
T6	219463	60348	0	0
T7	416489	157131	0	0
T8	5774	2960	0	0
T9	246483	55494	0	0
T10	75404	25337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3594950	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3594950	0	0
T1	219463	6187	0	0
T2	416489	2221	0	0
T3	161577	45	0	0
T4	257455	460	0	0
T5	738366	5794	0	0
T6	219463	6187	0	0
T7	416489	2221	0	0
T8	5774	110	0	0
T9	246483	1649	0	0
T10	75404	3033	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	14202400	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	14202400	0	0
T1	219463	6043	0	0
T2	416489	179935	0	0
T3	161577	2374	0	0
T4	257455	32078	0	0
T5	738366	5524	0	0
T6	219463	6043	0	0
T7	416489	179935	0	0
T8	5774	110	0	0
T9	246483	1817	0	0
T10	75404	3021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2604600	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2604600	0	0
T1	219463	911	0	0
T2	416489	1039	0	0
T3	161577	27	0	0
T4	257455	418	0	0
T5	738366	4750	0	0
T6	219463	911	0	0
T7	416489	1039	0	0
T8	5774	99	0	0
T9	246483	1866	0	0
T10	75404	1222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	8114750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	8114750	0	0
T1	219463	907	0	0
T2	416489	81825	0	0
T3	161577	2002	0	0
T4	257455	29526	0	0
T5	738366	4481	0	0
T6	219463	907	0	0
T7	416489	81825	0	0
T8	5774	99	0	0
T9	246483	1839	0	0
T10	75404	1389	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2847450	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2847450	0	0
T1	219463	1147	0	0
T2	416489	1207	0	0
T3	161577	21	0	0
T4	257455	443	0	0
T5	738366	6482	0	0
T6	219463	1147	0	0
T7	416489	1207	0	0
T8	5774	93	0	0
T9	246483	1929	0	0
T10	75404	1837	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	8387750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	8387750	0	0
T1	219463	1032	0	0
T2	416489	94472	0	0
T3	161577	878	0	0
T4	257455	27295	0	0
T5	738366	6174	0	0
T6	219463	1032	0	0
T7	416489	94472	0	0
T8	5774	93	0	0
T9	246483	1994	0	0
T10	75404	1429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3103500	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3103500	0	0
T1	219463	1115	0	0
T2	416489	0	0	0
T3	161577	37	0	0
T4	257455	464	0	0
T5	738366	11220	0	0
T6	219463	1115	0	0
T7	416489	0	0	0
T8	5774	116	0	0
T9	246483	832	0	0
T10	75404	0	0	0
T11	0	877	0	0
T12	0	877	0	0
T13	0	1115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4389150	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4389150	0	0
T1	219463	936	0	0
T2	416489	0	0	0
T3	161577	2046	0	0
T4	257455	28137	0	0
T5	738366	9800	0	0
T6	219463	936	0	0
T7	416489	0	0	0
T8	5774	116	0	0
T9	246483	1221	0	0
T10	75404	0	0	0
T11	0	722	0	0
T12	0	722	0	0
T13	0	936	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3455200	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3455200	0	0
T1	219463	6490	0	0
T2	416489	925	0	0
T3	161577	32	0	0
T4	257455	467	0	0
T5	738366	6387	0	0
T6	219463	6490	0	0
T7	416489	925	0	0
T8	5774	109	0	0
T9	246483	1121	0	0
T10	75404	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	8546450	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	8546450	0	0
T1	219463	4779	0	0
T2	416489	82042	0	0
T3	161577	825	0	0
T4	257455	31223	0	0
T5	738366	6017	0	0
T6	219463	4779	0	0
T7	416489	82042	0	0
T8	5774	109	0	0
T9	246483	192	0	0
T10	75404	1188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3042050	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3042050	0	0
T1	219463	4372	0	0
T2	416489	0	0	0
T3	161577	32	0	0
T4	257455	511	0	0
T5	738366	4259	0	0
T6	219463	4372	0	0
T7	416489	0	0	0
T8	5774	120	0	0
T9	246483	2529	0	0
T10	75404	0	0	0
T11	0	916	0	0
T12	0	916	0	0
T13	0	4372	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4832650	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4832650	0	0
T1	219463	3686	0	0
T2	416489	0	0	0
T3	161577	3217	0	0
T4	257455	39993	0	0
T5	738366	4117	0	0
T6	219463	3686	0	0
T7	416489	0	0	0
T8	5774	120	0	0
T9	246483	1490	0	0
T10	75404	0	0	0
T11	0	747	0	0
T12	0	747	0	0
T13	0	3686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3203050	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3203050	0	0
T1	219463	1117	0	0
T2	416489	0	0	0
T3	161577	13	0	0
T4	257455	417	0	0
T5	738366	11684	0	0
T6	219463	1117	0	0
T7	416489	0	0	0
T8	5774	106	0	0
T9	246483	1693	0	0
T10	75404	0	0	0
T11	0	805	0	0
T12	0	805	0	0
T13	0	1117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4209800	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4209800	0	0
T1	219463	1082	0	0
T2	416489	0	0	0
T3	161577	880	0	0
T4	257455	25805	0	0
T5	738366	10446	0	0
T6	219463	1082	0	0
T7	416489	0	0	0
T8	5774	106	0	0
T9	246483	857	0	0
T10	75404	0	0	0
T11	0	728	0	0
T12	0	728	0	0
T13	0	1082	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3261250	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3261250	0	0
T1	219463	2448	0	0
T2	416489	0	0	0
T3	161577	22	0	0
T4	257455	465	0	0
T5	738366	7966	0	0
T6	219463	2448	0	0
T7	416489	0	0	0
T8	5774	99	0	0
T9	246483	1766	0	0
T10	75404	0	0	0
T11	0	746	0	0
T12	0	746	0	0
T13	0	2448	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4371150	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4371150	0	0
T1	219463	2307	0	0
T2	416489	0	0	0
T3	161577	1555	0	0
T4	257455	30667	0	0
T5	738366	7845	0	0
T6	219463	2307	0	0
T7	416489	0	0	0
T8	5774	99	0	0
T9	246483	589	0	0
T10	75404	0	0	0
T11	0	866	0	0
T12	0	866	0	0
T13	0	2307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3093500	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3093500	0	0
T1	219463	1305	0	0
T2	416489	1141	0	0
T3	161577	36	0	0
T4	257455	455	0	0
T5	738366	5934	0	0
T6	219463	1305	0	0
T7	416489	1141	0	0
T8	5774	116	0	0
T9	246483	6132	0	0
T10	75404	1408	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	9734800	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	9734800	0	0
T1	219463	1214	0	0
T2	416489	104929	0	0
T3	161577	2487	0	0
T4	257455	33730	0	0
T5	738366	5293	0	0
T6	219463	1214	0	0
T7	416489	104929	0	0
T8	5774	116	0	0
T9	246483	4685	0	0
T10	75404	1601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2598300	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2598300	0	0
T1	219463	1190	0	0
T2	416489	0	0	0
T3	161577	40	0	0
T4	257455	504	0	0
T5	738366	4378	0	0
T6	219463	1190	0	0
T7	416489	0	0	0
T8	5774	121	0	0
T9	246483	4026	0	0
T10	75404	0	0	0
T11	0	864	0	0
T12	0	864	0	0
T13	0	1190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4389550	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4389550	0	0
T1	219463	1026	0	0
T2	416489	0	0	0
T3	161577	3955	0	0
T4	257455	33443	0	0
T5	738366	4096	0	0
T6	219463	1026	0	0
T7	416489	0	0	0
T8	5774	121	0	0
T9	246483	4435	0	0
T10	75404	0	0	0
T11	0	873	0	0
T12	0	873	0	0
T13	0	1026	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3566000	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3566000	0	0
T1	219463	2656	0	0
T2	416489	983	0	0
T3	161577	61	0	0
T4	257455	484	0	0
T5	738366	10539	0	0
T6	219463	2656	0	0
T7	416489	983	0	0
T8	5774	123	0	0
T9	246483	4202	0	0
T10	75404	1116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	8845950	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	8845950	0	0
T1	219463	2502	0	0
T2	416489	83141	0	0
T3	161577	2424	0	0
T4	257455	30525	0	0
T5	738366	9668	0	0
T6	219463	2502	0	0
T7	416489	83141	0	0
T8	5774	123	0	0
T9	246483	3234	0	0
T10	75404	1105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3734850	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3734850	0	0
T1	219463	2812	0	0
T2	416489	2226	0	0
T3	161577	10	0	0
T4	257455	517	0	0
T5	738366	9345	0	0
T6	219463	2812	0	0
T7	416489	2226	0	0
T8	5774	116	0	0
T9	246483	2140	0	0
T10	75404	2749	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	14106250	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	14106250	0	0
T1	219463	2953	0	0
T2	416489	181605	0	0
T3	161577	113	0	0
T4	257455	35776	0	0
T5	738366	8580	0	0
T6	219463	2953	0	0
T7	416489	181605	0	0
T8	5774	116	0	0
T9	246483	1239	0	0
T10	75404	2751	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3412150	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3412150	0	0
T1	219463	1064	0	0
T2	416489	0	0	0
T3	161577	26	0	0
T4	257455	500	0	0
T5	738366	10450	0	0
T6	219463	1064	0	0
T7	416489	0	0	0
T8	5774	116	0	0
T9	246483	1921	0	0
T10	75404	0	0	0
T11	0	930	0	0
T12	0	930	0	0
T13	0	1064	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4695150	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4695150	0	0
T1	219463	1055	0	0
T2	416489	0	0	0
T3	161577	1690	0	0
T4	257455	36296	0	0
T5	738366	8768	0	0
T6	219463	1055	0	0
T7	416489	0	0	0
T8	5774	116	0	0
T9	246483	2406	0	0
T10	75404	0	0	0
T11	0	724	0	0
T12	0	724	0	0
T13	0	1055	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2971600	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2971600	0	0
T1	219463	1155	0	0
T2	416489	968	0	0
T3	161577	9	0	0
T4	257455	511	0	0
T5	738366	4356	0	0
T6	219463	1155	0	0
T7	416489	968	0	0
T8	5774	116	0	0
T9	246483	315	0	0
T10	75404	1279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	7491800	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	7491800	0	0
T1	219463	1083	0	0
T2	416489	76677	0	0
T3	161577	53	0	0
T4	257455	27146	0	0
T5	738366	4058	0	0
T6	219463	1083	0	0
T7	416489	76677	0	0
T8	5774	116	0	0
T9	246483	554	0	0
T10	75404	1285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2729900	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2729900	0	0
T1	219463	1076	0	0
T2	416489	1238	0	0
T3	161577	23	0	0
T4	257455	447	0	0
T5	738366	6061	0	0
T6	219463	1076	0	0
T7	416489	1238	0	0
T8	5774	90	0	0
T9	246483	1104	0	0
T10	75404	1593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	8715950	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	8715950	0	0
T1	219463	1025	0	0
T2	416489	96054	0	0
T3	161577	2441	0	0
T4	257455	29136	0	0
T5	738366	5443	0	0
T6	219463	1025	0	0
T7	416489	96054	0	0
T8	5774	90	0	0
T9	246483	2268	0	0
T10	75404	1509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3535750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3535750	0	0
T1	219463	5217	0	0
T2	416489	0	0	0
T3	161577	28	0	0
T4	257455	561	0	0
T5	738366	6072	0	0
T6	219463	5217	0	0
T7	416489	0	0	0
T8	5774	123	0	0
T9	246483	1290	0	0
T10	75404	0	0	0
T11	0	1009	0	0
T12	0	1009	0	0
T13	0	5217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	5085000	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	5085000	0	0
T1	219463	3934	0	0
T2	416489	0	0	0
T3	161577	1849	0	0
T4	257455	39938	0	0
T5	738366	5685	0	0
T6	219463	3934	0	0
T7	416489	0	0	0
T8	5774	123	0	0
T9	246483	1717	0	0
T10	75404	0	0	0
T11	0	897	0	0
T12	0	897	0	0
T13	0	3934	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3203250	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3203250	0	0
T1	219463	1056	0	0
T2	416489	0	0	0
T3	161577	36	0	0
T4	257455	458	0	0
T5	738366	8852	0	0
T6	219463	1056	0	0
T7	416489	0	0	0
T8	5774	117	0	0
T9	246483	2036	0	0
T10	75404	0	0	0
T11	0	762	0	0
T12	0	762	0	0
T13	0	1056	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4800050	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4800050	0	0
T1	219463	973	0	0
T2	416489	0	0	0
T3	161577	2206	0	0
T4	257455	29376	0	0
T5	738366	7468	0	0
T6	219463	973	0	0
T7	416489	0	0	0
T8	5774	117	0	0
T9	246483	2426	0	0
T10	75404	0	0	0
T11	0	743	0	0
T12	0	743	0	0
T13	0	973	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3031050	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3031050	0	0
T1	219463	2532	0	0
T2	416489	1301	0	0
T3	161577	28	0	0
T4	257455	474	0	0
T5	738366	7269	0	0
T6	219463	2532	0	0
T7	416489	1301	0	0
T8	5774	108	0	0
T9	246483	3689	0	0
T10	75404	1738	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	10641150	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	10641150	0	0
T1	219463	2383	0	0
T2	416489	112154	0	0
T3	161577	2140	0	0
T4	257455	33149	0	0
T5	738366	7294	0	0
T6	219463	2383	0	0
T7	416489	112154	0	0
T8	5774	108	0	0
T9	246483	2996	0	0
T10	75404	1997	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2711200	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2711200	0	0
T1	219463	2897	0	0
T2	416489	0	0	0
T3	161577	24	0	0
T4	257455	438	0	0
T5	738366	4287	0	0
T6	219463	2897	0	0
T7	416489	0	0	0
T8	5774	109	0	0
T9	246483	1505	0	0
T10	75404	0	0	0
T11	0	931	0	0
T12	0	931	0	0
T13	0	2897	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4041250	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4041250	0	0
T1	219463	2256	0	0
T2	416489	0	0	0
T3	161577	1817	0	0
T4	257455	32591	0	0
T5	738366	3895	0	0
T6	219463	2256	0	0
T7	416489	0	0	0
T8	5774	109	0	0
T9	246483	1001	0	0
T10	75404	0	0	0
T11	0	738	0	0
T12	0	738	0	0
T13	0	2256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3696000	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3696000	0	0
T1	219463	4818	0	0
T2	416489	0	0	0
T3	161577	38	0	0
T4	257455	484	0	0
T5	738366	8112	0	0
T6	219463	4818	0	0
T7	416489	0	0	0
T8	5774	97	0	0
T9	246483	3793	0	0
T10	75404	0	0	0
T11	0	736	0	0
T12	0	736	0	0
T13	0	4818	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	5096750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	5096750	0	0
T1	219463	3756	0	0
T2	416489	0	0	0
T3	161577	6705	0	0
T4	257455	26311	0	0
T5	738366	6910	0	0
T6	219463	3756	0	0
T7	416489	0	0	0
T8	5774	97	0	0
T9	246483	4977	0	0
T10	75404	0	0	0
T11	0	631	0	0
T12	0	631	0	0
T13	0	3756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2921300	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2921300	0	0
T1	219463	1116	0	0
T2	416489	0	0	0
T3	161577	20	0	0
T4	257455	521	0	0
T5	738366	6315	0	0
T6	219463	1116	0	0
T7	416489	0	0	0
T8	5774	127	0	0
T9	246483	1995	0	0
T10	75404	0	0	0
T11	0	893	0	0
T12	0	893	0	0
T13	0	1116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4643800	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4643800	0	0
T1	219463	1018	0	0
T2	416489	0	0	0
T3	161577	335	0	0
T4	257455	39255	0	0
T5	738366	5652	0	0
T6	219463	1018	0	0
T7	416489	0	0	0
T8	5774	127	0	0
T9	246483	1529	0	0
T10	75404	0	0	0
T11	0	864	0	0
T12	0	864	0	0
T13	0	1018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3070500	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3070500	0	0
T1	219463	954	0	0
T2	416489	1015	0	0
T3	161577	32	0	0
T4	257455	392	0	0
T5	738366	6065	0	0
T6	219463	954	0	0
T7	416489	1015	0	0
T8	5774	105	0	0
T9	246483	3177	0	0
T10	75404	1676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	7763750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	7763750	0	0
T1	219463	738	0	0
T2	416489	73630	0	0
T3	161577	1750	0	0
T4	257455	27508	0	0
T5	738366	5193	0	0
T6	219463	738	0	0
T7	416489	73630	0	0
T8	5774	105	0	0
T9	246483	1785	0	0
T10	75404	1285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3342950	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3342950	0	0
T1	219463	2578	0	0
T2	416489	2021	0	0
T3	161577	8	0	0
T4	257455	446	0	0
T5	738366	6692	0	0
T6	219463	2578	0	0
T7	416489	2021	0	0
T8	5774	121	0	0
T9	246483	2718	0	0
T10	75404	2515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	12372100	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	12372100	0	0
T1	219463	2621	0	0
T2	416489	156934	0	0
T3	161577	896	0	0
T4	257455	33035	0	0
T5	738366	6111	0	0
T6	219463	2621	0	0
T7	416489	156934	0	0
T8	5774	121	0	0
T9	246483	1826	0	0
T10	75404	2718	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2858900	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2858900	0	0
T1	219463	2285	0	0
T2	416489	2142	0	0
T3	161577	36	0	0
T4	257455	431	0	0
T5	738366	4653	0	0
T6	219463	2285	0	0
T7	416489	2142	0	0
T8	5774	98	0	0
T9	246483	3412	0	0
T10	75404	3708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	12423800	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	12423800	0	0
T1	219463	1986	0	0
T2	416489	169637	0	0
T3	161577	1463	0	0
T4	257455	28152	0	0
T5	738366	4315	0	0
T6	219463	1986	0	0
T7	416489	169637	0	0
T8	5774	98	0	0
T9	246483	2493	0	0
T10	75404	2899	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3147400	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3147400	0	0
T1	219463	2935	0	0
T2	416489	0	0	0
T3	161577	24	0	0
T4	257455	381	0	0
T5	738366	9519	0	0
T6	219463	2935	0	0
T7	416489	0	0	0
T8	5774	97	0	0
T9	246483	3164	0	0
T10	75404	0	0	0
T11	0	679	0	0
T12	0	679	0	0
T13	0	2935	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3922800	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3922800	0	0
T1	219463	2381	0	0
T2	416489	0	0	0
T3	161577	1111	0	0
T4	257455	29437	0	0
T5	738366	7488	0	0
T6	219463	2381	0	0
T7	416489	0	0	0
T8	5774	97	0	0
T9	246483	960	0	0
T10	75404	0	0	0
T11	0	582	0	0
T12	0	582	0	0
T13	0	2381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	3085050	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	3085050	0	0
T1	219463	2962	0	0
T2	416489	0	0	0
T3	161577	24	0	0
T4	257455	426	0	0
T5	738366	7202	0	0
T6	219463	2962	0	0
T7	416489	0	0	0
T8	5774	104	0	0
T9	246483	3481	0	0
T10	75404	0	0	0
T11	0	747	0	0
T12	0	747	0	0
T13	0	2962	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	4101200	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	4101200	0	0
T1	219463	2830	0	0
T2	416489	0	0	0
T3	161577	146	0	0
T4	257455	32095	0	0
T5	738366	6758	0	0
T6	219463	2830	0	0
T7	416489	0	0	0
T8	5774	104	0	0
T9	246483	2337	0	0
T10	75404	0	0	0
T11	0	741	0	0
T12	0	741	0	0
T13	0	2830	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	2883550	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	2883550	0	0
T1	219463	1109	0	0
T2	416489	930	0	0
T3	161577	13	0	0
T4	257455	454	0	0
T5	738366	7097	0	0
T6	219463	1109	0	0
T7	416489	930	0	0
T8	5774	102	0	0
T9	246483	2737	0	0
T10	75404	1810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	665093250	8000750	0	0
DepthKnown_A	665093250	665036850	0	0
RvalidKnown_A	665093250	665036850	0	0
WreadyKnown_A	665093250	665036850	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	8000750	0	0
T1	219463	1053	0	0
T2	416489	77649	0	0
T3	161577	2752	0	0
T4	257455	29471	0	0
T5	738366	6185	0	0
T6	219463	1053	0	0
T7	416489	77649	0	0
T8	5774	102	0	0
T9	246483	2627	0	0
T10	75404	1147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665093250	665036850	0	0
T1	219463	219035	0	0
T2	416489	416488	0	0
T3	161577	161563	0	0
T4	257455	257453	0	0
T5	738366	738329	0	0
T6	219463	219035	0	0
T7	416489	416488	0	0
T8	5774	5760	0	0
T9	246483	246469	0	0
T10	75404	75390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0