Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1505009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236919

1

T1

709

T2

78

T4

176

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	589524	1			T1	1627		T2	350		T4	435
values[0x0]	560911	1			T1	1656		T2	55		T4	459
values[0x1]	591493	1			T1	1732		T2	353		T4	465

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1165527	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

576401

1

T1

1619

T2

277

T4

440

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6404	1			T1	19		T2	3		T4	18
valid_sources[0x01]	7307	1			T1	20		T2	3		T5	4
valid_sources[0x02]	8305	1			T1	21		T2	5		T4	20
valid_sources[0x03]	6689	1			T1	19		T2	2		T5	10
valid_sources[0x04]	7408	1			T1	20		T2	3		T4	12
valid_sources[0x05]	6522	1			T1	21		T2	5		T5	5
valid_sources[0x06]	7195	1			T1	19		T2	4		T3	20
valid_sources[0x07]	6320	1			T1	17		T2	1		T5	11
valid_sources[0x08]	6935	1			T1	23		T2	3		T3	7
valid_sources[0x09]	6714	1			T1	22		T2	2		T5	3
valid_sources[0x0a]	7184	1			T1	18		T3	10		T5	8
valid_sources[0x0b]	6566	1			T1	20		T2	3		T3	25
valid_sources[0x0c]	7714	1			T1	21		T2	4		T4	13
valid_sources[0x0d]	7140	1			T1	20		T2	5		T3	5
valid_sources[0x0e]	7071	1			T1	17		T2	5		T4	15
valid_sources[0x0f]	7588	1			T1	20		T2	7		T4	21
valid_sources[0x10]	6548	1			T1	16		T2	3		T4	16
valid_sources[0x11]	7182	1			T1	19		T2	2		T5	3
valid_sources[0x12]	6703	1			T1	21		T2	2		T3	38
valid_sources[0x13]	6271	1			T1	20		T2	1		T5	4
valid_sources[0x14]	7098	1			T1	18		T2	4		T3	10
valid_sources[0x15]	6657	1			T1	16		T2	4		T4	5
valid_sources[0x16]	7525	1			T1	20		T2	3		T4	5
valid_sources[0x17]	6885	1			T1	21		T2	5		T4	13
valid_sources[0x18]	6499	1			T1	20		T2	2		T4	6
valid_sources[0x19]	6805	1			T1	20		T2	1		T4	9
valid_sources[0x1a]	6635	1			T1	21		T2	5		T4	18
valid_sources[0x1b]	6900	1			T1	19		T2	5		T4	20
valid_sources[0x1c]	6727	1			T1	19		T2	3		T4	16
valid_sources[0x1d]	7086	1			T1	20		T2	4		T5	4
valid_sources[0x1e]	7296	1			T1	21		T2	1		T5	4
valid_sources[0x1f]	6671	1			T1	18		T3	36		T5	8
valid_sources[0x20]	6312	1			T1	20		T2	7		T5	7
valid_sources[0x21]	6629	1			T1	20		T2	6		T4	8
valid_sources[0x22]	7677	1			T1	20		T3	11		T5	10
valid_sources[0x23]	5964	1			T1	19		T2	1		T5	3
valid_sources[0x24]	6785	1			T1	19		T2	2		T3	35
valid_sources[0x25]	7069	1			T1	23		T2	4		T4	13
valid_sources[0x26]	6248	1			T1	19		T2	1		T4	19
valid_sources[0x27]	6995	1			T1	20		T2	7		T4	15
valid_sources[0x28]	8875	1			T1	21		T2	2		T4	15
valid_sources[0x29]	7566	1			T1	22		T2	5		T3	43
valid_sources[0x2a]	6507	1			T1	18		T2	3		T4	17
valid_sources[0x2b]	7447	1			T1	20		T2	4		T4	18
valid_sources[0x2c]	6787	1			T1	21		T2	3		T3	18
valid_sources[0x2d]	6829	1			T1	22		T2	3		T3	19
valid_sources[0x2e]	6569	1			T1	21		T2	3		T4	20
valid_sources[0x2f]	6045	1			T1	19		T2	1		T5	5
valid_sources[0x30]	6446	1			T1	19		T2	4		T5	7
valid_sources[0x31]	7038	1			T1	21		T2	1		T3	6
valid_sources[0x32]	6249	1			T1	18		T2	4		T5	2
valid_sources[0x33]	7158	1			T1	20		T3	12		T5	7
valid_sources[0x34]	6512	1			T1	20		T2	1		T3	24
valid_sources[0x35]	6206	1			T1	18		T2	3		T4	18
valid_sources[0x36]	7248	1			T1	21		T2	4		T4	5
valid_sources[0x37]	6732	1			T1	20		T2	4		T5	4
valid_sources[0x38]	6902	1			T1	20		T2	1		T5	3
valid_sources[0x39]	6339	1			T1	20		T4	24		T5	8
valid_sources[0x3a]	6816	1			T1	19		T2	2		T5	7
valid_sources[0x3b]	7631	1			T1	18		T2	2		T5	4
valid_sources[0x3c]	7074	1			T1	21		T2	2		T3	13
valid_sources[0x3d]	8294	1			T1	19		T2	2		T3	29
valid_sources[0x3e]	6658	1			T1	20		T5	4		T6	5
valid_sources[0x3f]	7055	1			T1	20		T2	4		T3	21
valid_sources[0x40]	6787	1			T1	19		T2	1		T5	8
valid_sources[0x41]	7214	1			T1	21		T2	1		T5	2
valid_sources[0x42]	6431	1			T1	19		T2	1		T4	7
valid_sources[0x43]	6588	1			T1	21		T2	2		T3	16
valid_sources[0x44]	6640	1			T1	21		T2	4		T5	3
valid_sources[0x45]	6091	1			T1	18		T2	4		T4	16
valid_sources[0x46]	6471	1			T1	20		T2	3		T3	15
valid_sources[0x47]	6589	1			T1	21		T2	2		T5	6
valid_sources[0x48]	6981	1			T1	18		T2	2		T5	5
valid_sources[0x49]	6762	1			T1	19		T2	3		T3	11
valid_sources[0x4a]	8346	1			T1	20		T2	1		T5	7
valid_sources[0x4b]	7265	1			T1	18		T2	3		T4	19
valid_sources[0x4c]	6909	1			T1	19		T2	1		T5	9
valid_sources[0x4d]	6880	1			T1	21		T2	3		T4	14
valid_sources[0x4e]	6995	1			T1	19		T2	3		T5	4
valid_sources[0x4f]	6056	1			T1	21		T2	1		T3	17
valid_sources[0x50]	6268	1			T1	19		T2	5		T5	3
valid_sources[0x51]	6852	1			T1	19		T2	3		T4	6
valid_sources[0x52]	6896	1			T1	18		T2	1		T3	7
valid_sources[0x53]	6218	1			T1	20		T2	7		T3	12
valid_sources[0x54]	6820	1			T1	19		T2	7		T3	29
valid_sources[0x55]	6707	1			T1	20		T2	3		T5	5
valid_sources[0x56]	6714	1			T1	20		T2	3		T4	26
valid_sources[0x57]	6371	1			T1	21		T2	2		T4	12
valid_sources[0x58]	6378	1			T1	17		T2	4		T4	14
valid_sources[0x59]	6597	1			T1	21		T2	1		T5	4
valid_sources[0x5a]	6637	1			T1	21		T2	2		T3	27
valid_sources[0x5b]	6972	1			T1	20		T2	2		T5	9
valid_sources[0x5c]	6499	1			T1	17		T2	2		T3	5
valid_sources[0x5d]	6591	1			T1	20		T2	3		T3	20
valid_sources[0x5e]	8096	1			T1	21		T4	20		T5	4
valid_sources[0x5f]	6875	1			T1	19		T2	2		T4	8
valid_sources[0x60]	6828	1			T1	22		T3	9		T5	4
valid_sources[0x61]	6522	1			T1	23		T2	3		T5	4
valid_sources[0x62]	6127	1			T1	20		T2	4		T5	2
valid_sources[0x63]	9193	1			T1	20		T2	1		T4	16
valid_sources[0x64]	6516	1			T1	19		T2	6		T5	2
valid_sources[0x65]	6617	1			T1	20		T2	5		T5	9
valid_sources[0x66]	7060	1			T1	19		T2	2		T5	5
valid_sources[0x67]	6881	1			T1	22		T2	2		T5	5
valid_sources[0x68]	6617	1			T1	21		T2	4		T5	3
valid_sources[0x69]	6881	1			T1	21		T5	4		T6	2
valid_sources[0x6a]	7298	1			T1	21		T2	4		T5	11
valid_sources[0x6b]	6638	1			T1	20		T2	4		T5	3
valid_sources[0x6c]	6908	1			T1	22		T2	6		T5	3
valid_sources[0x6d]	6930	1			T1	19		T2	4		T3	21
valid_sources[0x6e]	6674	1			T1	17		T2	2		T4	18
valid_sources[0x6f]	7963	1			T1	20		T2	5		T5	11
valid_sources[0x70]	6127	1			T1	18		T2	6		T4	13
valid_sources[0x71]	6709	1			T1	19		T2	5		T5	7
valid_sources[0x72]	7318	1			T1	19		T2	1		T5	6
valid_sources[0x73]	6140	1			T1	19		T2	7		T4	15
valid_sources[0x74]	6402	1			T1	20		T2	4		T3	5
valid_sources[0x75]	7042	1			T1	21		T2	3		T5	4
valid_sources[0x76]	6971	1			T1	19		T2	5		T4	26
valid_sources[0x77]	6846	1			T1	19		T2	3		T3	11
valid_sources[0x78]	8005	1			T1	19		T2	1		T4	16
valid_sources[0x79]	7348	1			T1	20		T2	2		T4	19
valid_sources[0x7a]	6478	1			T1	20		T2	3		T3	19
valid_sources[0x7b]	6374	1			T1	19		T2	3		T3	13
valid_sources[0x7c]	6262	1			T1	19		T2	2		T5	6
valid_sources[0x7d]	6601	1			T1	19		T2	4		T5	1
valid_sources[0x7e]	6365	1			T1	19		T2	2		T4	17
valid_sources[0x7f]	6548	1			T1	17		T2	3		T4	18
valid_sources[0x80]	6224	1			T1	20		T2	3		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25254

1

T1

73

T2

30

T4

13

values[0x0]

all_enables

biggest_size

186370

1

T1

572

T2

27

T4

144

values[0x1]

all_enables

biggest_size

25295

1

T1

64

T2

21

T4

19