Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	335357693	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335357693	0	0
T1	13770240	2007078	0	0
T2	23281608	524675	0	0
T3	3846304	54148	0	0
T4	180656	5418	0	0
T5	180040	6712	0	0
T6	159264	6004	0	0
T15	10028952	119718	0	0
T16	0	30	0	0
T17	191016	5898	0	0
T18	4537568	126360	0	0
T19	241976	10558	0	0
T20	2793448	72188	0	0
T21	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24097920	24097584	0	0
T2	23281608	23276344	0	0
T3	3846304	3843280	0	0
T4	180656	176008	0	0
T5	180040	174496	0	0
T6	159264	155120	0	0
T17	191016	186816	0	0
T18	4537568	4536784	0	0
T19	241976	240856	0	0
T20	2793448	2791880	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24097920	24097584	0	0
T2	23281608	23276344	0	0
T3	3846304	3843280	0	0
T4	180656	176008	0	0
T5	180040	174496	0	0
T6	159264	155120	0	0
T17	191016	186816	0	0
T18	4537568	4536784	0	0
T19	241976	240856	0	0
T20	2793448	2791880	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24097920	24097584	0	0
T2	23281608	23276344	0	0
T3	3846304	3843280	0	0
T4	180656	176008	0	0
T5	180040	174496	0	0
T6	159264	155120	0	0
T17	191016	186816	0	0
T18	4537568	4536784	0	0
T19	241976	240856	0	0
T20	2793448	2791880	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	124262586	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	124262586	0	0
T1	430320	22692	0	0
T2	415743	199399	0	0
T3	68684	14467	0	0
T4	3226	1359	0	0
T5	3215	2609	0	0
T6	2844	2346	0	0
T17	3411	1475	0	0
T18	81028	30491	0	0
T19	4321	4104	0	0
T20	49883	29756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	87304556	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	87304556	0	0
T1	430320	178336	0	0
T2	415743	100884	0	0
T3	68684	12637	0	0
T4	3226	1359	0	0
T5	3215	1369	0	0
T6	2844	1220	0	0
T17	3411	1475	0	0
T18	81028	32689	0	0
T19	4321	2152	0	0
T20	49883	14092	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1383443	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1383443	0	0
T1	430320	2001	0	0
T2	415743	4509	0	0
T3	68684	529	0	0
T4	3226	49	0	0
T5	3215	48	0	0
T6	2844	42	0	0
T15	0	2740	0	0
T17	3411	43	0	0
T18	81028	0	0	0
T19	4321	91	0	0
T20	49883	404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3480764	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3480764	0	0
T1	430320	155885	0	0
T2	415743	3485	0	0
T3	68684	485	0	0
T4	3226	49	0	0
T5	3215	48	0	0
T6	2844	42	0	0
T15	0	1733	0	0
T17	3411	43	0	0
T18	81028	0	0	0
T19	4321	91	0	0
T20	49883	436	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1383241	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1383241	0	0
T1	430320	2123	0	0
T2	415743	4337	0	0
T3	68684	611	0	0
T4	3226	53	0	0
T5	3215	45	0	0
T6	2844	55	0	0
T17	3411	47	0	0
T18	81028	2538	0	0
T19	4321	76	0	0
T20	49883	617	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3249267	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3249267	0	0
T1	430320	162137	0	0
T2	415743	3142	0	0
T3	68684	552	0	0
T4	3226	53	0	0
T5	3215	45	0	0
T6	2844	55	0	0
T17	3411	47	0	0
T18	81028	2326	0	0
T19	4321	76	0	0
T20	49883	551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1344454	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1344454	0	0
T1	430320	1026	0	0
T2	415743	5744	0	0
T3	68684	486	0	0
T4	3226	47	0	0
T5	3215	52	0	0
T6	2844	51	0	0
T15	0	2576	0	0
T17	3411	53	0	0
T18	81028	0	0	0
T19	4321	96	0	0
T20	49883	676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2981248	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2981248	0	0
T1	430320	78690	0	0
T2	415743	5412	0	0
T3	68684	422	0	0
T4	3226	47	0	0
T5	3215	52	0	0
T6	2844	51	0	0
T15	0	1598	0	0
T17	3411	53	0	0
T18	81028	0	0	0
T19	4321	96	0	0
T20	49883	674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1329694	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1329694	0	0
T1	430320	1190	0	0
T2	415743	7609	0	0
T3	68684	729	0	0
T4	3226	48	0	0
T5	3215	46	0	0
T6	2844	43	0	0
T15	0	4081	0	0
T17	3411	43	0	0
T18	81028	0	0	0
T19	4321	78	0	0
T20	49883	535	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2577773	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2577773	0	0
T1	430320	96226	0	0
T2	415743	6831	0	0
T3	68684	623	0	0
T4	3226	48	0	0
T5	3215	46	0	0
T6	2844	43	0	0
T15	0	2132	0	0
T17	3411	43	0	0
T18	81028	0	0	0
T19	4321	78	0	0
T20	49883	604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1441163	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1441163	0	0
T1	430320	1158	0	0
T2	415743	8312	0	0
T3	68684	646	0	0
T4	3226	71	0	0
T5	3215	59	0	0
T6	2844	55	0	0
T17	3411	66	0	0
T18	81028	2362	0	0
T19	4321	69	0	0
T20	49883	496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2964830	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2964830	0	0
T1	430320	84088	0	0
T2	415743	5987	0	0
T3	68684	559	0	0
T4	3226	71	0	0
T5	3215	59	0	0
T6	2844	55	0	0
T17	3411	66	0	0
T18	81028	2275	0	0
T19	4321	69	0	0
T20	49883	490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1355972	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1355972	0	0
T2	415743	6025	0	0
T3	68684	416	0	0
T4	3226	53	0	0
T5	3215	49	0	0
T6	2844	56	0	0
T15	417873	2589	0	0
T17	3411	60	0	0
T18	81028	2393	0	0
T19	4321	69	0	0
T20	49883	470	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2781728	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2781728	0	0
T2	415743	4377	0	0
T3	68684	442	0	0
T4	3226	53	0	0
T5	3215	49	0	0
T6	2844	56	0	0
T15	417873	1649	0	0
T17	3411	60	0	0
T18	81028	2369	0	0
T19	4321	69	0	0
T20	49883	515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1375166	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1375166	0	0
T2	415743	4196	0	0
T3	68684	436	0	0
T4	3226	56	0	0
T5	3215	62	0	0
T6	2844	38	0	0
T15	417873	3813	0	0
T17	3411	53	0	0
T18	81028	1501	0	0
T19	4321	71	0	0
T20	49883	645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2544001	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2544001	0	0
T2	415743	3228	0	0
T3	68684	391	0	0
T4	3226	56	0	0
T5	3215	62	0	0
T6	2844	38	0	0
T15	417873	2680	0	0
T17	3411	53	0	0
T18	81028	1863	0	0
T19	4321	71	0	0
T20	49883	624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1422639	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1422639	0	0
T1	430320	1009	0	0
T2	415743	4125	0	0
T3	68684	565	0	0
T4	3226	48	0	0
T5	3215	53	0	0
T6	2844	54	0	0
T15	0	3917	0	0
T17	3411	51	0	0
T18	81028	0	0	0
T19	4321	68	0	0
T20	49883	591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2845626	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2845626	0	0
T1	430320	83271	0	0
T2	415743	3017	0	0
T3	68684	439	0	0
T4	3226	48	0	0
T5	3215	53	0	0
T6	2844	54	0	0
T15	0	2477	0	0
T17	3411	51	0	0
T18	81028	0	0	0
T19	4321	68	0	0
T20	49883	488	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1408921	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1408921	0	0
T2	415743	5526	0	0
T3	68684	426	0	0
T4	3226	56	0	0
T5	3215	51	0	0
T6	2844	47	0	0
T15	417873	4674	0	0
T17	3411	60	0	0
T18	81028	0	0	0
T19	4321	85	0	0
T20	49883	560	0	0
T21	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3072606	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3072606	0	0
T2	415743	4179	0	0
T3	68684	420	0	0
T4	3226	56	0	0
T5	3215	51	0	0
T6	2844	47	0	0
T15	417873	2612	0	0
T17	3411	60	0	0
T18	81028	0	0	0
T19	4321	85	0	0
T20	49883	479	0	0
T21	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1357704	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1357704	0	0
T1	430320	1312	0	0
T2	415743	4198	0	0
T3	68684	611	0	0
T4	3226	44	0	0
T5	3215	57	0	0
T6	2844	39	0	0
T17	3411	57	0	0
T18	81028	1530	0	0
T19	4321	87	0	0
T20	49883	682	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3330136	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3330136	0	0
T1	430320	93693	0	0
T2	415743	3182	0	0
T3	68684	549	0	0
T4	3226	44	0	0
T5	3215	57	0	0
T6	2844	39	0	0
T17	3411	57	0	0
T18	81028	2168	0	0
T19	4321	87	0	0
T20	49883	608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1351148	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1351148	0	0
T1	430320	1142	0	0
T2	415743	1613	0	0
T3	68684	593	0	0
T4	3226	37	0	0
T5	3215	43	0	0
T6	2844	45	0	0
T17	3411	50	0	0
T18	81028	1888	0	0
T19	4321	91	0	0
T20	49883	463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3846194	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3846194	0	0
T1	430320	93616	0	0
T2	415743	1474	0	0
T3	68684	551	0	0
T4	3226	37	0	0
T5	3215	43	0	0
T6	2844	45	0	0
T17	3411	50	0	0
T18	81028	1761	0	0
T19	4321	91	0	0
T20	49883	355	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1377856	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1377856	0	0
T2	415743	1944	0	0
T3	68684	560	0	0
T4	3226	43	0	0
T5	3215	64	0	0
T6	2844	47	0	0
T15	417873	2293	0	0
T16	0	2	0	0
T17	3411	51	0	0
T18	81028	0	0	0
T19	4321	67	0	0
T20	49883	465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3321507	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3321507	0	0
T2	415743	1654	0	0
T3	68684	435	0	0
T4	3226	43	0	0
T5	3215	64	0	0
T6	2844	47	0	0
T15	417873	1427	0	0
T16	0	2	0	0
T17	3411	51	0	0
T18	81028	0	0	0
T19	4321	67	0	0
T20	49883	522	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1391126	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1391126	0	0
T2	415743	5653	0	0
T3	68684	472	0	0
T4	3226	53	0	0
T5	3215	53	0	0
T6	2844	38	0	0
T15	417873	7435	0	0
T16	0	4	0	0
T17	3411	45	0	0
T18	81028	0	0	0
T19	4321	85	0	0
T20	49883	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3558871	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3558871	0	0
T2	415743	4822	0	0
T3	68684	374	0	0
T4	3226	53	0	0
T5	3215	53	0	0
T6	2844	38	0	0
T15	417873	3428	0	0
T16	0	4	0	0
T17	3411	45	0	0
T18	81028	0	0	0
T19	4321	85	0	0
T20	49883	451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1376806	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1376806	0	0
T1	430320	2227	0	0
T2	415743	3765	0	0
T3	68684	592	0	0
T4	3226	45	0	0
T5	3215	44	0	0
T6	2844	38	0	0
T17	3411	59	0	0
T18	81028	1955	0	0
T19	4321	86	0	0
T20	49883	468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3010550	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3010550	0	0
T1	430320	176023	0	0
T2	415743	2978	0	0
T3	68684	518	0	0
T4	3226	45	0	0
T5	3215	44	0	0
T6	2844	38	0	0
T17	3411	59	0	0
T18	81028	1915	0	0
T19	4321	86	0	0
T20	49883	523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1357427	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1357427	0	0
T2	415743	3708	0	0
T3	68684	513	0	0
T4	3226	49	0	0
T5	3215	55	0	0
T6	2844	45	0	0
T15	417873	4028	0	0
T17	3411	50	0	0
T18	81028	4481	0	0
T19	4321	74	0	0
T20	49883	593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2873829	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2873829	0	0
T2	415743	2927	0	0
T3	68684	460	0	0
T4	3226	49	0	0
T5	3215	55	0	0
T6	2844	45	0	0
T15	417873	2834	0	0
T17	3411	50	0	0
T18	81028	5870	0	0
T19	4321	74	0	0
T20	49883	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1397999	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1397999	0	0
T1	430320	2449	0	0
T2	415743	4334	0	0
T3	68684	513	0	0
T4	3226	38	0	0
T5	3215	41	0	0
T6	2844	48	0	0
T17	3411	47	0	0
T18	81028	2141	0	0
T19	4321	74	0	0
T20	49883	561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3870499	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3870499	0	0
T1	430320	194804	0	0
T2	415743	3256	0	0
T3	68684	415	0	0
T4	3226	38	0	0
T5	3215	41	0	0
T6	2844	48	0	0
T17	3411	47	0	0
T18	81028	2096	0	0
T19	4321	74	0	0
T20	49883	554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1383994	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1383994	0	0
T1	430320	1275	0	0
T2	415743	1999	0	0
T3	68684	586	0	0
T4	3226	54	0	0
T5	3215	54	0	0
T6	2844	44	0	0
T17	3411	70	0	0
T18	81028	2449	0	0
T19	4321	83	0	0
T20	49883	486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2809231	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2809231	0	0
T1	430320	109711	0	0
T2	415743	1675	0	0
T3	68684	529	0	0
T4	3226	54	0	0
T5	3215	54	0	0
T6	2844	44	0	0
T17	3411	70	0	0
T18	81028	2069	0	0
T19	4321	83	0	0
T20	49883	455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1420375	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1420375	0	0
T2	415743	3636	0	0
T3	68684	514	0	0
T4	3226	50	0	0
T5	3215	52	0	0
T6	2844	43	0	0
T15	417873	5711	0	0
T17	3411	54	0	0
T18	81028	1626	0	0
T19	4321	93	0	0
T20	49883	604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3212617	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3212617	0	0
T2	415743	2998	0	0
T3	68684	416	0	0
T4	3226	50	0	0
T5	3215	52	0	0
T6	2844	43	0	0
T15	417873	3440	0	0
T17	3411	54	0	0
T18	81028	2176	0	0
T19	4321	93	0	0
T20	49883	592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1416579	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1416579	0	0
T2	415743	1707	0	0
T3	68684	533	0	0
T4	3226	49	0	0
T5	3215	47	0	0
T6	2844	48	0	0
T15	417873	2587	0	0
T17	3411	60	0	0
T18	81028	1605	0	0
T19	4321	65	0	0
T20	49883	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	4279811	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	4279811	0	0
T2	415743	1425	0	0
T3	68684	493	0	0
T4	3226	49	0	0
T5	3215	47	0	0
T6	2844	48	0	0
T15	417873	1465	0	0
T17	3411	60	0	0
T18	81028	1852	0	0
T19	4321	65	0	0
T20	49883	530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1412095	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1412095	0	0
T1	430320	2646	0	0
T2	415743	4975	0	0
T3	68684	488	0	0
T4	3226	50	0	0
T5	3215	50	0	0
T6	2844	44	0	0
T17	3411	59	0	0
T18	81028	1852	0	0
T19	4321	69	0	0
T20	49883	546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3953746	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3953746	0	0
T1	430320	205159	0	0
T2	415743	4299	0	0
T3	68684	335	0	0
T4	3226	50	0	0
T5	3215	50	0	0
T6	2844	44	0	0
T17	3411	59	0	0
T18	81028	1876	0	0
T19	4321	69	0	0
T20	49883	532	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1426043	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1426043	0	0
T1	430320	1042	0	0
T2	415743	5563	0	0
T3	68684	698	0	0
T4	3226	38	0	0
T5	3215	46	0	0
T6	2844	36	0	0
T15	0	8616	0	0
T17	3411	45	0	0
T18	81028	0	0	0
T19	4321	71	0	0
T20	49883	445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3311856	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3311856	0	0
T1	430320	79233	0	0
T2	415743	4573	0	0
T3	68684	593	0	0
T4	3226	38	0	0
T5	3215	46	0	0
T6	2844	36	0	0
T15	0	4267	0	0
T17	3411	45	0	0
T18	81028	0	0	0
T19	4321	71	0	0
T20	49883	444	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1420209	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1420209	0	0
T2	415743	2050	0	0
T3	68684	495	0	0
T4	3226	45	0	0
T5	3215	45	0	0
T6	2844	34	0	0
T15	417873	5755	0	0
T16	0	2	0	0
T17	3411	65	0	0
T18	81028	0	0	0
T19	4321	75	0	0
T20	49883	513	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2857920	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2857920	0	0
T2	415743	1693	0	0
T3	68684	423	0	0
T4	3226	45	0	0
T5	3215	45	0	0
T6	2844	34	0	0
T15	417873	3491	0	0
T16	0	2	0	0
T17	3411	65	0	0
T18	81028	0	0	0
T19	4321	75	0	0
T20	49883	548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1382473	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1382473	0	0
T2	415743	6962	0	0
T3	68684	511	0	0
T4	3226	56	0	0
T5	3215	48	0	0
T6	2844	39	0	0
T15	417873	4687	0	0
T17	3411	71	0	0
T18	81028	0	0	0
T19	4321	84	0	0
T20	49883	411	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3329958	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3329958	0	0
T2	415743	6046	0	0
T3	68684	414	0	0
T4	3226	56	0	0
T5	3215	48	0	0
T6	2844	39	0	0
T15	417873	2497	0	0
T17	3411	71	0	0
T18	81028	0	0	0
T19	4321	84	0	0
T20	49883	404	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1365269	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1365269	0	0
T1	430320	1171	0	0
T2	415743	4794	0	0
T3	68684	400	0	0
T4	3226	54	0	0
T5	3215	47	0	0
T6	2844	55	0	0
T17	3411	46	0	0
T18	81028	2170	0	0
T19	4321	92	0	0
T20	49883	515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2504676	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2504676	0	0
T1	430320	93655	0	0
T2	415743	4219	0	0
T3	68684	456	0	0
T4	3226	54	0	0
T5	3215	47	0	0
T6	2844	55	0	0
T17	3411	46	0	0
T18	81028	2073	0	0
T19	4321	92	0	0
T20	49883	561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1353715	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1353715	0	0
T2	415743	5150	0	0
T3	68684	546	0	0
T4	3226	51	0	0
T5	3215	58	0	0
T6	2844	42	0	0
T15	417873	2291	0	0
T16	0	2	0	0
T17	3411	54	0	0
T18	81028	0	0	0
T19	4321	90	0	0
T20	49883	511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3563663	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3563663	0	0
T2	415743	4481	0	0
T3	68684	465	0	0
T4	3226	51	0	0
T5	3215	58	0	0
T6	2844	42	0	0
T15	417873	1609	0	0
T16	0	2	0	0
T17	3411	54	0	0
T18	81028	0	0	0
T19	4321	90	0	0
T20	49883	580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1405036	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1405036	0	0
T1	430320	920	0	0
T2	415743	7054	0	0
T3	68684	506	0	0
T4	3226	52	0	0
T5	3215	49	0	0
T6	2844	43	0	0
T15	0	4563	0	0
T17	3411	54	0	0
T18	81028	0	0	0
T19	4321	94	0	0
T20	49883	582	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	3298019	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	3298019	0	0
T1	430320	77168	0	0
T2	415743	6328	0	0
T3	68684	428	0	0
T4	3226	52	0	0
T5	3215	49	0	0
T6	2844	43	0	0
T15	0	2399	0	0
T17	3411	54	0	0
T18	81028	0	0	0
T19	4321	94	0	0
T20	49883	569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	1341098	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	1341098	0	0
T2	415743	4140	0	0
T3	68684	478	0	0
T4	3226	61	0	0
T5	3215	49	0	0
T6	2844	50	0	0
T15	417873	3568	0	0
T16	0	5	0	0
T17	3411	61	0	0
T18	81028	0	0	0
T19	4321	68	0	0
T20	49883	493	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299867560	2977980	0	0
DepthKnown_A	299867560	299747072	0	0
RvalidKnown_A	299867560	299747072	0	0
WreadyKnown_A	299867560	299747072	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	2977980	0	0
T2	415743	3076	0	0
T3	68684	404	0	0
T4	3226	61	0	0
T5	3215	49	0	0
T6	2844	50	0	0
T15	417873	2056	0	0
T16	0	5	0	0
T17	3411	61	0	0
T18	81028	0	0	0
T19	4321	68	0	0
T20	49883	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299867560	299747072	0	0
T1	430320	430314	0	0
T2	415743	415649	0	0
T3	68684	68630	0	0
T4	3226	3143	0	0
T5	3215	3116	0	0
T6	2844	2770	0	0
T17	3411	3336	0	0
T18	81028	81014	0	0
T19	4321	4301	0	0
T20	49883	49855	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0