Unified Coverage Report :: Module :: tlul_socket_1n

Module : tlul_socket_1n

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.28	100.00	93.10			100.00	100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28	98.28	100.00	93.10			100.00	100.00

---

Module Instance : tb.dut.u_s1n_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.28	100.00	93.10			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	100.00	95.02			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_h	100.00	100.00	100.00			100.00	100.00
gen_dfifo[0].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[10].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[11].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[12].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[13].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[14].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[15].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[16].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[17].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[18].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[19].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[1].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[20].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[21].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[22].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[23].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[24].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[25].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[26].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[2].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[3].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[4].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[5].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[6].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[7].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[8].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[9].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_err_resp.err_resp	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_socket_1n

	Line No.	Total	Covered	Percent
TOTAL		340	340	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
ALWAYS	178	6	6	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	4	4	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
122	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
			MISSING_ELSE
130	1	1
143	1	1
153	27	27
155	27	27
156	27	27
157	27	27
158	27	27
159	27	27
160	27	27
161	27	27
162	27	27
165	27	27
169	27	27
178	1	1
179	1	1
181	2	2
			MISSING_ELSE
183	2	2
			MISSING_ELSE
187	1	1
190	1	1
191	1	1
192	2	2
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
228	1	1
229	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1

---

Cond Coverage for Module : tlul_socket_1n

	Total	Covered	Percent
Conditions	348	324	93.10
Logical	348	324	93.10
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       130
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(0))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(1))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(2)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(2))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(3)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(3))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(4)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(4))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(5)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(5))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(6)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(6))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(7)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(7))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(8)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(8))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(9)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(9))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(10)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(10))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(11)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(11))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(12)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(12))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(13)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(13))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(14)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(14))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(15)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(15))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(16)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(16))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(17)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(17))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(18)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(18))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(19)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(19))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(20)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(20))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(21)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(21))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(22)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(22))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(23)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(23))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(24)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(24))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       153
 EXPRESSION ((dev_select_t == 5'(25)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(25))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION ((dev_select_t == 5'(26)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 5'(26))
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[4].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[5].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[6].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[7].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[8].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[9].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[10].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[11].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[12].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[13].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[14].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[15].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T7,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[16].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[17].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[18].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[19].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[20].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[21].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T9
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[22].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[23].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[24].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[25].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[26].dev_select)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[24].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       162
 EXPRESSION (gen_u_o[25].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       162
 EXPRESSION (gen_u_o[26].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[24].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       165
 EXPRESSION (gen_u_o[25].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       165
 EXPRESSION (gen_u_o[26].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T3

 LINE       181
 EXPRESSION (dev_select_t == 5'(idx))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       187
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       192
 EXPRESSION (dev_select_outstanding == 5'(idx))
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       229
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 5'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T2,T15,T16
1	1	1	Covered	T1,T2,T4

---

Branch Coverage for Module : tlul_socket_1n

	Line No.	Total	Covered	Percent
Branches		119	119	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
IF	116	5	5	100.00
IF	181	2	2	100.00
IF	183	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[2].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[2].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[3].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[3].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[4].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[4].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[5].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[5].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[6].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[6].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[7].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[7].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[8].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[8].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[9].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[9].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[10].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[10].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[11].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[11].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[12].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[12].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[13].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[13].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[14].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[14].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[15].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[15].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[16].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[16].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[17].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[17].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[18].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[18].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[19].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[19].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[20].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[20].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[21].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[21].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[22].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[22].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[23].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[23].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[24].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[24].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[25].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[25].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	162	(gen_u_o[26].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	165	(gen_u_o[26].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	116	if ((!rst_ni))
-2-:	119	if (accept_t_req)
-3-:	120	if ((!accept_t_rsp))
-4-:	125	if (accept_t_rsp)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T4
0	1	1	-	Covered	T1,T2,T4
0	1	0	-	Covered	T1,T2,T5
0	0	-	1	Covered	T1,T2,T4
0	0	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	181	if ((dev_select_t == 5'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	183	if (hold_all_requests)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	192	if ((dev_select_outstanding == 5'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Module : tlul_socket_1n

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NotOverflowed_A	2788848	2788848	0	0
maxN	900	900	0	0

NotOverflowed_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788848	2788848	0	0
T1	4995	4995	0	0
T2	15881	15881	0	0
T3	1809	1809	0	0
T4	1359	1359	0	0
T5	1249	1249	0	0
T6	1134	1134	0	0
T17	1475	1475	0	0
T18	3899	3899	0	0
T19	1966	1966	0	0
T20	1851	1851	0	0

maxN

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0