Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1859553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

293396

1

T1

279

T4

194

T2

444

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	727889	1			T1	692		T4	468		T2	1113
values[0x0]	696652	1			T1	678		T4	473		T2	1148
values[0x1]	728408	1			T1	687		T4	432		T2	1123

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1441114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

711835

1

T1

645

T4

427

T2

1083

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8126	1			T4	9		T3	36		T5	9
valid_sources[0x01]	9007	1			T1	153		T3	11		T5	12
valid_sources[0x02]	8364	1			T3	17		T15	14		T19	12
valid_sources[0x03]	8355	1			T3	20		T5	10		T7	4
valid_sources[0x04]	8643	1			T3	30		T15	17		T19	6
valid_sources[0x05]	7451	1			T3	6		T15	9		T19	9
valid_sources[0x06]	7525	1			T3	9		T5	15		T7	3
valid_sources[0x07]	8219	1			T3	16		T8	3		T15	8
valid_sources[0x08]	8513	1			T3	29		T8	2		T15	14
valid_sources[0x09]	7802	1			T4	13		T5	5		T7	3
valid_sources[0x0a]	8179	1			T1	1		T4	10		T8	1
valid_sources[0x0b]	8380	1			T5	6		T15	5		T19	7
valid_sources[0x0c]	8054	1			T3	34		T5	36		T8	8
valid_sources[0x0d]	8222	1			T4	11		T3	5		T15	16
valid_sources[0x0e]	7585	1			T4	10		T3	7		T5	11
valid_sources[0x0f]	8723	1			T15	7		T19	8		T17	46
valid_sources[0x10]	8548	1			T4	19		T8	5		T15	12
valid_sources[0x11]	7568	1			T4	37		T3	16		T8	7
valid_sources[0x12]	10573	1			T4	15		T8	3		T15	11
valid_sources[0x13]	7874	1			T4	8		T8	3		T15	5
valid_sources[0x14]	7930	1			T5	20		T15	7		T19	6
valid_sources[0x15]	7649	1			T4	37		T5	17		T6	1
valid_sources[0x16]	8034	1			T4	17		T5	16		T15	2
valid_sources[0x17]	8632	1			T4	13		T5	22		T6	1
valid_sources[0x18]	8088	1			T3	10		T5	16		T15	12
valid_sources[0x19]	8049	1			T4	22		T15	13		T19	6
valid_sources[0x1a]	8913	1			T2	257		T5	18		T8	4
valid_sources[0x1b]	7795	1			T4	7		T3	17		T5	7
valid_sources[0x1c]	7514	1			T15	5		T19	9		T17	34
valid_sources[0x1d]	7865	1			T5	12		T8	7		T15	9
valid_sources[0x1e]	8323	1			T5	11		T7	1		T8	5
valid_sources[0x1f]	9452	1			T3	11		T5	18		T15	12
valid_sources[0x20]	8785	1			T4	17		T5	11		T8	6
valid_sources[0x21]	7944	1			T3	9		T5	15		T8	3
valid_sources[0x22]	8412	1			T4	8		T3	5		T8	2
valid_sources[0x23]	8640	1			T4	17		T3	14		T5	38
valid_sources[0x24]	8654	1			T5	20		T8	2		T15	9
valid_sources[0x25]	7922	1			T8	6		T15	6		T19	3
valid_sources[0x26]	8388	1			T3	15		T8	4		T15	9
valid_sources[0x27]	8217	1			T3	14		T5	27		T7	2
valid_sources[0x28]	8785	1			T4	11		T3	35		T8	6
valid_sources[0x29]	8712	1			T4	12		T3	8		T15	8
valid_sources[0x2a]	8768	1			T4	7		T3	17		T5	7
valid_sources[0x2b]	8169	1			T5	13		T6	1		T7	1
valid_sources[0x2c]	8396	1			T4	5		T5	6		T8	6
valid_sources[0x2d]	7928	1			T3	11		T5	10		T7	2
valid_sources[0x2e]	8533	1			T1	145		T4	12		T8	4
valid_sources[0x2f]	7757	1			T4	19		T3	18		T5	24
valid_sources[0x30]	8367	1			T5	9		T8	1		T15	8
valid_sources[0x31]	8603	1			T2	127		T15	16		T19	2
valid_sources[0x32]	7731	1			T5	9		T8	6		T15	8
valid_sources[0x33]	8933	1			T5	14		T15	13		T19	14
valid_sources[0x34]	8079	1			T3	24		T5	17		T8	8
valid_sources[0x35]	8686	1			T1	64		T3	5		T15	9
valid_sources[0x36]	8794	1			T4	9		T2	414		T3	32
valid_sources[0x37]	8654	1			T15	9		T19	6		T17	37
valid_sources[0x38]	7484	1			T3	10		T7	3		T8	2
valid_sources[0x39]	8364	1			T4	16		T7	1		T8	3
valid_sources[0x3a]	7819	1			T5	19		T15	5		T19	3
valid_sources[0x3b]	8256	1			T3	20		T6	1		T7	1
valid_sources[0x3c]	9214	1			T1	77		T4	9		T3	16
valid_sources[0x3d]	9045	1			T5	5		T7	4		T8	4
valid_sources[0x3e]	8003	1			T3	19		T5	19		T15	10
valid_sources[0x3f]	7347	1			T4	19		T15	9		T19	17
valid_sources[0x40]	9363	1			T8	7		T15	11		T19	8
valid_sources[0x41]	8113	1			T5	8		T8	1		T15	12
valid_sources[0x42]	8090	1			T4	11		T5	27		T15	9
valid_sources[0x43]	10970	1			T5	6		T7	1		T15	11
valid_sources[0x44]	7909	1			T4	7		T7	7		T15	10
valid_sources[0x45]	8174	1			T3	18		T5	8		T7	1
valid_sources[0x46]	7813	1			T8	4		T15	12		T19	6
valid_sources[0x47]	8059	1			T8	2		T15	8		T19	13
valid_sources[0x48]	9497	1			T15	11		T19	5		T17	23
valid_sources[0x49]	9110	1			T4	21		T8	2		T15	11
valid_sources[0x4a]	8680	1			T3	16		T5	23		T8	1
valid_sources[0x4b]	8620	1			T1	45		T4	13		T3	10
valid_sources[0x4c]	8092	1			T3	17		T15	13		T19	28
valid_sources[0x4d]	9797	1			T3	5		T5	5		T7	6
valid_sources[0x4e]	8680	1			T3	28		T5	10		T8	16
valid_sources[0x4f]	8016	1			T5	28		T8	5		T15	13
valid_sources[0x50]	7776	1			T8	7		T15	13		T19	6
valid_sources[0x51]	8457	1			T5	5		T15	14		T19	10
valid_sources[0x52]	7884	1			T8	5		T15	11		T19	7
valid_sources[0x53]	10774	1			T3	15		T5	20		T8	7
valid_sources[0x54]	8239	1			T5	13		T8	2		T15	14
valid_sources[0x55]	8416	1			T2	112		T5	8		T8	2
valid_sources[0x56]	8490	1			T5	13		T15	11		T19	7
valid_sources[0x57]	8056	1			T3	23		T5	22		T15	9
valid_sources[0x58]	9204	1			T3	18		T8	3		T15	10
valid_sources[0x59]	7880	1			T1	22		T5	21		T6	1
valid_sources[0x5a]	8460	1			T3	14		T15	8		T19	10
valid_sources[0x5b]	8394	1			T7	1		T15	8		T19	8
valid_sources[0x5c]	9649	1			T4	6		T3	17		T8	8
valid_sources[0x5d]	7572	1			T3	5		T5	16		T7	1
valid_sources[0x5e]	8373	1			T4	13		T3	15		T5	28
valid_sources[0x5f]	7707	1			T5	42		T7	2		T8	6
valid_sources[0x60]	9232	1			T4	12		T8	4		T15	11
valid_sources[0x61]	8112	1			T1	44		T2	130		T7	1
valid_sources[0x62]	7939	1			T3	41		T5	7		T8	8
valid_sources[0x63]	8369	1			T5	20		T7	1		T8	7
valid_sources[0x64]	8093	1			T4	11		T7	2		T8	3
valid_sources[0x65]	8390	1			T3	19		T5	18		T6	1
valid_sources[0x66]	7394	1			T4	10		T5	16		T7	1
valid_sources[0x67]	8940	1			T5	11		T15	19		T19	16
valid_sources[0x68]	8605	1			T4	21		T5	18		T8	1
valid_sources[0x69]	8633	1			T4	17		T3	15		T5	13
valid_sources[0x6a]	8457	1			T3	31		T5	9		T8	2
valid_sources[0x6b]	8338	1			T4	6		T3	20		T5	16
valid_sources[0x6c]	8952	1			T3	12		T15	14		T19	13
valid_sources[0x6d]	8814	1			T1	219		T7	3		T15	12
valid_sources[0x6e]	8490	1			T4	5		T5	18		T15	11
valid_sources[0x6f]	8892	1			T7	1		T8	7		T15	6
valid_sources[0x70]	7916	1			T1	85		T3	20		T5	12
valid_sources[0x71]	7949	1			T4	11		T3	10		T5	5
valid_sources[0x72]	8254	1			T1	147		T5	29		T15	15
valid_sources[0x73]	8331	1			T4	25		T5	27		T15	8
valid_sources[0x74]	7754	1			T3	10		T5	31		T8	4
valid_sources[0x75]	7860	1			T3	31		T5	22		T8	6
valid_sources[0x76]	8222	1			T4	10		T15	12		T19	10
valid_sources[0x77]	7851	1			T5	5		T8	5		T15	11
valid_sources[0x78]	10143	1			T5	20		T8	1		T15	11
valid_sources[0x79]	7752	1			T4	17		T3	8		T8	4
valid_sources[0x7a]	7834	1			T4	12		T8	4		T15	6
valid_sources[0x7b]	8252	1			T4	9		T5	48		T8	2
valid_sources[0x7c]	9196	1			T8	3		T15	10		T19	9
valid_sources[0x7d]	8547	1			T1	15		T4	16		T3	11
valid_sources[0x7e]	8066	1			T5	22		T8	1		T15	12
valid_sources[0x7f]	8458	1			T4	8		T3	7		T5	9
valid_sources[0x80]	8020	1			T5	21		T15	6		T19	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30829

1

T1

32

T4

11

T2

37

values[0x0]

all_enables

biggest_size

231637

1

T1

226

T4

157

T2

358

values[0x1]

all_enables

biggest_size

30930

1

T1

21

T4

26

T2

49