Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	345676873	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345676873	0	0
T1	251776	10117	0	0
T2	210616	13534	0	0
T3	4236008	61028	0	0
T4	171192	5466	0	0
T5	5042912	75306	0	0
T6	320936	5302	0	0
T7	9159080	169753	0	0
T8	959504	19007	0	0
T15	11530624	1424882	0	0
T16	0	3202	0	0
T18	190008	3455	0	0
T19	0	190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	251776	247800	0	0
T2	210616	207480	0	0
T3	4236008	4234496	0	0
T4	171192	168616	0	0
T5	5042912	5038936	0	0
T6	320936	304808	0	0
T7	9159080	9156840	0	0
T8	959504	956816	0	0
T15	11530624	11530176	0	0
T18	190008	186256	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	251776	247800	0	0
T2	210616	207480	0	0
T3	4236008	4234496	0	0
T4	171192	168616	0	0
T5	5042912	5038936	0	0
T6	320936	304808	0	0
T7	9159080	9156840	0	0
T8	959504	956816	0	0
T15	11530624	11530176	0	0
T18	190008	186256	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	251776	247800	0	0
T2	210616	207480	0	0
T3	4236008	4234496	0	0
T4	171192	168616	0	0
T5	5042912	5038936	0	0
T6	320936	304808	0	0
T7	9159080	9156840	0	0
T8	959504	956816	0	0
T15	11530624	11530176	0	0
T18	190008	186256	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T7	56	56	0	0
T8	56	56	0	0
T15	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	130475161	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	130475161	0	0
T1	4496	3946	0	0
T2	3761	3386	0	0
T3	75643	15031	0	0
T4	3057	1373	0	0
T5	90052	18563	0	0
T6	5731	2422	0	0
T7	163555	84846	0	0
T8	17134	8826	0	0
T15	205904	202030	0	0
T18	3393	1582	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	87156644	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	87156644	0	0
T1	4496	2057	0	0
T2	3761	3384	0	0
T3	75643	15486	0	0
T4	3057	1373	0	0
T5	90052	19101	0	0
T6	5731	653	0	0
T7	163555	16197	0	0
T8	17134	2274	0	0
T15	205904	605873	0	0
T18	3393	419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1534001	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1534001	0	0
T1	4496	84	0	0
T2	3761	255	0	0
T3	75643	452	0	0
T4	3057	40	0	0
T5	90052	583	0	0
T6	5731	40	0	0
T7	163555	1236	0	0
T8	17134	201	0	0
T15	205904	315	0	0
T18	3393	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3181355	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3181355	0	0
T1	4496	84	0	0
T2	3761	255	0	0
T3	75643	470	0	0
T4	3057	40	0	0
T5	90052	647	0	0
T6	5731	15	0	0
T7	163555	119	0	0
T8	17134	67	0	0
T15	205904	15462	0	0
T18	3393	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1549139	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1549139	0	0
T1	4496	88	0	0
T2	3761	0	0	0
T3	75643	504	0	0
T4	3057	62	0	0
T5	90052	587	0	0
T6	5731	99	0	0
T7	163555	2498	0	0
T8	17134	216	0	0
T15	205904	538	0	0
T16	0	103	0	0
T18	3393	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3369122	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3369122	0	0
T1	4496	88	0	0
T2	3761	0	0	0
T3	75643	529	0	0
T4	3057	62	0	0
T5	90052	635	0	0
T6	5731	35	0	0
T7	163555	1227	0	0
T8	17134	97	0	0
T15	205904	26897	0	0
T16	0	112	0	0
T18	3393	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1526124	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1526124	0	0
T1	4496	66	0	0
T2	3761	0	0	0
T3	75643	537	0	0
T4	3057	57	0	0
T5	90052	708	0	0
T6	5731	251	0	0
T7	163555	911	0	0
T8	17134	145	0	0
T15	205904	314	0	0
T16	0	85	0	0
T18	3393	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3308593	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3308593	0	0
T1	4496	66	0	0
T2	3761	0	0	0
T3	75643	603	0	0
T4	3057	57	0	0
T5	90052	623	0	0
T6	5731	73	0	0
T7	163555	430	0	0
T8	17134	70	0	0
T15	205904	17250	0	0
T16	0	89	0	0
T18	3393	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1562096	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1562096	0	0
T1	4496	68	0	0
T2	3761	261	0	0
T3	75643	502	0	0
T4	3057	39	0	0
T5	90052	672	0	0
T6	5731	26	0	0
T7	163555	1512	0	0
T8	17134	158	0	0
T15	205904	448	0	0
T18	3393	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3091238	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3091238	0	0
T1	4496	68	0	0
T2	3761	261	0	0
T3	75643	598	0	0
T4	3057	39	0	0
T5	90052	606	0	0
T6	5731	6	0	0
T7	163555	306	0	0
T8	17134	65	0	0
T15	205904	23366	0	0
T18	3393	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1538926	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1538926	0	0
T1	4496	75	0	0
T2	3761	0	0	0
T3	75643	558	0	0
T4	3057	49	0	0
T5	90052	598	0	0
T6	5731	77	0	0
T7	163555	2593	0	0
T8	17134	214	0	0
T15	205904	334	0	0
T16	0	77	0	0
T18	3393	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3374624	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3374624	0	0
T1	4496	75	0	0
T2	3761	0	0	0
T3	75643	582	0	0
T4	3057	49	0	0
T5	90052	723	0	0
T6	5731	38	0	0
T7	163555	731	0	0
T8	17134	100	0	0
T15	205904	17678	0	0
T16	0	82	0	0
T18	3393	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1540572	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1540572	0	0
T1	4496	74	0	0
T2	3761	0	0	0
T3	75643	546	0	0
T4	3057	64	0	0
T5	90052	850	0	0
T6	5731	69	0	0
T7	163555	1016	0	0
T8	17134	305	0	0
T15	205904	423	0	0
T16	0	88	0	0
T18	3393	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3029543	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3029543	0	0
T1	4496	74	0	0
T2	3761	0	0	0
T3	75643	481	0	0
T4	3057	64	0	0
T5	90052	845	0	0
T6	5731	19	0	0
T7	163555	658	0	0
T8	17134	128	0	0
T15	205904	23695	0	0
T16	0	149	0	0
T18	3393	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1566597	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1566597	0	0
T1	4496	87	0	0
T2	3761	0	0	0
T3	75643	512	0	0
T4	3057	58	0	0
T5	90052	729	0	0
T6	5731	64	0	0
T7	163555	1107	0	0
T8	17134	190	0	0
T15	205904	380	0	0
T16	0	58	0	0
T18	3393	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3698749	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3698749	0	0
T1	4496	87	0	0
T2	3761	0	0	0
T3	75643	719	0	0
T4	3057	58	0	0
T5	90052	730	0	0
T6	5731	17	0	0
T7	163555	719	0	0
T8	17134	99	0	0
T15	205904	21568	0	0
T16	0	47	0	0
T18	3393	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1496339	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1496339	0	0
T1	4496	90	0	0
T2	3761	0	0	0
T3	75643	550	0	0
T4	3057	53	0	0
T5	90052	747	0	0
T6	5731	39	0	0
T7	163555	1610	0	0
T8	17134	252	0	0
T15	205904	427	0	0
T16	0	95	0	0
T18	3393	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3313229	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3313229	0	0
T1	4496	90	0	0
T2	3761	0	0	0
T3	75643	461	0	0
T4	3057	53	0	0
T5	90052	671	0	0
T6	5731	9	0	0
T7	163555	4	0	0
T8	17134	123	0	0
T15	205904	23921	0	0
T16	0	65	0	0
T18	3393	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1569862	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1569862	0	0
T1	4496	75	0	0
T2	3761	525	0	0
T3	75643	719	0	0
T4	3057	47	0	0
T5	90052	577	0	0
T6	5731	0	0	0
T7	163555	2582	0	0
T8	17134	156	0	0
T15	205904	465	0	0
T16	0	139	0	0
T18	3393	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3041468	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3041468	0	0
T1	4496	75	0	0
T2	3761	525	0	0
T3	75643	689	0	0
T4	3057	47	0	0
T5	90052	560	0	0
T6	5731	0	0	0
T7	163555	744	0	0
T8	17134	90	0	0
T15	205904	26721	0	0
T16	0	158	0	0
T18	3393	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1521640	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1521640	0	0
T1	4496	76	0	0
T2	3761	0	0	0
T3	75643	628	0	0
T4	3057	57	0	0
T5	90052	609	0	0
T6	5731	44	0	0
T7	163555	1512	0	0
T8	17134	189	0	0
T15	205904	437	0	0
T16	0	80	0	0
T18	3393	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3091229	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3091229	0	0
T1	4496	76	0	0
T2	3761	0	0	0
T3	75643	535	0	0
T4	3057	57	0	0
T5	90052	695	0	0
T6	5731	16	0	0
T7	163555	708	0	0
T8	17134	77	0	0
T15	205904	23971	0	0
T16	0	74	0	0
T18	3393	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1527331	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1527331	0	0
T1	4496	61	0	0
T2	3761	255	0	0
T3	75643	724	0	0
T4	3057	50	0	0
T5	90052	554	0	0
T6	5731	98	0	0
T7	163555	4015	0	0
T8	17134	254	0	0
T15	205904	423	0	0
T18	3393	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2623903	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2623903	0	0
T1	4496	61	0	0
T2	3761	255	0	0
T3	75643	614	0	0
T4	3057	50	0	0
T5	90052	598	0	0
T6	5731	73	0	0
T7	163555	1629	0	0
T8	17134	95	0	0
T15	205904	24651	0	0
T18	3393	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1577472	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1577472	0	0
T1	4496	70	0	0
T2	3761	0	0	0
T3	75643	495	0	0
T4	3057	56	0	0
T5	90052	555	0	0
T6	5731	27	0	0
T7	163555	2110	0	0
T8	17134	274	0	0
T15	205904	397	0	0
T16	0	78	0	0
T18	3393	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3825649	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3825649	0	0
T1	4496	70	0	0
T2	3761	0	0	0
T3	75643	489	0	0
T4	3057	56	0	0
T5	90052	564	0	0
T6	5731	9	0	0
T7	163555	334	0	0
T8	17134	107	0	0
T15	205904	21375	0	0
T16	0	74	0	0
T18	3393	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1594569	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1594569	0	0
T1	4496	71	0	0
T2	3761	0	0	0
T3	75643	646	0	0
T4	3057	43	0	0
T5	90052	743	0	0
T6	5731	31	0	0
T7	163555	1893	0	0
T8	17134	360	0	0
T15	205904	326	0	0
T16	0	105	0	0
T18	3393	0	0	0
T19	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3573361	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3573361	0	0
T1	4496	71	0	0
T2	3761	0	0	0
T3	75643	610	0	0
T4	3057	43	0	0
T5	90052	735	0	0
T6	5731	9	0	0
T7	163555	1203	0	0
T8	17134	104	0	0
T15	205904	20136	0	0
T16	0	71	0	0
T18	3393	0	0	0
T19	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1538561	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1538561	0	0
T1	4496	85	0	0
T2	3761	299	0	0
T3	75643	577	0	0
T4	3057	45	0	0
T5	90052	891	0	0
T6	5731	71	0	0
T7	163555	1238	0	0
T8	17134	211	0	0
T15	205904	492	0	0
T18	3393	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2671208	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2671208	0	0
T1	4496	85	0	0
T2	3761	299	0	0
T3	75643	573	0	0
T4	3057	45	0	0
T5	90052	915	0	0
T6	5731	37	0	0
T7	163555	70	0	0
T8	17134	100	0	0
T15	205904	28365	0	0
T18	3393	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1553249	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1553249	0	0
T1	4496	87	0	0
T2	3761	224	0	0
T3	75643	533	0	0
T4	3057	56	0	0
T5	90052	734	0	0
T6	5731	71	0	0
T7	163555	621	0	0
T8	17134	272	0	0
T15	205904	318	0	0
T18	3393	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3623424	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3623424	0	0
T1	4496	87	0	0
T2	3761	224	0	0
T3	75643	534	0	0
T4	3057	56	0	0
T5	90052	703	0	0
T6	5731	25	0	0
T7	163555	251	0	0
T8	17134	96	0	0
T15	205904	16923	0	0
T18	3393	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1554923	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1554923	0	0
T1	4496	75	0	0
T2	3761	0	0	0
T3	75643	536	0	0
T4	3057	50	0	0
T5	90052	703	0	0
T6	5731	57	0	0
T7	163555	1112	0	0
T8	17134	243	0	0
T15	205904	411	0	0
T16	0	109	0	0
T18	3393	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3387516	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3387516	0	0
T1	4496	75	0	0
T2	3761	0	0	0
T3	75643	595	0	0
T4	3057	50	0	0
T5	90052	735	0	0
T6	5731	17	0	0
T7	163555	92	0	0
T8	17134	77	0	0
T15	205904	23096	0	0
T16	0	52	0	0
T18	3393	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1523005	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1523005	0	0
T1	4496	85	0	0
T2	3761	790	0	0
T3	75643	551	0	0
T4	3057	45	0	0
T5	90052	719	0	0
T6	5731	42	0	0
T7	163555	3396	0	0
T8	17134	153	0	0
T15	205904	434	0	0
T18	3393	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3134353	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3134353	0	0
T1	4496	85	0	0
T2	3761	790	0	0
T3	75643	619	0	0
T4	3057	45	0	0
T5	90052	780	0	0
T6	5731	8	0	0
T7	163555	489	0	0
T8	17134	69	0	0
T15	205904	23311	0	0
T18	3393	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1524043	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1524043	0	0
T1	4496	85	0	0
T2	3761	0	0	0
T3	75643	528	0	0
T4	3057	49	0	0
T5	90052	760	0	0
T6	5731	51	0	0
T7	163555	3507	0	0
T8	17134	256	0	0
T15	205904	412	0	0
T16	0	100	0	0
T18	3393	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2658236	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2658236	0	0
T1	4496	85	0	0
T2	3761	0	0	0
T3	75643	510	0	0
T4	3057	49	0	0
T5	90052	782	0	0
T6	5731	52	0	0
T7	163555	533	0	0
T8	17134	91	0	0
T15	205904	25115	0	0
T16	0	103	0	0
T18	3393	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1547723	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1547723	0	0
T1	4496	63	0	0
T2	3761	0	0	0
T3	75643	680	0	0
T4	3057	44	0	0
T5	90052	729	0	0
T6	5731	62	0	0
T7	163555	2868	0	0
T8	17134	183	0	0
T15	205904	532	0	0
T16	0	80	0	0
T18	3393	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3121435	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3121435	0	0
T1	4496	63	0	0
T2	3761	0	0	0
T3	75643	618	0	0
T4	3057	44	0	0
T5	90052	714	0	0
T6	5731	22	0	0
T7	163555	1263	0	0
T8	17134	78	0	0
T15	205904	24157	0	0
T16	0	71	0	0
T18	3393	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1565738	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1565738	0	0
T1	4496	76	0	0
T2	3761	277	0	0
T3	75643	467	0	0
T4	3057	47	0	0
T5	90052	766	0	0
T6	5731	56	0	0
T7	163555	991	0	0
T8	17134	177	0	0
T15	205904	335	0	0
T18	3393	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3301520	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3301520	0	0
T1	4496	76	0	0
T2	3761	277	0	0
T3	75643	509	0	0
T4	3057	47	0	0
T5	90052	841	0	0
T6	5731	16	0	0
T7	163555	201	0	0
T8	17134	70	0	0
T15	205904	20214	0	0
T18	3393	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1542649	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1542649	0	0
T1	4496	69	0	0
T2	3761	276	0	0
T3	75643	425	0	0
T4	3057	56	0	0
T5	90052	655	0	0
T6	5731	37	0	0
T7	163555	1538	0	0
T8	17134	148	0	0
T15	205904	519	0	0
T18	3393	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2917132	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2917132	0	0
T1	4496	69	0	0
T2	3761	276	0	0
T3	75643	547	0	0
T4	3057	56	0	0
T5	90052	763	0	0
T6	5731	25	0	0
T7	163555	629	0	0
T8	17134	50	0	0
T15	205904	26945	0	0
T18	3393	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1585261	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1585261	0	0
T1	4496	67	0	0
T2	3761	0	0	0
T3	75643	551	0	0
T4	3057	42	0	0
T5	90052	593	0	0
T6	5731	64	0	0
T7	163555	3146	0	0
T8	17134	212	0	0
T15	205904	449	0	0
T16	0	58	0	0
T18	3393	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2905166	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2905166	0	0
T1	4496	67	0	0
T2	3761	0	0	0
T3	75643	515	0	0
T4	3057	42	0	0
T5	90052	614	0	0
T6	5731	29	0	0
T7	163555	641	0	0
T8	17134	103	0	0
T15	205904	24949	0	0
T16	0	79	0	0
T18	3393	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1563758	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1563758	0	0
T1	4496	88	0	0
T2	3761	0	0	0
T3	75643	499	0	0
T4	3057	44	0	0
T5	90052	697	0	0
T6	5731	27	0	0
T7	163555	1521	0	0
T8	17134	203	0	0
T15	205904	378	0	0
T16	0	143	0	0
T18	3393	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3344029	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3344029	0	0
T1	4496	88	0	0
T2	3761	0	0	0
T3	75643	521	0	0
T4	3057	44	0	0
T5	90052	871	0	0
T6	5731	10	0	0
T7	163555	4	0	0
T8	17134	106	0	0
T15	205904	20062	0	0
T16	0	145	0	0
T18	3393	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1534571	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1534571	0	0
T1	4496	65	0	0
T2	3761	0	0	0
T3	75643	776	0	0
T4	3057	52	0	0
T5	90052	719	0	0
T6	5731	73	0	0
T7	163555	2269	0	0
T8	17134	182	0	0
T15	205904	423	0	0
T16	0	47	0	0
T18	3393	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2970496	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2970496	0	0
T1	4496	65	0	0
T2	3761	0	0	0
T3	75643	810	0	0
T4	3057	52	0	0
T5	90052	734	0	0
T6	5731	28	0	0
T7	163555	636	0	0
T8	17134	52	0	0
T15	205904	27207	0	0
T16	0	52	0	0
T18	3393	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1529010	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1529010	0	0
T1	4496	72	0	0
T2	3761	220	0	0
T3	75643	513	0	0
T4	3057	53	0	0
T5	90052	655	0	0
T6	5731	34	0	0
T7	163555	2298	0	0
T8	17134	215	0	0
T15	205904	345	0	0
T18	3393	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3504277	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3504277	0	0
T1	4496	72	0	0
T2	3761	220	0	0
T3	75643	579	0	0
T4	3057	53	0	0
T5	90052	659	0	0
T6	5731	36	0	0
T7	163555	1368	0	0
T8	17134	87	0	0
T15	205904	17129	0	0
T18	3393	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1528628	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1528628	0	0
T1	4496	79	0	0
T2	3761	0	0	0
T3	75643	467	0	0
T4	3057	46	0	0
T5	90052	743	0	0
T6	5731	33	0	0
T7	163555	2420	0	0
T8	17134	120	0	0
T15	205904	286	0	0
T16	0	120	0	0
T18	3393	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	2813787	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	2813787	0	0
T1	4496	79	0	0
T2	3761	0	0	0
T3	75643	528	0	0
T4	3057	46	0	0
T5	90052	630	0	0
T6	5731	8	0	0
T7	163555	1205	0	0
T8	17134	26	0	0
T15	205904	15244	0	0
T16	0	115	0	0
T18	3393	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	1501038	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	1501038	0	0
T1	4496	76	0	0
T2	3761	0	0	0
T3	75643	552	0	0
T4	3057	56	0	0
T5	90052	676	0	0
T6	5731	41	0	0
T7	163555	993	0	0
T8	17134	144	0	0
T15	205904	545	0	0
T16	0	41	0	0
T18	3393	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313870156	3473601	0	0
DepthKnown_A	313870156	313741693	0	0
RvalidKnown_A	313870156	313741693	0	0
WreadyKnown_A	313870156	313741693	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	3473601	0	0
T1	4496	76	0	0
T2	3761	0	0	0
T3	75643	645	0	0
T4	3057	56	0	0
T5	90052	717	0	0
T6	5731	11	0	0
T7	163555	3	0	0
T8	17134	47	0	0
T15	205904	26465	0	0
T16	0	58	0	0
T18	3393	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313870156	313741693	0	0
T1	4496	4425	0	0
T2	3761	3705	0	0
T3	75643	75616	0	0
T4	3057	3011	0	0
T5	90052	89981	0	0
T6	5731	5443	0	0
T7	163555	163515	0	0
T8	17134	17086	0	0
T15	205904	205896	0	0
T18	3393	3326	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0