Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1750858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

276219

1

T1

213

T2

25

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	684487	1			T1	545		T2	118		T3	49
values[0x0]	659851	1			T1	532		T2	22		T3	51
values[0x1]	682739	1			T1	543		T2	136		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1357939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

669138

1

T1

536

T2

102

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8030	1			T1	5		T2	1		T3	1
valid_sources[0x01]	9414	1			T1	5		T4	1		T14	1
valid_sources[0x02]	7311	1			T1	2		T2	2		T14	1
valid_sources[0x03]	7766	1			T1	6		T2	1		T14	1
valid_sources[0x04]	7476	1			T1	10		T14	1		T20	2
valid_sources[0x05]	7971	1			T1	7		T17	2		T19	3
valid_sources[0x06]	7871	1			T1	5		T14	1		T22	8
valid_sources[0x07]	7839	1			T1	6		T2	1		T14	1
valid_sources[0x08]	7720	1			T1	6		T2	1		T4	1
valid_sources[0x09]	7903	1			T1	5		T2	2		T14	1
valid_sources[0x0a]	8628	1			T1	7		T14	1		T19	5
valid_sources[0x0b]	7570	1			T1	5		T2	1		T16	1
valid_sources[0x0c]	9153	1			T1	4		T2	1		T3	5
valid_sources[0x0d]	7518	1			T1	9		T2	2		T3	1
valid_sources[0x0e]	7389	1			T1	6		T19	2		T20	1
valid_sources[0x0f]	8395	1			T1	1		T2	1		T16	1
valid_sources[0x10]	7452	1			T1	6		T3	7		T14	1
valid_sources[0x11]	7068	1			T1	5		T2	1		T14	1
valid_sources[0x12]	8041	1			T1	8		T19	1		T20	1
valid_sources[0x13]	7353	1			T1	4		T2	2		T14	1
valid_sources[0x14]	7563	1			T1	4		T2	4		T14	1
valid_sources[0x15]	8052	1			T1	3		T14	1		T19	5
valid_sources[0x16]	7603	1			T1	5		T2	3		T14	1
valid_sources[0x17]	7987	1			T1	9		T2	3		T14	1
valid_sources[0x18]	7943	1			T1	3		T2	1		T14	1
valid_sources[0x19]	8955	1			T1	3		T2	1		T14	1
valid_sources[0x1a]	7548	1			T1	6		T2	4		T14	1
valid_sources[0x1b]	7070	1			T1	6		T22	5		T24	6
valid_sources[0x1c]	7750	1			T1	2		T2	2		T17	1
valid_sources[0x1d]	7338	1			T1	4		T2	2		T16	3
valid_sources[0x1e]	8267	1			T1	4		T14	1		T19	1
valid_sources[0x1f]	8376	1			T1	3		T2	1		T14	1
valid_sources[0x20]	7608	1			T1	3		T2	1		T14	1
valid_sources[0x21]	7687	1			T1	5		T14	1		T18	1
valid_sources[0x22]	7610	1			T1	2		T3	4		T14	1
valid_sources[0x23]	8216	1			T1	6		T14	1		T19	1
valid_sources[0x24]	7322	1			T1	10		T16	1		T14	1
valid_sources[0x25]	8115	1			T1	10		T2	3		T14	1
valid_sources[0x26]	8551	1			T1	9		T3	1		T14	1
valid_sources[0x27]	9583	1			T1	2		T2	1		T14	1
valid_sources[0x28]	8067	1			T1	4		T2	1		T14	1
valid_sources[0x29]	8091	1			T1	8		T14	1		T22	3
valid_sources[0x2a]	7864	1			T1	8		T14	1		T19	1
valid_sources[0x2b]	7218	1			T1	5		T2	1		T16	1
valid_sources[0x2c]	8072	1			T1	8		T3	9		T14	1
valid_sources[0x2d]	8339	1			T1	3		T2	1		T14	1
valid_sources[0x2e]	8073	1			T1	5		T2	2		T14	1
valid_sources[0x2f]	8028	1			T1	4		T3	1		T20	1
valid_sources[0x30]	7431	1			T1	7		T14	1		T17	5
valid_sources[0x31]	7317	1			T1	9		T2	3		T14	1
valid_sources[0x32]	8320	1			T1	4		T14	1		T17	4
valid_sources[0x33]	7893	1			T1	1		T2	2		T22	5
valid_sources[0x34]	7744	1			T1	4		T2	1		T14	1
valid_sources[0x35]	6924	1			T1	7		T2	1		T14	1
valid_sources[0x36]	7303	1			T1	5		T2	5		T14	1
valid_sources[0x37]	8333	1			T1	5		T2	1		T20	2
valid_sources[0x38]	8592	1			T1	5		T14	1		T19	3
valid_sources[0x39]	8302	1			T1	8		T14	1		T17	3
valid_sources[0x3a]	7901	1			T1	3		T14	1		T19	1
valid_sources[0x3b]	7506	1			T1	8		T2	2		T14	1
valid_sources[0x3c]	7885	1			T1	6		T2	1		T3	1
valid_sources[0x3d]	7803	1			T1	3		T2	1		T14	1
valid_sources[0x3e]	8943	1			T1	3		T14	1		T19	6
valid_sources[0x3f]	8423	1			T1	4		T3	5		T14	1
valid_sources[0x40]	8237	1			T1	7		T2	3		T4	1
valid_sources[0x41]	7708	1			T1	11		T16	8		T14	1
valid_sources[0x42]	8066	1			T1	6		T19	1		T22	6
valid_sources[0x43]	7953	1			T1	3		T2	1		T3	2
valid_sources[0x44]	7446	1			T1	12		T14	1		T17	3
valid_sources[0x45]	7864	1			T1	7		T2	2		T16	2
valid_sources[0x46]	7325	1			T1	10		T2	2		T14	1
valid_sources[0x47]	9240	1			T1	3		T2	1		T14	1
valid_sources[0x48]	7668	1			T1	11		T2	1		T15	1
valid_sources[0x49]	8582	1			T1	6		T14	1		T19	1
valid_sources[0x4a]	7213	1			T1	4		T2	1		T14	1
valid_sources[0x4b]	8011	1			T1	9		T14	1		T19	1
valid_sources[0x4c]	8078	1			T1	9		T3	3		T14	1
valid_sources[0x4d]	6900	1			T1	7		T16	2		T14	1
valid_sources[0x4e]	8370	1			T1	3		T14	1		T19	1
valid_sources[0x4f]	8019	1			T1	3		T2	1		T14	1
valid_sources[0x50]	7526	1			T1	4		T14	1		T19	1
valid_sources[0x51]	8865	1			T1	6		T2	3		T14	1
valid_sources[0x52]	7891	1			T1	8		T2	1		T16	4
valid_sources[0x53]	7526	1			T1	8		T3	1		T14	1
valid_sources[0x54]	8186	1			T1	6		T2	1		T14	1
valid_sources[0x55]	8195	1			T1	5		T2	2		T14	1
valid_sources[0x56]	7615	1			T1	8		T14	1		T22	11
valid_sources[0x57]	8225	1			T1	8		T2	6		T3	1
valid_sources[0x58]	7324	1			T1	6		T2	1		T3	4
valid_sources[0x59]	7359	1			T1	10		T2	3		T14	2
valid_sources[0x5a]	7634	1			T1	6		T2	1		T3	1
valid_sources[0x5b]	7679	1			T1	5		T2	3		T3	5
valid_sources[0x5c]	8194	1			T1	4		T2	4		T14	1
valid_sources[0x5d]	7782	1			T1	5		T2	2		T14	1
valid_sources[0x5e]	8617	1			T1	12		T14	1		T19	1
valid_sources[0x5f]	8286	1			T1	8		T2	2		T14	1
valid_sources[0x60]	7621	1			T1	5		T2	1		T3	1
valid_sources[0x61]	8048	1			T1	2		T3	5		T4	1
valid_sources[0x62]	7868	1			T1	5		T2	1		T17	1
valid_sources[0x63]	7871	1			T1	5		T14	1		T19	3
valid_sources[0x64]	7925	1			T1	6		T14	1		T17	2
valid_sources[0x65]	7705	1			T1	10		T17	1		T22	2
valid_sources[0x66]	7697	1			T1	9		T2	1		T14	1
valid_sources[0x67]	7421	1			T1	7		T14	1		T17	1
valid_sources[0x68]	7478	1			T1	3		T14	1		T19	3
valid_sources[0x69]	8100	1			T1	6		T2	1		T14	1
valid_sources[0x6a]	7932	1			T1	5		T19	2		T22	5
valid_sources[0x6b]	8219	1			T1	11		T14	1		T17	3
valid_sources[0x6c]	9360	1			T1	7		T2	1		T14	1
valid_sources[0x6d]	7788	1			T1	6		T2	2		T14	1
valid_sources[0x6e]	7998	1			T1	9		T2	1		T14	1
valid_sources[0x6f]	7708	1			T1	9		T14	1		T19	2
valid_sources[0x70]	7140	1			T1	10		T2	2		T14	1
valid_sources[0x71]	8119	1			T1	10		T17	1		T22	5
valid_sources[0x72]	8077	1			T1	13		T3	7		T14	1
valid_sources[0x73]	7534	1			T1	5		T14	1		T17	3
valid_sources[0x74]	8028	1			T1	2		T2	3		T14	1
valid_sources[0x75]	8326	1			T1	5		T2	4		T14	1
valid_sources[0x76]	8212	1			T1	9		T2	3		T14	1
valid_sources[0x77]	8537	1			T1	5		T2	1		T14	1
valid_sources[0x78]	7874	1			T1	13		T19	3		T22	5
valid_sources[0x79]	7194	1			T1	3		T2	1		T19	4
valid_sources[0x7a]	7191	1			T1	5		T14	1		T19	3
valid_sources[0x7b]	7381	1			T1	4		T2	3		T17	1
valid_sources[0x7c]	8794	1			T1	11		T2	3		T16	1
valid_sources[0x7d]	8872	1			T1	3		T2	2		T16	1
valid_sources[0x7e]	7475	1			T1	11		T2	1		T14	1
valid_sources[0x7f]	7899	1			T1	6		T2	1		T14	1
valid_sources[0x80]	8738	1			T1	7		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28869

1

T1

17

T2

8

T3

1

values[0x0]

all_enables

biggest_size

218501

1

T1

180

T2

8

T3

16

values[0x1]

all_enables

biggest_size

28849

1

T1

16

T2

9

T3

4