Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	342562887	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342562887	0	0
T1	2110024	44106	0	0
T2	709184	27278	0	0
T3	244272	4049	0	0
T4	20664	508	0	0
T14	12073936	167286	0	0
T15	32760	895	0	0
T16	2381176	50436	0	0
T17	42952	847	0	0
T18	10591336	228226	0	0
T19	48552	2081	0	0
T20	0	1073	0	0
T21	0	193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110024	2108960	0	0
T2	709184	671664	0	0
T3	244272	241416	0	0
T4	20664	19152	0	0
T14	12073936	12070632	0	0
T15	32760	31304	0	0
T16	2381176	2378544	0	0
T17	42952	38920	0	0
T18	10591336	10589376	0	0
T19	48552	48104	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110024	2108960	0	0
T2	709184	671664	0	0
T3	244272	241416	0	0
T4	20664	19152	0	0
T14	12073936	12070632	0	0
T15	32760	31304	0	0
T16	2381176	2378544	0	0
T17	42952	38920	0	0
T18	10591336	10589376	0	0
T19	48552	48104	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110024	2108960	0	0
T2	709184	671664	0	0
T3	244272	241416	0	0
T4	20664	19152	0	0
T14	12073936	12070632	0	0
T15	32760	31304	0	0
T16	2381176	2378544	0	0
T17	42952	38920	0	0
T18	10591336	10589376	0	0
T19	48552	48104	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	124773015	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	124773015	0	0
T1	37679	16709	0	0
T2	12664	9628	0	0
T3	4362	1744	0	0
T4	369	196	0	0
T14	215606	1046	0	0
T15	585	406	0	0
T16	42521	19029	0	0
T17	767	334	0	0
T18	189131	87634	0	0
T19	867	806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	91322257	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	91322257	0	0
T1	37679	14408	0	0
T2	12664	6097	0	0
T3	4362	572	0	0
T4	369	104	0	0
T14	215606	82597	0	0
T15	585	241	0	0
T16	42521	16803	0	0
T17	767	171	0	0
T18	189131	46046	0	0
T19	867	425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1325829	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1325829	0	0
T1	37679	223	0	0
T2	12664	154	0	0
T3	4362	54	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	279	0	0
T17	767	8	0	0
T18	189131	2023	0	0
T19	867	15	0	0
T20	0	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3240724	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3240724	0	0
T1	37679	184	0	0
T2	12664	154	0	0
T3	4362	47	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	315	0	0
T17	767	8	0	0
T18	189131	3099	0	0
T19	867	15	0	0
T20	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1309493	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1309493	0	0
T1	37679	196	0	0
T2	12664	146	0	0
T3	4362	41	0	0
T4	369	2	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	320	0	0
T17	767	5	0	0
T18	189131	1236	0	0
T19	867	20	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2745214	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2745214	0	0
T1	37679	159	0	0
T2	12664	146	0	0
T3	4362	13	0	0
T4	369	2	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	337	0	0
T17	767	5	0	0
T18	189131	2726	0	0
T19	867	20	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1356208	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1356208	0	0
T1	37679	210	0	0
T2	12664	159	0	0
T3	4362	17	0	0
T4	369	1	0	0
T14	215606	0	0	0
T15	585	8	0	0
T16	42521	252	0	0
T17	767	7	0	0
T18	189131	2837	0	0
T19	867	25	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2662569	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2662569	0	0
T1	37679	244	0	0
T2	12664	158	0	0
T3	4362	19	0	0
T4	369	1	0	0
T14	215606	0	0	0
T15	585	8	0	0
T16	42521	296	0	0
T17	767	7	0	0
T18	189131	2837	0	0
T19	867	25	0	0
T20	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1329034	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1329034	0	0
T1	37679	235	0	0
T2	12664	157	0	0
T3	4362	47	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	3	0	0
T16	42521	343	0	0
T17	767	8	0	0
T18	189131	2351	0	0
T19	867	12	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3375291	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3375291	0	0
T1	37679	242	0	0
T2	12664	157	0	0
T3	4362	12	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	3	0	0
T16	42521	309	0	0
T17	767	8	0	0
T18	189131	614	0	0
T19	867	12	0	0
T20	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1352344	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1352344	0	0
T1	37679	241	0	0
T2	12664	399	0	0
T3	4362	41	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	187	0	0
T17	767	5	0	0
T18	189131	2306	0	0
T19	867	15	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2974354	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2974354	0	0
T1	37679	247	0	0
T2	12664	399	0	0
T3	4362	28	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	195	0	0
T17	767	5	0	0
T18	189131	1714	0	0
T19	867	15	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1350750	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1350750	0	0
T1	37679	230	0	0
T2	12664	175	0	0
T3	4362	66	0	0
T4	369	7	0	0
T14	215606	0	0	0
T15	585	6	0	0
T16	42521	286	0	0
T17	767	3	0	0
T18	189131	1654	0	0
T19	867	24	0	0
T20	0	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2704986	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2704986	0	0
T1	37679	296	0	0
T2	12664	173	0	0
T3	4362	28	0	0
T4	369	7	0	0
T14	215606	0	0	0
T15	585	6	0	0
T16	42521	224	0	0
T17	767	3	0	0
T18	189131	1210	0	0
T19	867	24	0	0
T20	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1391585	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1391585	0	0
T1	37679	233	0	0
T2	12664	161	0	0
T3	4362	31	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	7	0	0
T16	42521	236	0	0
T17	767	3	0	0
T18	189131	3264	0	0
T19	867	17	0	0
T20	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	4421862	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	4421862	0	0
T1	37679	260	0	0
T2	12664	161	0	0
T3	4362	6	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	7	0	0
T16	42521	250	0	0
T17	767	3	0	0
T18	189131	1224	0	0
T19	867	17	0	0
T20	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1384193	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1384193	0	0
T1	37679	190	0	0
T2	12664	153	0	0
T3	4362	35	0	0
T4	369	6	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	273	0	0
T17	767	5	0	0
T18	189131	645	0	0
T19	867	22	0	0
T20	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3011041	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3011041	0	0
T1	37679	203	0	0
T2	12664	153	0	0
T3	4362	12	0	0
T4	369	6	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	300	0	0
T17	767	5	0	0
T18	189131	461	0	0
T19	867	22	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1326330	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1326330	0	0
T1	37679	268	0	0
T2	12664	147	0	0
T3	4362	20	0	0
T4	369	7	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	361	0	0
T17	767	8	0	0
T18	189131	2119	0	0
T19	867	11	0	0
T20	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3400862	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3400862	0	0
T1	37679	356	0	0
T2	12664	147	0	0
T3	4362	32	0	0
T4	369	7	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	327	0	0
T17	767	8	0	0
T18	189131	1751	0	0
T19	867	11	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1327192	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1327192	0	0
T1	37679	276	0	0
T2	12664	147	0	0
T3	4362	29	0	0
T4	369	7	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	220	0	0
T17	767	5	0	0
T18	189131	1769	0	0
T19	867	19	0	0
T20	0	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3306601	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3306601	0	0
T1	37679	317	0	0
T2	12664	147	0	0
T3	4362	15	0	0
T4	369	7	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	253	0	0
T17	767	5	0	0
T18	189131	1560	0	0
T19	867	19	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1305118	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1305118	0	0
T1	37679	214	0	0
T2	12664	430	0	0
T3	4362	33	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	7	0	0
T16	42521	316	0	0
T17	767	3	0	0
T18	189131	1878	0	0
T19	867	14	0	0
T20	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3634332	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3634332	0	0
T1	37679	209	0	0
T2	12664	430	0	0
T3	4362	13	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	7	0	0
T16	42521	258	0	0
T17	767	3	0	0
T18	189131	1156	0	0
T19	867	14	0	0
T20	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1325003	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1325003	0	0
T1	37679	382	0	0
T2	12664	399	0	0
T3	4362	50	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	6	0	0
T16	42521	293	0	0
T17	767	6	0	0
T18	189131	1356	0	0
T19	867	8	0	0
T20	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3901499	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3901499	0	0
T1	37679	392	0	0
T2	12664	399	0	0
T3	4362	38	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	6	0	0
T16	42521	442	0	0
T17	767	6	0	0
T18	189131	1973	0	0
T19	867	8	0	0
T20	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1340351	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1340351	0	0
T1	37679	191	0	0
T2	12664	165	0	0
T3	4362	74	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	5	0	0
T16	42521	169	0	0
T17	767	8	0	0
T18	189131	3167	0	0
T19	867	15	0	0
T20	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3084307	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3084307	0	0
T1	37679	294	0	0
T2	12664	165	0	0
T3	4362	22	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	5	0	0
T16	42521	144	0	0
T17	767	8	0	0
T18	189131	2814	0	0
T19	867	15	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1406352	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1406352	0	0
T1	37679	284	0	0
T2	12664	134	0	0
T3	4362	31	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	158	0	0
T17	767	9	0	0
T18	189131	1069	0	0
T19	867	20	0	0
T20	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	4162530	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	4162530	0	0
T1	37679	314	0	0
T2	12664	134	0	0
T3	4362	16	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	207	0	0
T17	767	9	0	0
T18	189131	1749	0	0
T19	867	20	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1334048	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1334048	0	0
T1	37679	174	0	0
T2	12664	156	0	0
T3	4362	54	0	0
T4	369	4	0	0
T14	215606	0	0	0
T15	585	3	0	0
T16	42521	339	0	0
T17	767	4	0	0
T18	189131	291	0	0
T19	867	8	0	0
T20	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2739033	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2739033	0	0
T1	37679	220	0	0
T2	12664	156	0	0
T3	4362	10	0	0
T4	369	4	0	0
T14	215606	0	0	0
T15	585	3	0	0
T16	42521	305	0	0
T17	767	4	0	0
T18	189131	1838	0	0
T19	867	8	0	0
T20	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1324453	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1324453	0	0
T1	37679	310	0	0
T2	12664	350	0	0
T3	4362	32	0	0
T4	369	6	0	0
T14	215606	0	0	0
T15	585	6	0	0
T16	42521	312	0	0
T17	767	5	0	0
T18	189131	2263	0	0
T19	867	16	0	0
T20	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3753301	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3753301	0	0
T1	37679	271	0	0
T2	12664	349	0	0
T3	4362	13	0	0
T4	369	6	0	0
T14	215606	0	0	0
T15	585	6	0	0
T16	42521	213	0	0
T17	767	5	0	0
T18	189131	1837	0	0
T19	867	16	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1328893	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1328893	0	0
T1	37679	199	0	0
T2	12664	183	0	0
T3	4362	41	0	0
T4	369	1	0	0
T14	215606	1046	0	0
T15	585	3	0	0
T16	42521	266	0	0
T17	767	8	0	0
T18	189131	1600	0	0
T19	867	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3115526	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3115526	0	0
T1	37679	212	0	0
T2	12664	183	0	0
T3	4362	27	0	0
T4	369	1	0	0
T14	215606	82597	0	0
T15	585	3	0	0
T16	42521	304	0	0
T17	767	8	0	0
T18	189131	2313	0	0
T19	867	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1305787	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1305787	0	0
T1	37679	163	0	0
T2	12664	420	0	0
T3	4362	20	0	0
T4	369	2	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	226	0	0
T17	767	6	0	0
T18	189131	2398	0	0
T19	867	19	0	0
T20	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3076490	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3076490	0	0
T1	37679	186	0	0
T2	12664	420	0	0
T3	4362	2	0	0
T4	369	2	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	339	0	0
T17	767	6	0	0
T18	189131	1233	0	0
T19	867	19	0	0
T20	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1325062	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1325062	0	0
T1	37679	251	0	0
T2	12664	153	0	0
T3	4362	32	0	0
T4	369	2	0	0
T14	215606	0	0	0
T15	585	7	0	0
T16	42521	263	0	0
T17	767	8	0	0
T18	189131	3470	0	0
T19	867	12	0	0
T20	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	4481153	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	4481153	0	0
T1	37679	211	0	0
T2	12664	153	0	0
T3	4362	15	0	0
T4	369	2	0	0
T14	215606	0	0	0
T15	585	7	0	0
T16	42521	256	0	0
T17	767	8	0	0
T18	189131	3112	0	0
T19	867	12	0	0
T20	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1395679	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1395679	0	0
T1	37679	247	0	0
T2	12664	168	0	0
T3	4362	26	0	0
T4	369	10	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	251	0	0
T17	767	10	0	0
T18	189131	1934	0	0
T19	867	23	0	0
T20	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3729390	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3729390	0	0
T1	37679	225	0	0
T2	12664	168	0	0
T3	4362	31	0	0
T4	369	10	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	368	0	0
T17	767	10	0	0
T18	189131	2975	0	0
T19	867	23	0	0
T20	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1340433	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1340433	0	0
T1	37679	224	0	0
T2	12664	167	0	0
T3	4362	73	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	8	0	0
T16	42521	287	0	0
T17	767	2	0	0
T18	189131	1247	0	0
T19	867	13	0	0
T20	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2711325	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2711325	0	0
T1	37679	321	0	0
T2	12664	167	0	0
T3	4362	10	0	0
T4	369	5	0	0
T14	215606	0	0	0
T15	585	8	0	0
T16	42521	263	0	0
T17	767	2	0	0
T18	189131	68	0	0
T19	867	13	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1285444	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1285444	0	0
T1	37679	188	0	0
T2	12664	165	0	0
T3	4362	79	0	0
T4	369	6	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	278	0	0
T17	767	9	0	0
T18	189131	1493	0	0
T19	867	10	0	0
T20	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2699084	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2699084	0	0
T1	37679	127	0	0
T2	12664	165	0	0
T3	4362	20	0	0
T4	369	6	0	0
T14	215606	0	0	0
T15	585	2	0	0
T16	42521	224	0	0
T17	767	9	0	0
T18	189131	2418	0	0
T19	867	10	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1323138	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1323138	0	0
T1	37679	230	0	0
T2	12664	180	0	0
T3	4362	64	0	0
T4	369	0	0	0
T14	215606	0	0	0
T15	585	5	0	0
T16	42521	302	0	0
T17	767	10	0	0
T18	189131	2105	0	0
T19	867	17	0	0
T20	0	14	0	0
T21	0	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3576553	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3576553	0	0
T1	37679	232	0	0
T2	12664	180	0	0
T3	4362	48	0	0
T4	369	0	0	0
T14	215606	0	0	0
T15	585	5	0	0
T16	42521	351	0	0
T17	767	10	0	0
T18	189131	1173	0	0
T19	867	17	0	0
T20	0	2	0	0
T21	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1361395	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1361395	0	0
T1	37679	218	0	0
T2	12664	154	0	0
T3	4362	105	0	0
T4	369	1	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	130	0	0
T17	767	6	0	0
T18	189131	635	0	0
T19	867	12	0	0
T20	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	2918791	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	2918791	0	0
T1	37679	252	0	0
T2	12664	154	0	0
T3	4362	66	0	0
T4	369	1	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	160	0	0
T17	767	6	0	0
T18	189131	1139	0	0
T19	867	12	0	0
T20	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1303366	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1303366	0	0
T1	37679	274	0	0
T2	12664	159	0	0
T3	4362	24	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	9	0	0
T16	42521	285	0	0
T17	767	8	0	0
T18	189131	1989	0	0
T19	867	18	0	0
T20	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3420091	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3420091	0	0
T1	37679	289	0	0
T2	12664	159	0	0
T3	4362	3	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	9	0	0
T16	42521	312	0	0
T17	767	8	0	0
T18	189131	1197	0	0
T19	867	18	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1361935	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1361935	0	0
T1	37679	196	0	0
T2	12664	156	0	0
T3	4362	21	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	204	0	0
T17	767	7	0	0
T18	189131	914	0	0
T19	867	15	0	0
T20	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3708764	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3708764	0	0
T1	37679	237	0	0
T2	12664	156	0	0
T3	4362	11	0	0
T4	369	3	0	0
T14	215606	0	0	0
T15	585	4	0	0
T16	42521	245	0	0
T17	767	7	0	0
T18	189131	818	0	0
T19	867	15	0	0
T20	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	1331175	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	1331175	0	0
T1	37679	248	0	0
T2	12664	442	0	0
T3	4362	21	0	0
T4	369	1	0	0
T14	215606	0	0	0
T15	585	9	0	0
T16	42521	286	0	0
T17	767	5	0	0
T18	189131	487	0	0
T19	867	14	0	0
T20	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307562036	3761352	0	0
DepthKnown_A	307562036	307449889	0	0
RvalidKnown_A	307562036	307449889	0	0
WreadyKnown_A	307562036	307449889	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	3761352	0	0
T1	37679	194	0	0
T2	12664	441	0	0
T3	4362	15	0	0
T4	369	1	0	0
T14	215606	0	0	0
T15	585	9	0	0
T16	42521	285	0	0
T17	767	5	0	0
T18	189131	1037	0	0
T19	867	14	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307562036	307449889	0	0
T1	37679	37660	0	0
T2	12664	11994	0	0
T3	4362	4311	0	0
T4	369	342	0	0
T14	215606	215547	0	0
T15	585	559	0	0
T16	42521	42474	0	0
T17	767	695	0	0
T18	189131	189096	0	0
T19	867	859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0