Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1604247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251704

1

T1

107

T2

23

T3

1523

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	627451	1			T1	268		T2	51		T3	3655
values[0x0]	598973	1			T1	261		T2	65		T3	3656
values[0x1]	629527	1			T1	274		T2	49		T3	3696

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1242944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

613007

1

T1

253

T2

56

T3

3600

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7973	1			T1	7		T3	36		T4	1
valid_sources[0x01]	6888	1			T3	53		T12	14		T11	1
valid_sources[0x02]	7516	1			T3	40		T12	14		T11	3
valid_sources[0x03]	8022	1			T3	42		T12	11		T13	3
valid_sources[0x04]	8060	1			T3	59		T12	20		T11	1
valid_sources[0x05]	6907	1			T2	1		T3	43		T12	11
valid_sources[0x06]	8939	1			T3	38		T5	251		T4	1
valid_sources[0x07]	6878	1			T3	36		T12	5		T11	1
valid_sources[0x08]	7030	1			T3	46		T12	11		T11	7
valid_sources[0x09]	7503	1			T3	46		T12	13		T11	6
valid_sources[0x0a]	6727	1			T1	9		T2	5		T3	53
valid_sources[0x0b]	7219	1			T3	65		T4	1		T12	15
valid_sources[0x0c]	6703	1			T3	36		T12	16		T11	5
valid_sources[0x0d]	6577	1			T3	22		T12	13		T11	1
valid_sources[0x0e]	7225	1			T3	31		T12	18		T11	2
valid_sources[0x0f]	8719	1			T3	20		T12	9		T11	3
valid_sources[0x10]	6419	1			T3	42		T12	15		T11	4
valid_sources[0x11]	6735	1			T3	48		T12	11		T11	6
valid_sources[0x12]	8861	1			T3	49		T12	19		T11	18
valid_sources[0x13]	6788	1			T1	14		T3	55		T12	10
valid_sources[0x14]	7442	1			T3	60		T12	14		T11	3
valid_sources[0x15]	6777	1			T3	28		T12	21		T11	5
valid_sources[0x16]	7091	1			T3	50		T12	12		T11	2
valid_sources[0x17]	7218	1			T3	60		T12	13		T11	5
valid_sources[0x18]	6467	1			T3	58		T5	128		T12	16
valid_sources[0x19]	6209	1			T3	37		T12	18		T11	2
valid_sources[0x1a]	8082	1			T3	54		T12	11		T11	3
valid_sources[0x1b]	6509	1			T3	42		T12	12		T11	12
valid_sources[0x1c]	7460	1			T3	42		T12	15		T11	7
valid_sources[0x1d]	7625	1			T2	16		T3	32		T12	14
valid_sources[0x1e]	7497	1			T3	32		T4	1		T12	18
valid_sources[0x1f]	6984	1			T3	34		T4	1		T12	23
valid_sources[0x20]	6648	1			T1	18		T2	9		T3	56
valid_sources[0x21]	6361	1			T2	8		T3	26		T12	13
valid_sources[0x22]	9543	1			T3	39		T12	14		T11	3
valid_sources[0x23]	7281	1			T3	57		T4	1		T12	20
valid_sources[0x24]	6388	1			T1	9		T3	42		T12	10
valid_sources[0x25]	6983	1			T2	12		T3	34		T12	24
valid_sources[0x26]	7656	1			T3	38		T12	15		T11	1
valid_sources[0x27]	7853	1			T3	53		T12	14		T11	3
valid_sources[0x28]	6913	1			T3	54		T12	21		T13	5
valid_sources[0x29]	6986	1			T1	13		T3	32		T12	20
valid_sources[0x2a]	7063	1			T3	33		T12	16		T11	4
valid_sources[0x2b]	6726	1			T3	42		T12	10		T11	3
valid_sources[0x2c]	8078	1			T3	69		T12	13		T13	6
valid_sources[0x2d]	7386	1			T3	47		T12	13		T11	3
valid_sources[0x2e]	7035	1			T3	51		T12	14		T11	6
valid_sources[0x2f]	7375	1			T3	45		T12	12		T11	3
valid_sources[0x30]	9296	1			T3	37		T12	20		T11	1
valid_sources[0x31]	6890	1			T3	39		T12	9		T11	6
valid_sources[0x32]	7235	1			T3	40		T5	144		T12	14
valid_sources[0x33]	6997	1			T3	55		T12	13		T11	1
valid_sources[0x34]	6813	1			T3	34		T12	19		T11	4
valid_sources[0x35]	6856	1			T3	36		T12	6		T11	2
valid_sources[0x36]	7140	1			T3	38		T12	10		T11	3
valid_sources[0x37]	8037	1			T3	32		T12	14		T11	4
valid_sources[0x38]	6805	1			T3	49		T12	11		T11	2
valid_sources[0x39]	7134	1			T3	34		T5	291		T12	8
valid_sources[0x3a]	7257	1			T1	12		T2	17		T3	28
valid_sources[0x3b]	6635	1			T3	42		T12	11		T11	2
valid_sources[0x3c]	7494	1			T1	13		T3	33		T12	11
valid_sources[0x3d]	7631	1			T2	5		T3	29		T4	1
valid_sources[0x3e]	6583	1			T1	6		T3	50		T12	9
valid_sources[0x3f]	6812	1			T1	14		T3	42		T12	10
valid_sources[0x40]	7756	1			T3	29		T5	225		T12	8
valid_sources[0x41]	7314	1			T3	37		T12	8		T11	6
valid_sources[0x42]	7293	1			T3	42		T5	132		T12	12
valid_sources[0x43]	8649	1			T3	41		T12	10		T11	4
valid_sources[0x44]	7142	1			T3	38		T12	9		T11	4
valid_sources[0x45]	7328	1			T3	35		T12	25		T13	6
valid_sources[0x46]	6729	1			T1	8		T3	56		T12	14
valid_sources[0x47]	6734	1			T1	18		T3	46		T12	14
valid_sources[0x48]	6946	1			T1	6		T3	30		T12	15
valid_sources[0x49]	6599	1			T1	20		T3	66		T12	11
valid_sources[0x4a]	7727	1			T3	75		T12	11		T11	4
valid_sources[0x4b]	7484	1			T3	41		T12	16		T11	2
valid_sources[0x4c]	7208	1			T3	63		T10	5		T12	17
valid_sources[0x4d]	6706	1			T1	15		T3	56		T12	11
valid_sources[0x4e]	6976	1			T2	3		T3	89		T12	9
valid_sources[0x4f]	6561	1			T2	6		T3	47		T12	15
valid_sources[0x50]	7322	1			T2	3		T3	29		T12	18
valid_sources[0x51]	6789	1			T3	40		T12	24		T11	6
valid_sources[0x52]	7209	1			T3	35		T12	17		T13	5
valid_sources[0x53]	7801	1			T1	5		T3	53		T12	11
valid_sources[0x54]	7918	1			T3	35		T12	14		T11	3
valid_sources[0x55]	6390	1			T3	38		T12	14		T11	7
valid_sources[0x56]	7506	1			T1	11		T3	36		T12	16
valid_sources[0x57]	6638	1			T3	38		T12	22		T11	2
valid_sources[0x58]	6961	1			T3	35		T12	15		T11	3
valid_sources[0x59]	6687	1			T3	39		T12	14		T11	3
valid_sources[0x5a]	7356	1			T2	18		T3	34		T12	13
valid_sources[0x5b]	7537	1			T1	20		T3	78		T12	25
valid_sources[0x5c]	7017	1			T3	31		T12	9		T11	6
valid_sources[0x5d]	8228	1			T3	36		T5	882		T12	15
valid_sources[0x5e]	8067	1			T3	42		T5	443		T12	14
valid_sources[0x5f]	7402	1			T3	47		T12	13		T11	4
valid_sources[0x60]	6771	1			T3	36		T10	2		T12	11
valid_sources[0x61]	6450	1			T3	40		T12	11		T11	3
valid_sources[0x62]	7398	1			T3	36		T12	14		T11	7
valid_sources[0x63]	6187	1			T3	25		T12	13		T13	10
valid_sources[0x64]	7263	1			T3	33		T12	8		T11	3
valid_sources[0x65]	6545	1			T3	68		T12	10		T11	4
valid_sources[0x66]	6576	1			T3	45		T12	9		T11	2
valid_sources[0x67]	8635	1			T3	70		T12	13		T11	3
valid_sources[0x68]	7243	1			T3	44		T4	1		T12	13
valid_sources[0x69]	6899	1			T3	36		T12	9		T11	2
valid_sources[0x6a]	6970	1			T3	48		T12	17		T11	6
valid_sources[0x6b]	6869	1			T3	28		T12	13		T11	4
valid_sources[0x6c]	9276	1			T3	47		T12	15		T11	4
valid_sources[0x6d]	7592	1			T1	5		T3	60		T12	15
valid_sources[0x6e]	7100	1			T1	17		T3	38		T12	2
valid_sources[0x6f]	6554	1			T1	14		T3	30		T10	2
valid_sources[0x70]	7253	1			T3	56		T12	15		T11	5
valid_sources[0x71]	7155	1			T3	29		T12	19		T11	3
valid_sources[0x72]	7595	1			T3	40		T12	9		T11	1
valid_sources[0x73]	7223	1			T2	36		T3	42		T12	17
valid_sources[0x74]	7797	1			T3	40		T12	12		T11	1
valid_sources[0x75]	6596	1			T3	39		T12	13		T13	7
valid_sources[0x76]	7381	1			T3	47		T12	6		T11	1
valid_sources[0x77]	7608	1			T2	5		T3	34		T12	15
valid_sources[0x78]	7614	1			T1	10		T3	58		T12	11
valid_sources[0x79]	7403	1			T3	29		T12	10		T13	4
valid_sources[0x7a]	7543	1			T3	92		T12	13		T11	6
valid_sources[0x7b]	7672	1			T2	2		T3	42		T5	131
valid_sources[0x7c]	7683	1			T3	46		T12	14		T11	2
valid_sources[0x7d]	6824	1			T3	40		T12	23		T11	7
valid_sources[0x7e]	7370	1			T3	54		T12	16		T11	9
valid_sources[0x7f]	7572	1			T3	53		T12	12		T11	4
valid_sources[0x80]	7437	1			T3	31		T12	18		T11	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26651

1

T1

6

T2

3

T3

161

values[0x0]

all_enables

biggest_size

198449

1

T1

86

T2

20

T3

1218

values[0x1]

all_enables

biggest_size

26604

1

T1

15

T3

144

T5

69