Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	344380977	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	47936	47936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	344380977	0	0
T1	1697976	23783	0	0
T2	7958440	256059	0	0
T3	1254176	48601	0	0
T4	54880	1514	0	0
T5	274176	18946	0	0
T10	1193416	17245	0	0
T11	927192	13700	0	0
T12	4041464	111944	0	0
T13	3210256	145985	0	0
T14	4665752	83879	0	0
T15	0	744526	0	0
T16	0	29562	0	0
T17	0	105993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1697976	1697136	0	0
T2	7958440	7955248	0	0
T3	1254176	1194256	0	0
T4	54880	51800	0	0
T5	274176	273448	0	0
T10	1193416	1189888	0	0
T11	927192	923048	0	0
T12	4041464	4039392	0	0
T13	3210256	3182872	0	0
T14	4665752	4665304	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1697976	1697136	0	0
T2	7958440	7955248	0	0
T3	1254176	1194256	0	0
T4	54880	51800	0	0
T5	274176	273448	0	0
T10	1193416	1189888	0	0
T11	927192	923048	0	0
T12	4041464	4039392	0	0
T13	3210256	3182872	0	0
T14	4665752	4665304	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1697976	1697136	0	0
T2	7958440	7955248	0	0
T3	1254176	1194256	0	0
T4	54880	51800	0	0
T5	274176	273448	0	0
T10	1193416	1189888	0	0
T11	927192	923048	0	0
T12	4041464	4039392	0	0
T13	3210256	3182872	0	0
T14	4665752	4665304	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	47936	47936	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T10	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	129304823	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	129304823	0	0
T1	30321	6456	0	0
T2	142115	140148	0	0
T3	22396	20179	0	0
T4	980	587	0	0
T5	4896	4739	0	0
T10	21311	8199	0	0
T11	16557	6283	0	0
T12	72169	26266	0	0
T13	57326	55465	0	0
T14	83317	81540	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	86509259	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	86509259	0	0
T1	30321	5445	0	0
T2	142115	57603	0	0
T3	22396	11007	0	0
T4	980	309	0	0
T5	4896	4737	0	0
T10	21311	2403	0	0
T11	16557	2038	0	0
T12	72169	29713	0	0
T13	57326	32593	0	0
T14	83317	826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1583425	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1583425	0	0
T1	30321	326	0	0
T2	142115	22	0	0
T3	22396	278	0	0
T4	980	12	0	0
T5	4896	215	0	0
T10	21311	190	0	0
T11	16557	96	0	0
T12	72169	2128	0	0
T13	57326	975	0	0
T14	83317	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2428013	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2428013	0	0
T1	30321	283	0	0
T2	142115	1896	0	0
T3	22396	278	0	0
T4	980	12	0	0
T5	4896	215	0	0
T10	21311	90	0	0
T11	16557	16	0	0
T12	72169	2115	0	0
T13	57326	974	0	0
T14	83317	676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1587514	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1587514	0	0
T1	30321	238	0	0
T2	142115	21	0	0
T3	22396	398	0	0
T4	980	13	0	0
T5	4896	578	0	0
T10	21311	156	0	0
T11	16557	263	0	0
T12	72169	4493	0	0
T13	57326	698	0	0
T14	83317	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3717959	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3717959	0	0
T1	30321	237	0	0
T2	142115	1741	0	0
T3	22396	398	0	0
T4	980	13	0	0
T5	4896	578	0	0
T10	21311	47	0	0
T11	16557	94	0	0
T12	72169	4768	0	0
T13	57326	698	0	0
T14	83317	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1595773	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1595773	0	0
T1	30321	192	0	0
T2	142115	28	0	0
T3	22396	594	0	0
T4	980	11	0	0
T5	4896	0	0	0
T10	21311	161	0	0
T11	16557	181	0	0
T12	72169	0	0	0
T13	57326	682	0	0
T14	83317	3	0	0
T15	0	1152	0	0
T16	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2935068	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2935068	0	0
T1	30321	123	0	0
T2	142115	1960	0	0
T3	22396	593	0	0
T4	980	11	0	0
T5	4896	0	0	0
T10	21311	52	0	0
T11	16557	71	0	0
T12	72169	0	0	0
T13	57326	682	0	0
T14	83317	1	0	0
T15	0	82029	0	0
T16	0	431	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1556383	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1556383	0	0
T1	30321	129	0	0
T2	142115	38	0	0
T3	22396	276	0	0
T4	980	2	0	0
T5	4896	0	0	0
T10	21311	196	0	0
T11	16557	130	0	0
T12	72169	1764	0	0
T13	57326	720	0	0
T14	83317	43	0	0
T16	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2986952	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2986952	0	0
T1	30321	134	0	0
T2	142115	2384	0	0
T3	22396	276	0	0
T4	980	2	0	0
T5	4896	0	0	0
T10	21311	65	0	0
T11	16557	59	0	0
T12	72169	2043	0	0
T13	57326	720	0	0
T14	83317	9	0	0
T16	0	2088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1549981	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1549981	0	0
T1	30321	207	0	0
T2	142115	17	0	0
T3	22396	272	0	0
T4	980	7	0	0
T5	4896	515	0	0
T10	21311	223	0	0
T11	16557	148	0	0
T12	72169	1675	0	0
T13	57326	1398	0	0
T14	83317	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2969404	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2969404	0	0
T1	30321	159	0	0
T2	142115	920	0	0
T3	22396	272	0	0
T4	980	7	0	0
T5	4896	515	0	0
T10	21311	68	0	0
T11	16557	79	0	0
T12	72169	1737	0	0
T13	57326	1398	0	0
T14	83317	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1596016	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1596016	0	0
T1	30321	244	0	0
T2	142115	19	0	0
T3	22396	271	0	0
T4	980	7	0	0
T5	4896	263	0	0
T10	21311	188	0	0
T11	16557	93	0	0
T12	72169	2409	0	0
T13	57326	1136	0	0
T14	83317	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3985541	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3985541	0	0
T1	30321	173	0	0
T2	142115	937	0	0
T3	22396	271	0	0
T4	980	7	0	0
T5	4896	263	0	0
T10	21311	73	0	0
T11	16557	50	0	0
T12	72169	2648	0	0
T13	57326	1136	0	0
T14	83317	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1590953	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1590953	0	0
T1	30321	295	0	0
T2	142115	36	0	0
T3	22396	287	0	0
T4	980	6	0	0
T5	4896	265	0	0
T10	21311	119	0	0
T11	16557	111	0	0
T12	72169	0	0	0
T13	57326	1435	0	0
T14	83317	33	0	0
T16	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2696358	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2696358	0	0
T1	30321	250	0	0
T2	142115	2911	0	0
T3	22396	287	0	0
T4	980	6	0	0
T5	4896	265	0	0
T10	21311	48	0	0
T11	16557	58	0	0
T12	72169	0	0	0
T13	57326	1434	0	0
T14	83317	8	0	0
T16	0	508	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1623865	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1623865	0	0
T1	30321	147	0	0
T2	142115	21	0	0
T3	22396	526	0	0
T4	980	16	0	0
T5	4896	0	0	0
T10	21311	213	0	0
T11	16557	128	0	0
T12	72169	0	0	0
T13	57326	1703	0	0
T14	83317	17	0	0
T15	0	1399	0	0
T16	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2998809	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2998809	0	0
T1	30321	118	0	0
T2	142115	2196	0	0
T3	22396	526	0	0
T4	980	16	0	0
T5	4896	0	0	0
T10	21311	36	0	0
T11	16557	36	0	0
T12	72169	0	0	0
T13	57326	1703	0	0
T14	83317	7	0	0
T15	0	109499	0	0
T16	0	574	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1542948	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1542948	0	0
T1	30321	200	0	0
T2	142115	17	0	0
T3	22396	248	0	0
T4	980	10	0	0
T5	4896	0	0	0
T10	21311	132	0	0
T11	16557	163	0	0
T12	72169	2411	0	0
T13	57326	884	0	0
T14	83317	32	0	0
T16	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3393980	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3393980	0	0
T1	30321	118	0	0
T2	142115	1330	0	0
T3	22396	247	0	0
T4	980	10	0	0
T5	4896	0	0	0
T10	21311	90	0	0
T11	16557	50	0	0
T12	72169	2200	0	0
T13	57326	884	0	0
T14	83317	6	0	0
T16	0	5551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1602813	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1602813	0	0
T1	30321	254	0	0
T2	142115	13	0	0
T3	22396	258	0	0
T4	980	15	0	0
T5	4896	213	0	0
T10	21311	177	0	0
T11	16557	103	0	0
T12	72169	0	0	0
T13	57326	681	0	0
T14	83317	14	0	0
T16	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3512725	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3512725	0	0
T1	30321	194	0	0
T2	142115	1689	0	0
T3	22396	258	0	0
T4	980	15	0	0
T5	4896	213	0	0
T10	21311	81	0	0
T11	16557	42	0	0
T12	72169	0	0	0
T13	57326	681	0	0
T14	83317	3	0	0
T16	0	1849	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1551318	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1551318	0	0
T1	30321	236	0	0
T2	142115	28	0	0
T3	22396	271	0	0
T4	980	8	0	0
T5	4896	0	0	0
T10	21311	116	0	0
T11	16557	113	0	0
T12	72169	0	0	0
T13	57326	734	0	0
T14	83317	52	0	0
T16	0	15	0	0
T17	0	13790	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2788686	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2788686	0	0
T1	30321	252	0	0
T2	142115	1850	0	0
T3	22396	271	0	0
T4	980	8	0	0
T5	4896	0	0	0
T10	21311	52	0	0
T11	16557	36	0	0
T12	72169	0	0	0
T13	57326	734	0	0
T14	83317	8	0	0
T16	0	642	0	0
T17	0	4656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1614870	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1614870	0	0
T1	30321	200	0	0
T2	142115	16	0	0
T3	22396	753	0	0
T4	980	9	0	0
T5	4896	202	0	0
T10	21311	164	0	0
T11	16557	156	0	0
T12	72169	0	0	0
T13	57326	1529	0	0
T14	83317	3	0	0
T16	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3589004	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3589004	0	0
T1	30321	179	0	0
T2	142115	2028	0	0
T3	22396	753	0	0
T4	980	9	0	0
T5	4896	202	0	0
T10	21311	51	0	0
T11	16557	58	0	0
T12	72169	0	0	0
T13	57326	1529	0	0
T14	83317	2	0	0
T16	0	2697	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1617481	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1617481	0	0
T1	30321	230	0	0
T2	142115	27	0	0
T3	22396	469	0	0
T4	980	11	0	0
T5	4896	0	0	0
T10	21311	136	0	0
T11	16557	127	0	0
T12	72169	1846	0	0
T13	57326	1561	0	0
T14	83317	27	0	0
T15	0	3144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3054434	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3054434	0	0
T1	30321	135	0	0
T2	142115	2233	0	0
T3	22396	469	0	0
T4	980	11	0	0
T5	4896	0	0	0
T10	21311	67	0	0
T11	16557	39	0	0
T12	72169	2322	0	0
T13	57326	1561	0	0
T14	83317	5	0	0
T15	0	248354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1609498	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1609498	0	0
T1	30321	280	0	0
T2	142115	42	0	0
T3	22396	256	0	0
T4	980	13	0	0
T5	4896	0	0	0
T10	21311	162	0	0
T11	16557	138	0	0
T12	72169	0	0	0
T13	57326	723	0	0
T14	83317	28	0	0
T16	0	6	0	0
T17	0	17496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2908057	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2908057	0	0
T1	30321	192	0	0
T2	142115	2964	0	0
T3	22396	256	0	0
T4	980	13	0	0
T5	4896	0	0	0
T10	21311	80	0	0
T11	16557	52	0	0
T12	72169	0	0	0
T13	57326	722	0	0
T14	83317	7	0	0
T16	0	147	0	0
T17	0	6631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1557091	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1557091	0	0
T1	30321	204	0	0
T2	142115	31	0	0
T3	22396	259	0	0
T4	980	9	0	0
T5	4896	236	0	0
T10	21311	227	0	0
T11	16557	73	0	0
T12	72169	0	0	0
T13	57326	902	0	0
T14	83317	15	0	0
T16	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3611094	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3611094	0	0
T1	30321	207	0	0
T2	142115	3923	0	0
T3	22396	259	0	0
T4	980	9	0	0
T5	4896	236	0	0
T10	21311	62	0	0
T11	16557	15	0	0
T12	72169	0	0	0
T13	57326	902	0	0
T14	83317	7	0	0
T16	0	2528	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1622640	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1622640	0	0
T1	30321	183	0	0
T2	142115	24	0	0
T3	22396	279	0	0
T4	980	11	0	0
T5	4896	487	0	0
T10	21311	143	0	0
T11	16557	160	0	0
T12	72169	0	0	0
T13	57326	1502	0	0
T14	83317	18	0	0
T16	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3739736	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3739736	0	0
T1	30321	104	0	0
T2	142115	1946	0	0
T3	22396	279	0	0
T4	980	11	0	0
T5	4896	487	0	0
T10	21311	53	0	0
T11	16557	56	0	0
T12	72169	0	0	0
T13	57326	1501	0	0
T14	83317	6	0	0
T16	0	1673	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1628923	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1628923	0	0
T1	30321	214	0	0
T2	142115	26	0	0
T3	22396	451	0	0
T4	980	4	0	0
T5	4896	0	0	0
T10	21311	121	0	0
T11	16557	144	0	0
T12	72169	1906	0	0
T13	57326	1867	0	0
T14	83317	28	0	0
T16	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3336657	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3336657	0	0
T1	30321	190	0	0
T2	142115	2253	0	0
T3	22396	450	0	0
T4	980	4	0	0
T5	4896	0	0	0
T10	21311	68	0	0
T11	16557	84	0	0
T12	72169	1902	0	0
T13	57326	1866	0	0
T14	83317	6	0	0
T16	0	2588	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1591566	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1591566	0	0
T1	30321	254	0	0
T2	142115	16	0	0
T3	22396	248	0	0
T4	980	9	0	0
T5	4896	500	0	0
T10	21311	288	0	0
T11	16557	132	0	0
T12	72169	0	0	0
T13	57326	1255	0	0
T14	83317	15	0	0
T15	0	1170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3190641	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3190641	0	0
T1	30321	198	0	0
T2	142115	1963	0	0
T3	22396	248	0	0
T4	980	9	0	0
T5	4896	500	0	0
T10	21311	71	0	0
T11	16557	57	0	0
T12	72169	0	0	0
T13	57326	1255	0	0
T14	83317	3	0	0
T15	0	97255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1613121	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1613121	0	0
T1	30321	206	0	0
T2	142115	30	0	0
T3	22396	245	0	0
T4	980	16	0	0
T5	4896	0	0	0
T10	21311	227	0	0
T11	16557	150	0	0
T12	72169	0	0	0
T13	57326	988	0	0
T14	83317	37	0	0
T16	0	5	0	0
T17	0	13454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2809098	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2809098	0	0
T1	30321	243	0	0
T2	142115	2898	0	0
T3	22396	244	0	0
T4	980	16	0	0
T5	4896	0	0	0
T10	21311	69	0	0
T11	16557	79	0	0
T12	72169	0	0	0
T13	57326	988	0	0
T14	83317	8	0	0
T16	0	314	0	0
T17	0	7236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1561384	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1561384	0	0
T1	30321	249	0	0
T2	142115	11	0	0
T3	22396	247	0	0
T4	980	12	0	0
T5	4896	0	0	0
T10	21311	197	0	0
T11	16557	103	0	0
T12	72169	0	0	0
T13	57326	487	0	0
T14	83317	11	0	0
T15	0	1236	0	0
T16	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2997597	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2997597	0	0
T1	30321	231	0	0
T2	142115	1037	0	0
T3	22396	247	0	0
T4	980	12	0	0
T5	4896	0	0	0
T10	21311	102	0	0
T11	16557	47	0	0
T12	72169	0	0	0
T13	57326	487	0	0
T14	83317	4	0	0
T15	0	109904	0	0
T16	0	2260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1587161	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1587161	0	0
T1	30321	320	0	0
T2	142115	33	0	0
T3	22396	256	0	0
T4	980	14	0	0
T5	4896	0	0	0
T10	21311	174	0	0
T11	16557	160	0	0
T12	72169	0	0	0
T13	57326	665	0	0
T14	83317	17	0	0
T16	0	21	0	0
T17	0	18011	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2481716	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2481716	0	0
T1	30321	238	0	0
T2	142115	2107	0	0
T3	22396	256	0	0
T4	980	14	0	0
T5	4896	0	0	0
T10	21311	54	0	0
T11	16557	56	0	0
T12	72169	0	0	0
T13	57326	665	0	0
T14	83317	6	0	0
T16	0	1246	0	0
T17	0	4496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1553425	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1553425	0	0
T1	30321	318	0	0
T2	142115	30	0	0
T3	22396	262	0	0
T4	980	9	0	0
T5	4896	0	0	0
T10	21311	158	0	0
T11	16557	159	0	0
T12	72169	0	0	0
T13	57326	665	0	0
T14	83317	35	0	0
T16	0	16	0	0
T17	0	13882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3118862	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3118862	0	0
T1	30321	272	0	0
T2	142115	3948	0	0
T3	22396	261	0	0
T4	980	9	0	0
T5	4896	0	0	0
T10	21311	73	0	0
T11	16557	56	0	0
T12	72169	0	0	0
T13	57326	664	0	0
T14	83317	5	0	0
T16	0	1389	0	0
T17	0	6341	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1589281	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1589281	0	0
T1	30321	190	0	0
T2	142115	49	0	0
T3	22396	266	0	0
T4	980	25	0	0
T5	4896	204	0	0
T10	21311	180	0	0
T11	16557	230	0	0
T12	72169	0	0	0
T13	57326	1504	0	0
T14	83317	24	0	0
T16	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2941579	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2941579	0	0
T1	30321	217	0	0
T2	142115	3784	0	0
T3	22396	266	0	0
T4	980	25	0	0
T5	4896	204	0	0
T10	21311	72	0	0
T11	16557	95	0	0
T12	72169	0	0	0
T13	57326	1504	0	0
T14	83317	7	0	0
T16	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1555734	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1555734	0	0
T1	30321	292	0	0
T2	142115	28	0	0
T3	22396	246	0	0
T4	980	12	0	0
T5	4896	0	0	0
T10	21311	247	0	0
T11	16557	134	0	0
T12	72169	1747	0	0
T13	57326	744	0	0
T14	83317	5	0	0
T16	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3708367	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3708367	0	0
T1	30321	238	0	0
T2	142115	2220	0	0
T3	22396	246	0	0
T4	980	12	0	0
T5	4896	0	0	0
T10	21311	58	0	0
T11	16557	84	0	0
T12	72169	1750	0	0
T13	57326	744	0	0
T14	83317	1	0	0
T16	0	1146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1623543	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1623543	0	0
T1	30321	281	0	0
T2	142115	27	0	0
T3	22396	245	0	0
T4	980	10	0	0
T5	4896	768	0	0
T10	21311	175	0	0
T11	16557	143	0	0
T12	72169	1508	0	0
T13	57326	1534	0	0
T14	83317	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3487328	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3487328	0	0
T1	30321	273	0	0
T2	142115	1544	0	0
T3	22396	245	0	0
T4	980	10	0	0
T5	4896	768	0	0
T10	21311	31	0	0
T11	16557	55	0	0
T12	72169	2067	0	0
T13	57326	1533	0	0
T14	83317	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1626333	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1626333	0	0
T1	30321	219	0	0
T2	142115	34	0	0
T3	22396	284	0	0
T4	980	19	0	0
T5	4896	0	0	0
T10	21311	217	0	0
T11	16557	121	0	0
T12	72169	4376	0	0
T13	57326	1001	0	0
T14	83317	25	0	0
T16	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	2738602	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	2738602	0	0
T1	30321	201	0	0
T2	142115	2465	0	0
T3	22396	284	0	0
T4	980	19	0	0
T5	4896	0	0	0
T10	21311	88	0	0
T11	16557	53	0	0
T12	72169	6150	0	0
T13	57326	1001	0	0
T14	83317	8	0	0
T16	0	1549	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	1586235	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	1586235	0	0
T1	30321	345	0	0
T2	142115	21	0	0
T3	22396	265	0	0
T4	980	19	0	0
T5	4896	289	0	0
T10	21311	193	0	0
T11	16557	145	0	0
T12	72169	0	0	0
T13	57326	994	0	0
T14	83317	26	0	0
T15	0	1097	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307236053	3521353	0	0
DepthKnown_A	307236053	307111494	0	0
RvalidKnown_A	307236053	307111494	0	0
WreadyKnown_A	307236053	307111494	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	3521353	0	0
T1	30321	270	0	0
T2	142115	476	0	0
T3	22396	265	0	0
T4	980	19	0	0
T5	4896	289	0	0
T10	21311	62	0	0
T11	16557	98	0	0
T12	72169	0	0	0
T13	57326	994	0	0
T14	83317	9	0	0
T15	0	88287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307236053	307111494	0	0
T1	30321	30306	0	0
T2	142115	142058	0	0
T3	22396	21326	0	0
T4	980	925	0	0
T5	4896	4883	0	0
T10	21311	21248	0	0
T11	16557	16483	0	0
T12	72169	72132	0	0
T13	57326	56837	0	0
T14	83317	83309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0