Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1738900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

274334

1

T1

2

T2

333

T3

133

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	681437	1			T1	34		T2	861		T3	292
values[0x0]	649768	1			T1	22		T2	827		T3	335
values[0x1]	682029	1			T1	30		T2	817		T3	339

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1347440	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

665794

1

T1

18

T2

797

T3

310

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6732	1			T2	10		T3	4		T4	4
valid_sources[0x01]	8033	1			T2	13		T3	4		T4	6
valid_sources[0x02]	8060	1			T2	15		T3	4		T4	3
valid_sources[0x03]	8643	1			T1	1		T2	8		T3	4
valid_sources[0x04]	7761	1			T2	11		T3	4		T4	5
valid_sources[0x05]	6877	1			T2	9		T3	4		T4	11
valid_sources[0x06]	8425	1			T2	11		T3	4		T4	4
valid_sources[0x07]	7981	1			T2	9		T3	4		T4	2
valid_sources[0x08]	9215	1			T2	9		T3	3		T4	4
valid_sources[0x09]	8616	1			T2	7		T3	3		T4	8
valid_sources[0x0a]	7506	1			T2	8		T3	4		T4	4
valid_sources[0x0b]	8025	1			T2	4		T3	4		T4	2
valid_sources[0x0c]	7418	1			T2	12		T3	4		T4	21
valid_sources[0x0d]	7458	1			T2	10		T3	4		T4	5
valid_sources[0x0e]	7693	1			T2	6		T3	3		T4	7
valid_sources[0x0f]	7514	1			T2	9		T3	5		T4	5
valid_sources[0x10]	7584	1			T2	17		T3	4		T4	5
valid_sources[0x11]	7686	1			T1	2		T2	4		T3	4
valid_sources[0x12]	7397	1			T2	12		T3	4		T4	5
valid_sources[0x13]	9039	1			T1	2		T2	6		T3	3
valid_sources[0x14]	7894	1			T2	3		T3	3		T4	16
valid_sources[0x15]	9678	1			T2	11		T3	4		T4	3
valid_sources[0x16]	7502	1			T2	15		T3	4		T4	5
valid_sources[0x17]	7656	1			T2	9		T3	4		T4	5
valid_sources[0x18]	8764	1			T1	2		T2	9		T3	4
valid_sources[0x19]	8155	1			T2	11		T3	4		T4	5
valid_sources[0x1a]	7209	1			T2	3		T3	4		T4	1
valid_sources[0x1b]	7847	1			T2	16		T3	4		T4	4
valid_sources[0x1c]	8069	1			T2	13		T3	4		T4	6
valid_sources[0x1d]	8569	1			T2	13		T3	4		T4	19
valid_sources[0x1e]	6982	1			T2	10		T3	5		T4	4
valid_sources[0x1f]	7294	1			T2	16		T3	3		T4	6
valid_sources[0x20]	7367	1			T2	10		T3	4		T4	3
valid_sources[0x21]	6601	1			T1	1		T2	7		T3	6
valid_sources[0x22]	7419	1			T2	14		T3	3		T4	7
valid_sources[0x23]	8060	1			T2	12		T3	4		T4	1
valid_sources[0x24]	7812	1			T2	6		T3	4		T4	5
valid_sources[0x25]	7683	1			T2	2		T3	3		T4	9
valid_sources[0x26]	7830	1			T2	9		T3	2		T4	8
valid_sources[0x27]	7898	1			T2	14		T3	3		T4	6
valid_sources[0x28]	7246	1			T2	9		T3	3		T4	3
valid_sources[0x29]	7387	1			T2	8		T3	4		T4	1
valid_sources[0x2a]	7590	1			T1	1		T2	9		T3	4
valid_sources[0x2b]	9247	1			T2	9		T3	4		T4	4
valid_sources[0x2c]	7276	1			T2	10		T3	4		T4	5
valid_sources[0x2d]	7688	1			T2	6		T3	4		T4	14
valid_sources[0x2e]	7122	1			T1	1		T2	4		T3	4
valid_sources[0x2f]	7859	1			T2	11		T3	4		T4	8
valid_sources[0x30]	7521	1			T2	11		T3	4		T4	3
valid_sources[0x31]	7084	1			T2	5		T3	4		T4	5
valid_sources[0x32]	7480	1			T2	15		T3	3		T4	24
valid_sources[0x33]	7041	1			T1	2		T2	7		T3	3
valid_sources[0x34]	7324	1			T1	1		T2	4		T3	3
valid_sources[0x35]	7524	1			T2	6		T3	4		T4	6
valid_sources[0x36]	8601	1			T1	4		T2	11		T3	3
valid_sources[0x37]	7555	1			T2	12		T3	4		T4	6
valid_sources[0x38]	8779	1			T2	9		T3	4		T4	6
valid_sources[0x39]	7970	1			T2	11		T3	4		T4	7
valid_sources[0x3a]	7678	1			T1	1		T2	7		T3	4
valid_sources[0x3b]	7627	1			T2	9		T3	4		T4	1
valid_sources[0x3c]	6684	1			T2	3		T3	4		T4	6
valid_sources[0x3d]	7221	1			T2	9		T3	4		T4	5
valid_sources[0x3e]	6907	1			T2	7		T3	3		T4	4
valid_sources[0x3f]	8934	1			T2	8		T3	4		T4	4
valid_sources[0x40]	7642	1			T2	19		T3	3		T4	9
valid_sources[0x41]	7631	1			T2	6		T3	5		T4	5
valid_sources[0x42]	7864	1			T2	13		T3	3		T4	4
valid_sources[0x43]	7381	1			T1	1		T2	11		T3	5
valid_sources[0x44]	7970	1			T2	16		T3	4		T4	7
valid_sources[0x45]	7444	1			T2	2		T3	3		T4	4
valid_sources[0x46]	8606	1			T2	15		T3	3		T4	7
valid_sources[0x47]	8256	1			T2	10		T3	4		T4	3
valid_sources[0x48]	7548	1			T1	1		T2	7		T3	3
valid_sources[0x49]	7882	1			T1	3		T2	9		T3	4
valid_sources[0x4a]	8567	1			T1	6		T2	6		T3	4
valid_sources[0x4b]	7807	1			T2	11		T3	4		T4	5
valid_sources[0x4c]	7937	1			T2	10		T3	4		T4	9
valid_sources[0x4d]	7843	1			T2	10		T3	4		T4	6
valid_sources[0x4e]	7824	1			T2	11		T3	4		T4	4
valid_sources[0x4f]	7535	1			T2	7		T3	4		T4	7
valid_sources[0x50]	7520	1			T2	3		T3	4		T4	5
valid_sources[0x51]	7976	1			T2	7		T3	4		T4	4
valid_sources[0x52]	7171	1			T2	13		T3	4		T4	17
valid_sources[0x53]	8555	1			T2	4		T3	3		T4	4
valid_sources[0x54]	7937	1			T2	11		T3	4		T4	8
valid_sources[0x55]	7231	1			T2	19		T3	4		T4	10
valid_sources[0x56]	7940	1			T2	10		T3	4		T4	2
valid_sources[0x57]	7498	1			T2	10		T3	4		T4	7
valid_sources[0x58]	8776	1			T2	9		T3	4		T4	4
valid_sources[0x59]	9155	1			T2	7		T3	4		T4	7
valid_sources[0x5a]	8606	1			T2	14		T3	3		T4	24
valid_sources[0x5b]	8383	1			T2	11		T3	5		T4	2
valid_sources[0x5c]	7155	1			T2	10		T3	4		T4	8
valid_sources[0x5d]	8615	1			T2	9		T3	4		T4	4
valid_sources[0x5e]	8556	1			T1	1		T2	8		T3	4
valid_sources[0x5f]	7477	1			T2	14		T3	2		T4	5
valid_sources[0x60]	8501	1			T2	9		T3	3		T4	5
valid_sources[0x61]	7697	1			T2	7		T3	3		T4	8
valid_sources[0x62]	8749	1			T2	13		T3	4		T4	5
valid_sources[0x63]	7410	1			T2	6		T3	4		T4	2
valid_sources[0x64]	6973	1			T2	14		T3	4		T4	3
valid_sources[0x65]	8056	1			T2	10		T3	4		T4	7
valid_sources[0x66]	8196	1			T2	9		T3	4		T4	6
valid_sources[0x67]	7803	1			T2	10		T3	4		T4	4
valid_sources[0x68]	8619	1			T2	6		T3	2		T4	15
valid_sources[0x69]	7965	1			T2	14		T3	4		T4	6
valid_sources[0x6a]	7992	1			T2	9		T3	3		T4	1
valid_sources[0x6b]	7250	1			T2	7		T3	3		T4	6
valid_sources[0x6c]	7963	1			T2	16		T3	4		T4	8
valid_sources[0x6d]	8721	1			T2	14		T3	4		T4	2
valid_sources[0x6e]	7057	1			T2	6		T3	4		T4	15
valid_sources[0x6f]	8428	1			T2	11		T3	4		T4	5
valid_sources[0x70]	7442	1			T2	7		T3	3		T4	6
valid_sources[0x71]	8262	1			T2	14		T3	4		T4	7
valid_sources[0x72]	7356	1			T2	9		T3	4		T4	8
valid_sources[0x73]	7657	1			T2	8		T3	4		T4	2
valid_sources[0x74]	7794	1			T1	1		T2	4		T3	4
valid_sources[0x75]	7978	1			T2	5		T3	4		T4	6
valid_sources[0x76]	7115	1			T2	13		T3	4		T4	2
valid_sources[0x77]	8420	1			T2	11		T3	4		T4	6
valid_sources[0x78]	7869	1			T2	13		T3	4		T4	11
valid_sources[0x79]	9513	1			T2	5		T3	3		T4	7
valid_sources[0x7a]	7884	1			T2	7		T3	3		T4	1
valid_sources[0x7b]	8280	1			T2	10		T3	4		T4	7
valid_sources[0x7c]	9790	1			T2	9		T3	2		T4	6
valid_sources[0x7d]	7290	1			T1	3		T2	17		T3	3
valid_sources[0x7e]	7958	1			T2	11		T3	5		T4	6
valid_sources[0x7f]	7772	1			T1	1		T2	11		T3	5
valid_sources[0x80]	7516	1			T2	9		T3	4		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29087

1

T2

35

T3

10

T4

33

values[0x0]

all_enables

biggest_size

216482

1

T1

2

T2

264

T3

108

values[0x1]

all_enables

biggest_size

28765

1

T2

34

T3

15

T4

20