Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	351448116	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351448116	0	0
T1	6610296	146555	0	0
T2	282128	12292	0	0
T3	47559736	709220	0	0
T4	2539992	63066	0	0
T5	2276512	33772	0	0
T14	1333808	19684	0	0
T15	0	625515	0	0
T17	22950984	1754664	0	0
T18	12901672	2016334	0	0
T19	5105744	73761	0	0
T20	21444304	1724447	0	0
T21	0	91373	0	0
T22	0	140	0	0
T23	0	2983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6610296	6608952	0	0
T2	282128	280504	0	0
T3	47559736	47558000	0	0
T4	2539992	2464000	0	0
T5	2276512	2275336	0	0
T14	1333808	1330336	0	0
T17	22950984	22950760	0	0
T18	12901672	12901392	0	0
T19	5105744	5102104	0	0
T20	21444304	21444024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6610296	6608952	0	0
T2	282128	280504	0	0
T3	47559736	47558000	0	0
T4	2539992	2464000	0	0
T5	2276512	2275336	0	0
T14	1333808	1330336	0	0
T17	22950984	22950760	0	0
T18	12901672	12901392	0	0
T19	5105744	5102104	0	0
T20	21444304	21444024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6610296	6608952	0	0
T2	282128	280504	0	0
T3	47559736	47558000	0	0
T4	2539992	2464000	0	0
T5	2276512	2275336	0	0
T14	1333808	1330336	0	0
T17	22950984	22950760	0	0
T18	12901672	12901392	0	0
T19	5105744	5102104	0	0
T20	21444304	21444024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	127617739	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	127617739	0	0
T1	118041	55171	0	0
T2	5038	4779	0	0
T3	849281	4450	0	0
T4	45357	26850	0	0
T5	40652	15818	0	0
T14	23818	9035	0	0
T17	409839	19107	0	0
T18	230387	12142	0	0
T19	91174	17971	0	0
T20	382934	19826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	93305483	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	93305483	0	0
T1	118041	32192	0	0
T2	5038	2505	0	0
T3	849281	350160	0	0
T4	45357	13025	0	0
T5	40652	4887	0	0
T14	23818	2977	0	0
T17	409839	156041	0	0
T18	230387	996025	0	0
T19	91174	18933	0	0
T20	382934	153163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1401081	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1401081	0	0
T1	118041	469	0	0
T2	5038	102	0	0
T3	849281	0	0	0
T4	45357	303	0	0
T5	40652	428	0	0
T14	23818	240	0	0
T15	0	17462	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	637	0	0
T20	382934	1237	0	0
T21	0	1211	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3296837	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3296837	0	0
T1	118041	5	0	0
T2	5038	102	0	0
T3	849281	0	0	0
T4	45357	390	0	0
T5	40652	107	0	0
T14	23818	81	0	0
T15	0	5299	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	685	0	0
T20	382934	93546	0	0
T21	0	197	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1437878	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1437878	0	0
T1	118041	755	0	0
T2	5038	86	0	0
T3	849281	0	0	0
T4	45357	1165	0	0
T5	40652	474	0	0
T14	23818	182	0	0
T15	0	15708	0	0
T17	409839	0	0	0
T18	230387	1166	0	0
T19	91174	740	0	0
T20	382934	0	0	0
T21	0	3405	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3771224	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3771224	0	0
T1	118041	140	0	0
T2	5038	86	0	0
T3	849281	0	0	0
T4	45357	1223	0	0
T5	40652	147	0	0
T14	23818	65	0	0
T15	0	5143	0	0
T17	409839	0	0	0
T18	230387	97982	0	0
T19	91174	783	0	0
T20	382934	0	0	0
T21	0	1056	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1393545	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1393545	0	0
T1	118041	991	0	0
T2	5038	100	0	0
T3	849281	0	0	0
T4	45357	293	0	0
T5	40652	282	0	0
T14	23818	156	0	0
T15	0	15760	0	0
T17	409839	1036	0	0
T18	230387	0	0	0
T19	91174	626	0	0
T20	382934	2635	0	0
T21	0	1246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3816100	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3816100	0	0
T1	118041	2366	0	0
T2	5038	100	0	0
T3	849281	0	0	0
T4	45357	333	0	0
T5	40652	118	0	0
T14	23818	93	0	0
T15	0	5555	0	0
T17	409839	84772	0	0
T18	230387	0	0	0
T19	91174	659	0	0
T20	382934	201185	0	0
T21	0	584	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1402882	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1402882	0	0
T1	118041	1313	0	0
T2	5038	95	0	0
T3	849281	1056	0	0
T4	45357	246	0	0
T5	40652	417	0	0
T14	23818	292	0	0
T15	0	17875	0	0
T17	409839	0	0	0
T18	230387	1098	0	0
T19	91174	620	0	0
T20	382934	0	0	0
T21	0	2816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3203677	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3203677	0	0
T1	118041	919	0	0
T2	5038	95	0	0
T3	849281	78286	0	0
T4	45357	281	0	0
T5	40652	203	0	0
T14	23818	83	0	0
T15	0	4332	0	0
T17	409839	0	0	0
T18	230387	92812	0	0
T19	91174	665	0	0
T20	382934	0	0	0
T21	0	1686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1413347	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1413347	0	0
T1	118041	775	0	0
T2	5038	89	0	0
T3	849281	1284	0	0
T4	45357	1181	0	0
T5	40652	436	0	0
T14	23818	237	0	0
T15	0	17855	0	0
T17	409839	2311	0	0
T18	230387	0	0	0
T19	91174	595	0	0
T20	382934	0	0	0
T21	0	2971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3424165	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3424165	0	0
T1	118041	1042	0	0
T2	5038	89	0	0
T3	849281	97328	0	0
T4	45357	1235	0	0
T5	40652	152	0	0
T14	23818	123	0	0
T15	0	5239	0	0
T17	409839	201823	0	0
T18	230387	0	0	0
T19	91174	626	0	0
T20	382934	0	0	0
T21	0	1139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1405308	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1405308	0	0
T1	118041	494	0	0
T2	5038	111	0	0
T3	849281	0	0	0
T4	45357	318	0	0
T5	40652	317	0	0
T14	23818	147	0	0
T15	0	12875	0	0
T17	409839	0	0	0
T18	230387	1252	0	0
T19	91174	714	0	0
T20	382934	0	0	0
T21	0	3820	0	0
T22	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	2906119	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	2906119	0	0
T1	118041	699	0	0
T2	5038	111	0	0
T3	849281	0	0	0
T4	45357	323	0	0
T5	40652	137	0	0
T14	23818	98	0	0
T15	0	4060	0	0
T17	409839	0	0	0
T18	230387	100591	0	0
T19	91174	804	0	0
T20	382934	0	0	0
T21	0	852	0	0
T22	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1437840	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1437840	0	0
T1	118041	2113	0	0
T2	5038	99	0	0
T3	849281	891	0	0
T4	45357	329	0	0
T5	40652	287	0	0
T14	23818	148	0	0
T15	0	17443	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	681	0	0
T20	382934	1151	0	0
T21	0	1715	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3316073	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3316073	0	0
T1	118041	1809	0	0
T2	5038	99	0	0
T3	849281	75114	0	0
T4	45357	386	0	0
T5	40652	135	0	0
T14	23818	78	0	0
T15	0	5654	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	785	0	0
T20	382934	86196	0	0
T21	0	1408	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1421425	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1421425	0	0
T1	118041	1209	0	0
T2	5038	76	0	0
T3	849281	0	0	0
T4	45357	335	0	0
T5	40652	426	0	0
T14	23818	239	0	0
T15	0	14320	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	643	0	0
T20	382934	974	0	0
T22	0	8	0	0
T23	0	760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	2836340	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	2836340	0	0
T1	118041	1736	0	0
T2	5038	76	0	0
T3	849281	0	0	0
T4	45357	357	0	0
T5	40652	144	0	0
T14	23818	97	0	0
T15	0	4383	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	683	0	0
T20	382934	75716	0	0
T22	0	8	0	0
T23	0	760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1406878	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1406878	0	0
T1	118041	1241	0	0
T2	5038	93	0	0
T3	849281	1219	0	0
T4	45357	216	0	0
T5	40652	397	0	0
T14	23818	162	0	0
T15	0	12706	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	571	0	0
T20	382934	0	0	0
T21	0	2262	0	0
T22	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3468080	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3468080	0	0
T1	118041	1193	0	0
T2	5038	93	0	0
T3	849281	99432	0	0
T4	45357	256	0	0
T5	40652	162	0	0
T14	23818	75	0	0
T15	0	5178	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	675	0	0
T20	382934	0	0	0
T21	0	1274	0	0
T22	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1420263	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1420263	0	0
T1	118041	541	0	0
T2	5038	96	0	0
T3	849281	0	0	0
T4	45357	310	0	0
T5	40652	312	0	0
T14	23818	234	0	0
T15	0	17358	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	733	0	0
T20	382934	1190	0	0
T21	0	1167	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3157590	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3157590	0	0
T1	118041	755	0	0
T2	5038	96	0	0
T3	849281	0	0	0
T4	45357	214	0	0
T5	40652	109	0	0
T14	23818	96	0	0
T15	0	10923	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	726	0	0
T20	382934	100178	0	0
T21	0	476	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1436847	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1436847	0	0
T1	118041	468	0	0
T2	5038	109	0	0
T3	849281	0	0	0
T4	45357	346	0	0
T5	40652	294	0	0
T14	23818	253	0	0
T15	0	18511	0	0
T17	409839	0	0	0
T18	230387	971	0	0
T19	91174	710	0	0
T20	382934	1265	0	0
T21	0	4744	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3628449	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3628449	0	0
T1	118041	1624	0	0
T2	5038	109	0	0
T3	849281	0	0	0
T4	45357	333	0	0
T5	40652	147	0	0
T14	23818	85	0	0
T15	0	7069	0	0
T17	409839	0	0	0
T18	230387	87731	0	0
T19	91174	716	0	0
T20	382934	96672	0	0
T21	0	1315	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1387903	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1387903	0	0
T1	118041	496	0	0
T2	5038	112	0	0
T3	849281	0	0	0
T4	45357	374	0	0
T5	40652	251	0	0
T14	23818	144	0	0
T15	0	19745	0	0
T17	409839	2306	0	0
T18	230387	1040	0	0
T19	91174	683	0	0
T20	382934	0	0	0
T21	0	2985	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3024691	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3024691	0	0
T1	118041	1530	0	0
T2	5038	112	0	0
T3	849281	0	0	0
T4	45357	327	0	0
T5	40652	111	0	0
T14	23818	69	0	0
T15	0	6147	0	0
T17	409839	190983	0	0
T18	230387	83071	0	0
T19	91174	638	0	0
T20	382934	0	0	0
T21	0	1065	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1414186	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1414186	0	0
T1	118041	2022	0	0
T2	5038	91	0	0
T3	849281	0	0	0
T4	45357	269	0	0
T5	40652	278	0	0
T14	23818	249	0	0
T15	0	15228	0	0
T17	409839	2064	0	0
T18	230387	0	0	0
T19	91174	600	0	0
T20	382934	1258	0	0
T21	0	1464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3797404	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3797404	0	0
T1	118041	1651	0	0
T2	5038	91	0	0
T3	849281	0	0	0
T4	45357	250	0	0
T5	40652	119	0	0
T14	23818	117	0	0
T15	0	5288	0	0
T17	409839	168663	0	0
T18	230387	0	0	0
T19	91174	694	0	0
T20	382934	101343	0	0
T21	0	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1373686	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1373686	0	0
T1	118041	870	0	0
T2	5038	90	0	0
T3	849281	0	0	0
T4	45357	548	0	0
T5	40652	291	0	0
T14	23818	250	0	0
T15	0	20886	0	0
T17	409839	1362	0	0
T18	230387	0	0	0
T19	91174	816	0	0
T20	382934	2775	0	0
T21	0	1244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3863671	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3863671	0	0
T1	118041	787	0	0
T2	5038	90	0	0
T3	849281	0	0	0
T4	45357	491	0	0
T5	40652	120	0	0
T14	23818	87	0	0
T15	0	6253	0	0
T17	409839	109316	0	0
T18	230387	0	0	0
T19	91174	695	0	0
T20	382934	199531	0	0
T21	0	520	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1438071	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1438071	0	0
T1	118041	787	0	0
T2	5038	89	0	0
T3	849281	0	0	0
T4	45357	364	0	0
T5	40652	321	0	0
T14	23818	273	0	0
T15	0	16086	0	0
T17	409839	0	0	0
T18	230387	1993	0	0
T19	91174	799	0	0
T20	382934	1205	0	0
T21	0	3450	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3718090	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3718090	0	0
T1	118041	1788	0	0
T2	5038	89	0	0
T3	849281	0	0	0
T4	45357	372	0	0
T5	40652	112	0	0
T14	23818	95	0	0
T15	0	5886	0	0
T17	409839	0	0	0
T18	230387	158982	0	0
T19	91174	841	0	0
T20	382934	103203	0	0
T21	0	703	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1415144	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1415144	0	0
T1	118041	767	0	0
T2	5038	74	0	0
T3	849281	0	0	0
T4	45357	476	0	0
T5	40652	428	0	0
T14	23818	237	0	0
T15	0	16058	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	763	0	0
T20	382934	0	0	0
T21	0	1573	0	0
T22	0	1	0	0
T23	0	732	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3479516	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3479516	0	0
T1	118041	1474	0	0
T2	5038	74	0	0
T3	849281	0	0	0
T4	45357	496	0	0
T5	40652	180	0	0
T14	23818	97	0	0
T15	0	5728	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	653	0	0
T20	382934	0	0	0
T21	0	1725	0	0
T22	0	1	0	0
T23	0	731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1424877	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1424877	0	0
T1	118041	715	0	0
T2	5038	78	0	0
T3	849281	0	0	0
T4	45357	466	0	0
T5	40652	277	0	0
T14	23818	153	0	0
T15	0	20870	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	603	0	0
T20	382934	3585	0	0
T21	0	2198	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3387492	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3387492	0	0
T1	118041	491	0	0
T2	5038	78	0	0
T3	849281	0	0	0
T4	45357	484	0	0
T5	40652	109	0	0
T14	23818	55	0	0
T15	0	8654	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	685	0	0
T20	382934	285010	0	0
T21	0	418	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1421696	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1421696	0	0
T1	118041	82	0	0
T2	5038	105	0	0
T3	849281	0	0	0
T4	45357	296	0	0
T5	40652	369	0	0
T14	23818	203	0	0
T15	0	17311	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	677	0	0
T20	382934	1327	0	0
T21	0	3120	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3575019	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3575019	0	0
T1	118041	268	0	0
T2	5038	105	0	0
T3	849281	0	0	0
T4	45357	268	0	0
T5	40652	145	0	0
T14	23818	79	0	0
T15	0	6540	0	0
T17	409839	0	0	0
T18	230387	0	0	0
T19	91174	599	0	0
T20	382934	99806	0	0
T21	0	444	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1428307	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1428307	0	0
T1	118041	1165	0	0
T2	5038	98	0	0
T3	849281	0	0	0
T4	45357	271	0	0
T5	40652	253	0	0
T14	23818	252	0	0
T15	0	16319	0	0
T17	409839	2100	0	0
T18	230387	1137	0	0
T19	91174	489	0	0
T20	382934	0	0	0
T21	0	3927	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3530114	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3530114	0	0
T1	118041	1570	0	0
T2	5038	98	0	0
T3	849281	0	0	0
T4	45357	274	0	0
T5	40652	113	0	0
T14	23818	95	0	0
T15	0	5309	0	0
T17	409839	171414	0	0
T18	230387	94901	0	0
T19	91174	492	0	0
T20	382934	0	0	0
T21	0	1376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1410544	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1410544	0	0
T1	118041	1493	0	0
T2	5038	87	0	0
T3	849281	0	0	0
T4	45357	256	0	0
T5	40652	410	0	0
T14	23818	216	0	0
T15	0	15719	0	0
T17	409839	1111	0	0
T18	230387	0	0	0
T19	91174	679	0	0
T20	382934	0	0	0
T21	0	2841	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3190463	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3190463	0	0
T1	118041	1544	0	0
T2	5038	87	0	0
T3	849281	0	0	0
T4	45357	386	0	0
T5	40652	152	0	0
T14	23818	80	0	0
T15	0	5103	0	0
T17	409839	82311	0	0
T18	230387	0	0	0
T19	91174	744	0	0
T20	382934	0	0	0
T21	0	1467	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1407712	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1407712	0	0
T1	118041	1433	0	0
T2	5038	96	0	0
T3	849281	0	0	0
T4	45357	290	0	0
T5	40652	384	0	0
T14	23818	194	0	0
T15	0	16297	0	0
T17	409839	1274	0	0
T18	230387	0	0	0
T19	91174	720	0	0
T20	382934	1223	0	0
T21	0	2589	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3437214	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3437214	0	0
T1	118041	2714	0	0
T2	5038	96	0	0
T3	849281	0	0	0
T4	45357	281	0	0
T5	40652	145	0	0
T14	23818	116	0	0
T15	0	4057	0	0
T17	409839	97223	0	0
T18	230387	0	0	0
T19	91174	788	0	0
T20	382934	89247	0	0
T21	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1403719	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1403719	0	0
T1	118041	1400	0	0
T2	5038	99	0	0
T3	849281	0	0	0
T4	45357	338	0	0
T5	40652	393	0	0
T14	23818	187	0	0
T15	0	19338	0	0
T17	409839	972	0	0
T18	230387	1121	0	0
T19	91174	776	0	0
T20	382934	0	0	0
T21	0	491	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3392284	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3392284	0	0
T1	118041	930	0	0
T2	5038	99	0	0
T3	849281	0	0	0
T4	45357	339	0	0
T5	40652	126	0	0
T14	23818	72	0	0
T15	0	7142	0	0
T17	409839	91108	0	0
T18	230387	90939	0	0
T19	91174	811	0	0
T20	382934	0	0	0
T21	0	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1418023	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1418023	0	0
T1	118041	1674	0	0
T2	5038	91	0	0
T3	849281	0	0	0
T4	45357	316	0	0
T5	40652	406	0	0
T14	23818	147	0	0
T15	0	19118	0	0
T17	409839	0	0	0
T18	230387	1334	0	0
T19	91174	509	0	0
T20	382934	0	0	0
T21	0	2405	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3302108	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3302108	0	0
T1	118041	1170	0	0
T2	5038	91	0	0
T3	849281	0	0	0
T4	45357	321	0	0
T5	40652	142	0	0
T14	23818	37	0	0
T15	0	7405	0	0
T17	409839	0	0	0
T18	230387	103094	0	0
T19	91174	675	0	0
T20	382934	0	0	0
T21	0	2430	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1388335	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1388335	0	0
T1	118041	556	0	0
T2	5038	82	0	0
T3	849281	0	0	0
T4	45357	1112	0	0
T5	40652	450	0	0
T14	23818	136	0	0
T15	0	15997	0	0
T17	409839	1039	0	0
T18	230387	0	0	0
T19	91174	555	0	0
T20	382934	0	0	0
T21	0	5058	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3060457	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3060457	0	0
T1	118041	740	0	0
T2	5038	82	0	0
T3	849281	0	0	0
T4	45357	1131	0	0
T5	40652	165	0	0
T14	23818	86	0	0
T15	0	4858	0	0
T17	409839	81365	0	0
T18	230387	0	0	0
T19	91174	615	0	0
T20	382934	0	0	0
T21	0	625	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1478586	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1478586	0	0
T1	118041	575	0	0
T2	5038	86	0	0
T3	849281	0	0	0
T4	45357	209	0	0
T5	40652	303	0	0
T14	23818	124	0	0
T15	0	16447	0	0
T17	409839	0	0	0
T18	230387	1030	0	0
T19	91174	694	0	0
T20	382934	0	0	0
T21	0	2720	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3486172	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3486172	0	0
T1	118041	774	0	0
T2	5038	86	0	0
T3	849281	0	0	0
T4	45357	302	0	0
T5	40652	111	0	0
T14	23818	61	0	0
T15	0	7825	0	0
T17	409839	0	0	0
T18	230387	85922	0	0
T19	91174	780	0	0
T20	382934	0	0	0
T21	0	1544	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1438406	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1438406	0	0
T1	118041	799	0	0
T2	5038	87	0	0
T3	849281	0	0	0
T4	45357	302	0	0
T5	40652	223	0	0
T14	23818	184	0	0
T15	0	20474	0	0
T17	409839	2534	0	0
T18	230387	0	0	0
T19	91174	570	0	0
T20	382934	0	0	0
T21	0	4342	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3502119	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3502119	0	0
T1	118041	1476	0	0
T2	5038	87	0	0
T3	849281	0	0	0
T4	45357	332	0	0
T5	40652	100	0	0
T14	23818	74	0	0
T15	0	6527	0	0
T17	409839	200685	0	0
T18	230387	0	0	0
T19	91174	650	0	0
T20	382934	0	0	0
T21	0	232	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	1464778	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	1464778	0	0
T1	118041	1797	0	0
T2	5038	83	0	0
T3	849281	0	0	0
T4	45357	430	0	0
T5	40652	339	0	0
T14	23818	173	0	0
T15	0	17667	0	0
T17	409839	996	0	0
T18	230387	0	0	0
T19	91174	760	0	0
T20	382934	0	0	0
T21	0	828	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314539398	3662159	0	0
DepthKnown_A	314539398	314421803	0	0
RvalidKnown_A	314539398	314421803	0	0
WreadyKnown_A	314539398	314421803	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	3662159	0	0
T1	118041	997	0	0
T2	5038	83	0	0
T3	849281	0	0	0
T4	45357	447	0	0
T5	40652	110	0	0
T14	23818	66	0	0
T15	0	8525	0	0
T17	409839	80748	0	0
T18	230387	0	0	0
T19	91174	727	0	0
T20	382934	0	0	0
T21	0	1409	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314539398	314421803	0	0
T1	118041	118017	0	0
T2	5038	5009	0	0
T3	849281	849250	0	0
T4	45357	44000	0	0
T5	40652	40631	0	0
T14	23818	23756	0	0
T17	409839	409835	0	0
T18	230387	230382	0	0
T19	91174	91109	0	0
T20	382934	382929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0