Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1831948	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

288682

1

T1

268

T2

11

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	715643	1			T1	622		T2	43		T3	20
values[0x0]	688081	1			T1	612		T2	38		T3	3
values[0x1]	716906	1			T1	663		T2	31		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1420917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

699713

1

T1

595

T2

39

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9052	1			T5	6		T17	10		T15	10
valid_sources[0x01]	7499	1			T4	3		T5	6		T17	2
valid_sources[0x02]	8712	1			T1	13		T4	4		T5	5
valid_sources[0x03]	9356	1			T1	18		T5	17		T17	8
valid_sources[0x04]	8137	1			T1	26		T4	5		T5	5
valid_sources[0x05]	9461	1			T4	9		T5	6		T17	8
valid_sources[0x06]	9120	1			T1	15		T5	8		T17	8
valid_sources[0x07]	7560	1			T4	1		T5	6		T17	5
valid_sources[0x08]	8637	1			T1	13		T5	3		T17	7
valid_sources[0x09]	8144	1			T4	5		T5	6		T17	3
valid_sources[0x0a]	7604	1			T4	9		T5	9		T17	2
valid_sources[0x0b]	8865	1			T4	10		T5	14		T17	9
valid_sources[0x0c]	8375	1			T1	14		T4	10		T5	7
valid_sources[0x0d]	9359	1			T1	23		T4	2		T5	8
valid_sources[0x0e]	8413	1			T1	14		T4	2		T5	5
valid_sources[0x0f]	8161	1			T4	1		T5	10		T17	5
valid_sources[0x10]	8389	1			T1	13		T5	8		T17	8
valid_sources[0x11]	9359	1			T2	20		T4	3		T5	6
valid_sources[0x12]	8541	1			T1	6		T4	2		T5	3
valid_sources[0x13]	8456	1			T1	23		T5	6		T17	3
valid_sources[0x14]	8163	1			T1	17		T5	8		T17	5
valid_sources[0x15]	7818	1			T4	3		T5	9		T17	6
valid_sources[0x16]	8262	1			T1	15		T4	2		T5	12
valid_sources[0x17]	9652	1			T1	17		T4	3		T5	3
valid_sources[0x18]	7016	1			T4	12		T5	8		T17	5
valid_sources[0x19]	7758	1			T1	12		T3	1		T4	4
valid_sources[0x1a]	8444	1			T1	14		T5	2		T17	4
valid_sources[0x1b]	8448	1			T3	1		T4	2		T5	13
valid_sources[0x1c]	7882	1			T1	9		T5	4		T17	8
valid_sources[0x1d]	7455	1			T1	11		T4	2		T5	4
valid_sources[0x1e]	7730	1			T4	4		T5	12		T17	12
valid_sources[0x1f]	7388	1			T1	11		T4	2		T5	11
valid_sources[0x20]	8972	1			T1	38		T4	3		T5	3
valid_sources[0x21]	8606	1			T4	5		T5	3		T17	5
valid_sources[0x22]	7568	1			T1	9		T4	2		T5	5
valid_sources[0x23]	9199	1			T5	5		T17	8		T15	11
valid_sources[0x24]	7834	1			T4	1		T5	5		T17	9
valid_sources[0x25]	8216	1			T4	2		T5	8		T17	14
valid_sources[0x26]	7968	1			T4	5		T5	5		T17	5
valid_sources[0x27]	7733	1			T5	8		T17	11		T15	11
valid_sources[0x28]	7678	1			T1	8		T2	15		T4	1
valid_sources[0x29]	10085	1			T4	3		T5	11		T17	3
valid_sources[0x2a]	8301	1			T2	14		T3	1		T5	7
valid_sources[0x2b]	8900	1			T1	11		T4	3		T5	13
valid_sources[0x2c]	7618	1			T1	16		T4	3		T5	5
valid_sources[0x2d]	7093	1			T1	12		T4	13		T5	7
valid_sources[0x2e]	8291	1			T1	29		T4	7		T5	8
valid_sources[0x2f]	7907	1			T1	21		T4	2		T5	3
valid_sources[0x30]	8359	1			T1	12		T3	1		T5	14
valid_sources[0x31]	7465	1			T4	7		T5	9		T17	8
valid_sources[0x32]	8158	1			T5	8		T17	6		T15	11
valid_sources[0x33]	7756	1			T4	5		T5	10		T17	3
valid_sources[0x34]	8278	1			T4	2		T5	10		T17	5
valid_sources[0x35]	8921	1			T4	5		T5	5		T17	5
valid_sources[0x36]	8708	1			T3	1		T4	1		T5	8
valid_sources[0x37]	8190	1			T1	18		T3	1		T4	4
valid_sources[0x38]	9344	1			T4	8		T5	11		T17	9
valid_sources[0x39]	8526	1			T5	9		T17	9		T15	10
valid_sources[0x3a]	8629	1			T1	30		T4	2		T5	6
valid_sources[0x3b]	7820	1			T5	9		T17	4		T15	11
valid_sources[0x3c]	7542	1			T4	4		T5	10		T17	3
valid_sources[0x3d]	7557	1			T1	8		T3	1		T5	5
valid_sources[0x3e]	8381	1			T4	2		T5	5		T17	5
valid_sources[0x3f]	7760	1			T3	1		T4	1		T5	7
valid_sources[0x40]	7493	1			T1	21		T4	12		T5	8
valid_sources[0x41]	8152	1			T1	10		T5	7		T17	4
valid_sources[0x42]	8358	1			T1	10		T5	4		T17	5
valid_sources[0x43]	8992	1			T3	2		T4	10		T5	14
valid_sources[0x44]	8021	1			T1	5		T4	3		T5	13
valid_sources[0x45]	8655	1			T1	11		T3	1		T4	1
valid_sources[0x46]	8297	1			T1	20		T5	8		T17	8
valid_sources[0x47]	8510	1			T1	19		T4	2		T5	5
valid_sources[0x48]	8903	1			T4	4		T5	9		T17	10
valid_sources[0x49]	8661	1			T4	1		T5	7		T17	12
valid_sources[0x4a]	8410	1			T1	13		T5	11		T17	11
valid_sources[0x4b]	8660	1			T4	8		T5	10		T17	8
valid_sources[0x4c]	7811	1			T3	1		T4	3		T5	13
valid_sources[0x4d]	8602	1			T1	19		T5	7		T17	9
valid_sources[0x4e]	8473	1			T4	6		T5	5		T17	10
valid_sources[0x4f]	8655	1			T4	4		T5	10		T17	8
valid_sources[0x50]	7896	1			T5	8		T17	3		T15	11
valid_sources[0x51]	7714	1			T1	13		T4	6		T5	5
valid_sources[0x52]	8786	1			T4	3		T5	8		T17	5
valid_sources[0x53]	8620	1			T1	5		T5	13		T17	10
valid_sources[0x54]	8022	1			T1	34		T5	2		T17	5
valid_sources[0x55]	8302	1			T4	3		T5	9		T17	5
valid_sources[0x56]	7848	1			T1	8		T4	9		T5	5
valid_sources[0x57]	9894	1			T1	17		T5	2		T17	2
valid_sources[0x58]	8151	1			T3	1		T4	4		T5	6
valid_sources[0x59]	7719	1			T1	11		T5	3		T17	3
valid_sources[0x5a]	8307	1			T5	6		T17	13		T15	10
valid_sources[0x5b]	8913	1			T5	14		T17	4		T15	10
valid_sources[0x5c]	7478	1			T4	3		T5	9		T17	3
valid_sources[0x5d]	8152	1			T3	1		T4	3		T5	6
valid_sources[0x5e]	8020	1			T3	1		T4	5		T5	4
valid_sources[0x5f]	8399	1			T4	3		T5	10		T17	6
valid_sources[0x60]	9667	1			T3	1		T5	3		T17	5
valid_sources[0x61]	8605	1			T1	13		T4	1		T5	8
valid_sources[0x62]	8899	1			T1	13		T4	6		T5	13
valid_sources[0x63]	9102	1			T1	10		T5	8		T17	7
valid_sources[0x64]	8812	1			T4	1		T5	10		T17	7
valid_sources[0x65]	8684	1			T1	14		T4	2		T5	11
valid_sources[0x66]	8126	1			T1	19		T4	5		T5	9
valid_sources[0x67]	9435	1			T1	10		T5	10		T17	2
valid_sources[0x68]	9624	1			T4	2		T5	4		T17	5
valid_sources[0x69]	7782	1			T4	1		T5	4		T17	8
valid_sources[0x6a]	7078	1			T4	3		T5	6		T17	5
valid_sources[0x6b]	7518	1			T4	1		T5	13		T17	8
valid_sources[0x6c]	8966	1			T5	5		T17	14		T15	11
valid_sources[0x6d]	7230	1			T1	19		T4	5		T5	9
valid_sources[0x6e]	9359	1			T1	31		T4	7		T5	7
valid_sources[0x6f]	9140	1			T5	6		T17	8		T15	10
valid_sources[0x70]	7982	1			T5	6		T17	7		T15	9
valid_sources[0x71]	8460	1			T4	7		T5	5		T17	11
valid_sources[0x72]	8023	1			T4	3		T5	5		T17	9
valid_sources[0x73]	9264	1			T1	19		T4	7		T5	3
valid_sources[0x74]	7494	1			T1	29		T4	4		T5	8
valid_sources[0x75]	7844	1			T5	11		T17	7		T15	11
valid_sources[0x76]	7923	1			T1	13		T4	2		T5	8
valid_sources[0x77]	8267	1			T5	6		T17	14		T15	11
valid_sources[0x78]	8214	1			T4	3		T5	6		T17	11
valid_sources[0x79]	7994	1			T1	18		T4	1		T5	2
valid_sources[0x7a]	8617	1			T1	18		T4	5		T5	9
valid_sources[0x7b]	8389	1			T1	15		T5	6		T17	8
valid_sources[0x7c]	7501	1			T3	1		T4	2		T5	7
valid_sources[0x7d]	8667	1			T4	1		T5	4		T17	5
valid_sources[0x7e]	9013	1			T4	8		T5	6		T17	5
valid_sources[0x7f]	8132	1			T5	3		T17	7		T15	9
valid_sources[0x80]	8896	1			T1	19		T17	5		T15	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30285

1

T1

29

T3

1

T4

17

values[0x0]

all_enables

biggest_size

228388

1

T1

205

T2

11

T3

2

values[0x1]

all_enables

biggest_size

30009

1

T1

34

T3

2

T4

7