Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	319472218	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319472218	0	0
T1	3919720	55477	0	0
T2	16520	547	0	0
T3	120512	3708	0	0
T4	733208	10236	0	0
T5	52477936	937034	0	0
T15	13870248	2004678	0	0
T16	0	16694	0	0
T17	9333688	1401017	0	0
T18	137088	5246	0	0
T19	5975872	196946	0	0
T20	170800	6974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3919720	3918992	0	0
T2	16520	15960	0	0
T3	120512	117208	0	0
T4	733208	730576	0	0
T5	52477936	52476536	0	0
T15	13870248	13870024	0	0
T17	9333688	9333408	0	0
T18	137088	134456	0	0
T19	5975872	5971448	0	0
T20	170800	168280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3919720	3918992	0	0
T2	16520	15960	0	0
T3	120512	117208	0	0
T4	733208	730576	0	0
T5	52477936	52476536	0	0
T15	13870248	13870024	0	0
T17	9333688	9333408	0	0
T18	137088	134456	0	0
T19	5975872	5971448	0	0
T20	170800	168280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3919720	3918992	0	0
T2	16520	15960	0	0
T3	120512	117208	0	0
T4	733208	730576	0	0
T5	52477936	52476536	0	0
T15	13870248	13870024	0	0
T17	9333688	9333408	0	0
T18	137088	134456	0	0
T19	5975872	5971448	0	0
T20	170800	168280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T15	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	119259209	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	119259209	0	0
T1	69995	14225	0	0
T2	295	211	0	0
T3	2152	1709	0	0
T4	13093	4578	0	0
T5	937106	916855	0	0
T15	247683	12508	0	0
T17	166673	164432	0	0
T18	2448	2042	0	0
T19	106712	104500	0	0
T20	3050	2708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	80996244	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	80996244	0	0
T1	69995	13538	0	0
T2	295	112	0	0
T3	2152	999	0	0
T4	13093	1599	0	0
T5	937106	5916	0	0
T15	247683	989832	0	0
T17	166673	615097	0	0
T18	2448	1068	0	0
T19	106712	45973	0	0
T20	3050	1422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1404673	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1404673	0	0
T1	69995	576	0	0
T2	295	7	0	0
T3	2152	19	0	0
T4	13093	174	0	0
T5	937106	366	0	0
T15	247683	0	0	0
T16	0	690	0	0
T17	166673	251	0	0
T18	2448	49	0	0
T19	106712	13	0	0
T20	3050	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2209591	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2209591	0	0
T1	69995	561	0	0
T2	295	7	0	0
T3	2152	19	0	0
T4	13093	61	0	0
T5	937106	78	0	0
T15	247683	0	0	0
T16	0	690	0	0
T17	166673	17949	0	0
T18	2448	49	0	0
T19	106712	1459	0	0
T20	3050	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1421992	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1421992	0	0
T1	69995	537	0	0
T2	295	5	0	0
T3	2152	18	0	0
T4	13093	52	0	0
T5	937106	266	0	0
T15	247683	990	0	0
T17	166673	268	0	0
T18	2448	39	0	0
T19	106712	31	0	0
T20	3050	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2887151	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2887151	0	0
T1	69995	456	0	0
T2	295	5	0	0
T3	2152	18	0	0
T4	13093	21	0	0
T5	937106	378	0	0
T15	247683	79649	0	0
T17	166673	22870	0	0
T18	2448	39	0	0
T19	106712	1529	0	0
T20	3050	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1441950	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1441950	0	0
T1	69995	634	0	0
T2	295	6	0	0
T3	2152	17	0	0
T4	13093	54	0	0
T5	937106	303	0	0
T15	247683	0	0	0
T16	0	395	0	0
T17	166673	247	0	0
T18	2448	36	0	0
T19	106712	49	0	0
T20	3050	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3383960	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3383960	0	0
T1	69995	533	0	0
T2	295	6	0	0
T3	2152	17	0	0
T4	13093	23	0	0
T5	937106	58	0	0
T15	247683	0	0	0
T16	0	395	0	0
T17	166673	21063	0	0
T18	2448	36	0	0
T19	106712	3001	0	0
T20	3050	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1449221	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1449221	0	0
T1	69995	508	0	0
T2	295	3	0	0
T3	2152	18	0	0
T4	13093	110	0	0
T5	937106	259	0	0
T15	247683	0	0	0
T16	0	371	0	0
T17	166673	251	0	0
T18	2448	38	0	0
T19	106712	24	0	0
T20	3050	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3165147	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3165147	0	0
T1	69995	534	0	0
T2	295	3	0	0
T3	2152	18	0	0
T4	13093	41	0	0
T5	937106	59	0	0
T15	247683	0	0	0
T16	0	371	0	0
T17	166673	20761	0	0
T18	2448	38	0	0
T19	106712	2261	0	0
T20	3050	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1443238	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1443238	0	0
T1	69995	569	0	0
T2	295	2	0	0
T3	2152	21	0	0
T4	13093	117	0	0
T5	937106	260	0	0
T15	247683	0	0	0
T16	0	930	0	0
T17	166673	230	0	0
T18	2448	32	0	0
T19	106712	8	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2727253	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2727253	0	0
T1	69995	498	0	0
T2	295	2	0	0
T3	2152	21	0	0
T4	13093	74	0	0
T5	937106	1334	0	0
T15	247683	0	0	0
T16	0	930	0	0
T17	166673	17575	0	0
T18	2448	32	0	0
T19	106712	673	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1484698	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1484698	0	0
T1	69995	643	0	0
T2	295	2	0	0
T3	2152	13	0	0
T4	13093	82	0	0
T5	937106	297	0	0
T15	247683	1184	0	0
T17	166673	244	0	0
T18	2448	39	0	0
T19	106712	16	0	0
T20	3050	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3383998	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3383998	0	0
T1	69995	590	0	0
T2	295	2	0	0
T3	2152	13	0	0
T4	13093	24	0	0
T5	937106	68	0	0
T15	247683	93036	0	0
T17	166673	18634	0	0
T18	2448	39	0	0
T19	106712	743	0	0
T20	3050	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1514193	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1514193	0	0
T1	69995	567	0	0
T2	295	1	0	0
T3	2152	16	0	0
T4	13093	81	0	0
T5	937106	355	0	0
T15	247683	1438	0	0
T17	166673	278	0	0
T18	2448	35	0	0
T19	106712	7	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2692248	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2692248	0	0
T1	69995	481	0	0
T2	295	1	0	0
T3	2152	16	0	0
T4	13093	47	0	0
T5	937106	233	0	0
T15	247683	110915	0	0
T17	166673	24824	0	0
T18	2448	35	0	0
T19	106712	458	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1489671	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1489671	0	0
T1	69995	453	0	0
T2	295	4	0	0
T3	2152	20	0	0
T4	13093	107	0	0
T5	937106	354	0	0
T15	247683	0	0	0
T16	0	689	0	0
T17	166673	407	0	0
T18	2448	44	0	0
T19	106712	19	0	0
T20	3050	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2642811	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2642811	0	0
T1	69995	486	0	0
T2	295	4	0	0
T3	2152	20	0	0
T4	13093	37	0	0
T5	937106	73	0	0
T15	247683	0	0	0
T16	0	689	0	0
T17	166673	32978	0	0
T18	2448	44	0	0
T19	106712	1943	0	0
T20	3050	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1497347	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1497347	0	0
T1	69995	522	0	0
T2	295	3	0	0
T3	2152	15	0	0
T4	13093	88	0	0
T5	937106	277	0	0
T15	247683	1029	0	0
T17	166673	228	0	0
T18	2448	46	0	0
T19	106712	26	0	0
T20	3050	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3271393	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3271393	0	0
T1	69995	562	0	0
T2	295	3	0	0
T3	2152	15	0	0
T4	13093	55	0	0
T5	937106	398	0	0
T15	247683	81985	0	0
T17	166673	21022	0	0
T18	2448	46	0	0
T19	106712	2824	0	0
T20	3050	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1436852	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1436852	0	0
T1	69995	582	0	0
T2	295	3	0	0
T3	2152	20	0	0
T4	13093	167	0	0
T5	937106	366	0	0
T15	247683	1149	0	0
T17	166673	277	0	0
T18	2448	43	0	0
T19	106712	33	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2482051	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2482051	0	0
T1	69995	521	0	0
T2	295	3	0	0
T3	2152	20	0	0
T4	13093	63	0	0
T5	937106	383	0	0
T15	247683	104426	0	0
T17	166673	20058	0	0
T18	2448	43	0	0
T19	106712	3059	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1488880	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1488880	0	0
T1	69995	617	0	0
T2	295	4	0	0
T3	2152	16	0	0
T4	13093	147	0	0
T5	937106	286	0	0
T15	247683	1044	0	0
T17	166673	281	0	0
T18	2448	32	0	0
T19	106712	23	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2709967	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2709967	0	0
T1	69995	515	0	0
T2	295	4	0	0
T3	2152	16	0	0
T4	13093	93	0	0
T5	937106	64	0	0
T15	247683	81801	0	0
T17	166673	27267	0	0
T18	2448	32	0	0
T19	106712	1850	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1465169	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1465169	0	0
T1	69995	471	0	0
T2	295	3	0	0
T3	2152	24	0	0
T4	13093	42	0	0
T5	937106	279	0	0
T15	247683	0	0	0
T16	0	403	0	0
T17	166673	223	0	0
T18	2448	42	0	0
T19	106712	2	0	0
T20	3050	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2529938	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2529938	0	0
T1	69995	493	0	0
T2	295	3	0	0
T3	2152	24	0	0
T4	13093	29	0	0
T5	937106	72	0	0
T15	247683	0	0	0
T16	0	403	0	0
T17	166673	17843	0	0
T18	2448	42	0	0
T19	106712	271	0	0
T20	3050	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1446688	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1446688	0	0
T1	69995	645	0	0
T2	295	6	0	0
T3	2152	20	0	0
T4	13093	137	0	0
T5	937106	357	0	0
T15	247683	1287	0	0
T17	166673	266	0	0
T18	2448	38	0	0
T19	106712	14	0	0
T20	3050	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2806747	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2806747	0	0
T1	69995	617	0	0
T2	295	6	0	0
T3	2152	20	0	0
T4	13093	51	0	0
T5	937106	79	0	0
T15	247683	102326	0	0
T17	166673	21943	0	0
T18	2448	38	0	0
T19	106712	1469	0	0
T20	3050	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1454650	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1454650	0	0
T1	69995	578	0	0
T2	295	4	0	0
T3	2152	17	0	0
T4	13093	141	0	0
T5	937106	227	0	0
T15	247683	0	0	0
T16	0	393	0	0
T17	166673	205	0	0
T18	2448	37	0	0
T19	106712	20	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2856047	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2856047	0	0
T1	69995	551	0	0
T2	295	4	0	0
T3	2152	17	0	0
T4	13093	74	0	0
T5	937106	206	0	0
T15	247683	0	0	0
T16	0	393	0	0
T17	166673	20413	0	0
T18	2448	37	0	0
T19	106712	3085	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1390041	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1390041	0	0
T1	69995	410	0	0
T2	295	5	0	0
T3	2152	16	0	0
T4	13093	58	0	0
T5	937106	342	0	0
T15	247683	1088	0	0
T17	166673	232	0	0
T18	2448	35	0	0
T19	106712	24	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3157808	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3157808	0	0
T1	69995	360	0	0
T2	295	5	0	0
T3	2152	16	0	0
T4	13093	20	0	0
T5	937106	69	0	0
T15	247683	82243	0	0
T17	166673	24020	0	0
T18	2448	35	0	0
T19	106712	1520	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1500488	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1500488	0	0
T1	69995	539	0	0
T2	295	6	0	0
T3	2152	18	0	0
T4	13093	142	0	0
T5	937106	318	0	0
T15	247683	0	0	0
T16	0	390	0	0
T17	166673	291	0	0
T18	2448	43	0	0
T19	106712	21	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3329492	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3329492	0	0
T1	69995	570	0	0
T2	295	6	0	0
T3	2152	18	0	0
T4	13093	44	0	0
T5	937106	75	0	0
T15	247683	0	0	0
T16	0	390	0	0
T17	166673	28093	0	0
T18	2448	43	0	0
T19	106712	1019	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1493562	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1493562	0	0
T1	69995	577	0	0
T2	295	4	0	0
T3	2152	21	0	0
T4	13093	78	0	0
T5	937106	342	0	0
T15	247683	0	0	0
T16	0	336	0	0
T17	166673	257	0	0
T18	2448	29	0	0
T19	106712	17	0	0
T20	3050	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3631244	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3631244	0	0
T1	69995	405	0	0
T2	295	4	0	0
T3	2152	21	0	0
T4	13093	24	0	0
T5	937106	732	0	0
T15	247683	0	0	0
T16	0	336	0	0
T17	166673	23195	0	0
T18	2448	29	0	0
T19	106712	2207	0	0
T20	3050	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1453842	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1453842	0	0
T1	69995	577	0	0
T2	295	3	0	0
T3	2152	28	0	0
T4	13093	135	0	0
T5	937106	302	0	0
T15	247683	1130	0	0
T17	166673	261	0	0
T18	2448	45	0	0
T19	106712	21	0	0
T20	3050	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2981867	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2981867	0	0
T1	69995	503	0	0
T2	295	3	0	0
T3	2152	28	0	0
T4	13093	43	0	0
T5	937106	73	0	0
T15	247683	87094	0	0
T17	166673	23632	0	0
T18	2448	45	0	0
T19	106712	1548	0	0
T20	3050	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1425160	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1425160	0	0
T1	69995	420	0	0
T2	295	4	0	0
T3	2152	18	0	0
T4	13093	110	0	0
T5	937106	279	0	0
T15	247683	0	0	0
T16	0	586	0	0
T17	166673	336	0	0
T18	2448	54	0	0
T19	106712	2	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3295257	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3295257	0	0
T1	69995	432	0	0
T2	295	4	0	0
T3	2152	18	0	0
T4	13093	99	0	0
T5	937106	62	0	0
T15	247683	0	0	0
T16	0	586	0	0
T17	166673	32144	0	0
T18	2448	54	0	0
T19	106712	1043	0	0
T20	3050	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1423880	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1423880	0	0
T1	69995	460	0	0
T2	295	7	0	0
T3	2152	26	0	0
T4	13093	148	0	0
T5	937106	357	0	0
T15	247683	1210	0	0
T17	166673	279	0	0
T18	2448	40	0	0
T19	106712	31	0	0
T20	3050	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3202475	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3202475	0	0
T1	69995	426	0	0
T2	295	7	0	0
T3	2152	26	0	0
T4	13093	52	0	0
T5	937106	79	0	0
T15	247683	97424	0	0
T17	166673	20162	0	0
T18	2448	40	0	0
T19	106712	3544	0	0
T20	3050	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1437630	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1437630	0	0
T1	69995	631	0	0
T2	295	3	0	0
T3	2152	22	0	0
T4	13093	90	0	0
T5	937106	351	0	0
T15	247683	0	0	0
T16	0	394	0	0
T17	166673	256	0	0
T18	2448	43	0	0
T19	106712	14	0	0
T20	3050	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2306419	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2306419	0	0
T1	69995	691	0	0
T2	295	3	0	0
T3	2152	22	0	0
T4	13093	19	0	0
T5	937106	65	0	0
T15	247683	0	0	0
T16	0	394	0	0
T17	166673	26463	0	0
T18	2448	43	0	0
T19	106712	2336	0	0
T20	3050	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1453252	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1453252	0	0
T1	69995	492	0	0
T2	295	1	0	0
T3	2152	14	0	0
T4	13093	117	0	0
T5	937106	221	0	0
T15	247683	0	0	0
T16	0	412	0	0
T17	166673	245	0	0
T18	2448	44	0	0
T19	106712	16	0	0
T20	3050	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3587890	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3587890	0	0
T1	69995	450	0	0
T2	295	1	0	0
T3	2152	14	0	0
T4	13093	48	0	0
T5	937106	355	0	0
T15	247683	0	0	0
T16	0	412	0	0
T17	166673	21692	0	0
T18	2448	44	0	0
T19	106712	2568	0	0
T20	3050	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1471368	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1471368	0	0
T1	69995	398	0	0
T2	295	5	0	0
T3	2152	10	0	0
T4	13093	50	0	0
T5	937106	291	0	0
T15	247683	0	0	0
T16	0	683	0	0
T17	166673	321	0	0
T18	2448	37	0	0
T19	106712	23	0	0
T20	3050	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2937553	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2937553	0	0
T1	69995	360	0	0
T2	295	5	0	0
T3	2152	10	0	0
T4	13093	29	0	0
T5	937106	393	0	0
T15	247683	0	0	0
T16	0	683	0	0
T17	166673	26570	0	0
T18	2448	37	0	0
T19	106712	1760	0	0
T20	3050	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1436719	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1436719	0	0
T1	69995	547	0	0
T2	295	2	0	0
T3	2152	20	0	0
T4	13093	97	0	0
T5	937106	316	0	0
T15	247683	0	0	0
T16	0	390	0	0
T17	166673	231	0	0
T18	2448	34	0	0
T19	106712	7	0	0
T20	3050	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2610769	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2610769	0	0
T1	69995	512	0	0
T2	295	2	0	0
T3	2152	20	0	0
T4	13093	35	0	0
T5	937106	69	0	0
T15	247683	0	0	0
T16	0	390	0	0
T17	166673	21459	0	0
T18	2448	34	0	0
T19	106712	1003	0	0
T20	3050	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1518326	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1518326	0	0
T1	69995	461	0	0
T2	295	8	0	0
T3	2152	20	0	0
T4	13093	58	0	0
T5	937106	422	0	0
T15	247683	958	0	0
T17	166673	274	0	0
T18	2448	32	0	0
T19	106712	2	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2887429	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2887429	0	0
T1	69995	524	0	0
T2	295	8	0	0
T3	2152	20	0	0
T4	13093	25	0	0
T5	937106	89	0	0
T15	247683	68932	0	0
T17	166673	24397	0	0
T18	2448	32	0	0
T19	106712	572	0	0
T20	3050	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1475142	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1475142	0	0
T1	69995	446	0	0
T2	295	8	0	0
T3	2152	11	0	0
T4	13093	154	0	0
T5	937106	255	0	0
T15	247683	0	0	0
T16	0	901	0	0
T17	166673	260	0	0
T18	2448	52	0	0
T19	106712	14	0	0
T20	3050	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	3221559	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	3221559	0	0
T1	69995	460	0	0
T2	295	8	0	0
T3	2152	11	0	0
T4	13093	57	0	0
T5	937106	300	0	0
T15	247683	0	0	0
T16	0	901	0	0
T17	166673	19207	0	0
T18	2448	52	0	0
T19	106712	896	0	0
T20	3050	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	1425764	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	1425764	0	0
T1	69995	358	0	0
T2	295	3	0	0
T3	2152	22	0	0
T4	13093	106	0	0
T5	937106	300	0	0
T15	247683	0	0	0
T16	0	384	0	0
T17	166673	267	0	0
T18	2448	30	0	0
T19	106712	23	0	0
T20	3050	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297530144	2974305	0	0
DepthKnown_A	297530144	297398784	0	0
RvalidKnown_A	297530144	297398784	0	0
WreadyKnown_A	297530144	297398784	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	2974305	0	0
T1	69995	405	0	0
T2	295	3	0	0
T3	2152	22	0	0
T4	13093	29	0	0
T5	937106	71	0	0
T15	247683	0	0	0
T16	0	384	0	0
T17	166673	18088	0	0
T18	2448	30	0	0
T19	106712	1332	0	0
T20	3050	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297530144	297398784	0	0
T1	69995	69982	0	0
T2	295	285	0	0
T3	2152	2093	0	0
T4	13093	13046	0	0
T5	937106	937081	0	0
T15	247683	247679	0	0
T17	166673	166668	0	0
T18	2448	2401	0	0
T19	106712	106633	0	0
T20	3050	3005	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0