Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1729020	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

270865

1

T1

138

T2

27

T3

163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	677569	1			T1	265		T2	63		T3	359
values[0x0]	644473	1			T1	273		T2	61		T3	373
values[0x1]	677843	1			T1	263		T2	65		T3	395

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1339236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

660649

1

T1

283

T2

65

T3

389

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7728	1			T3	5		T20	4		T17	34
valid_sources[0x01]	8192	1			T2	2		T3	4		T20	3
valid_sources[0x02]	7620	1			T3	4		T14	3		T20	8
valid_sources[0x03]	7985	1			T2	2		T3	2		T14	1
valid_sources[0x04]	6780	1			T1	2		T2	3		T3	4
valid_sources[0x05]	7108	1			T1	4		T3	5		T20	2
valid_sources[0x06]	7431	1			T2	1		T3	4		T20	11
valid_sources[0x07]	7577	1			T2	1		T3	4		T20	19
valid_sources[0x08]	7744	1			T3	4		T20	4		T17	3
valid_sources[0x09]	7712	1			T1	7		T2	9		T3	3
valid_sources[0x0a]	7968	1			T1	2		T3	4		T14	3
valid_sources[0x0b]	7897	1			T2	2		T3	4		T20	19
valid_sources[0x0c]	8355	1			T1	16		T2	8		T3	5
valid_sources[0x0d]	7013	1			T2	1		T3	4		T14	11
valid_sources[0x0e]	8147	1			T2	1		T3	5		T20	8
valid_sources[0x0f]	8279	1			T2	5		T3	4		T21	13
valid_sources[0x10]	7051	1			T2	1		T3	4		T5	22
valid_sources[0x11]	7483	1			T2	1		T3	4		T20	34
valid_sources[0x12]	8604	1			T2	2		T3	4		T14	2
valid_sources[0x13]	8883	1			T3	4		T20	2		T17	1
valid_sources[0x14]	7405	1			T1	6		T2	2		T3	5
valid_sources[0x15]	7442	1			T3	4		T6	1		T20	24
valid_sources[0x16]	7798	1			T2	2		T3	5		T5	5
valid_sources[0x17]	7371	1			T3	3		T20	18		T17	40
valid_sources[0x18]	7719	1			T2	1		T3	3		T14	8
valid_sources[0x19]	7474	1			T1	11		T3	5		T20	31
valid_sources[0x1a]	7846	1			T1	1		T3	5		T20	12
valid_sources[0x1b]	8381	1			T2	2		T3	2		T14	3
valid_sources[0x1c]	7339	1			T1	5		T3	5		T20	30
valid_sources[0x1d]	7786	1			T3	5		T17	75		T18	84
valid_sources[0x1e]	7437	1			T1	9		T2	1		T3	4
valid_sources[0x1f]	8156	1			T1	19		T3	4		T14	2
valid_sources[0x20]	7568	1			T2	5		T3	3		T20	5
valid_sources[0x21]	8008	1			T1	14		T3	5		T20	13
valid_sources[0x22]	7508	1			T1	5		T3	5		T20	25
valid_sources[0x23]	7454	1			T3	3		T6	10		T20	9
valid_sources[0x24]	7662	1			T3	5		T20	8		T17	2
valid_sources[0x25]	7640	1			T3	4		T20	2		T17	4
valid_sources[0x26]	7781	1			T1	8		T2	1		T3	4
valid_sources[0x27]	7528	1			T3	5		T20	7		T17	16
valid_sources[0x28]	6890	1			T1	5		T2	1		T3	4
valid_sources[0x29]	7396	1			T1	2		T3	4		T20	13
valid_sources[0x2a]	8259	1			T3	4		T21	16		T14	2
valid_sources[0x2b]	8259	1			T1	14		T3	4		T20	10
valid_sources[0x2c]	7341	1			T2	1		T3	6		T20	32
valid_sources[0x2d]	7690	1			T2	4		T3	4		T20	11
valid_sources[0x2e]	9865	1			T3	4		T20	10		T17	37
valid_sources[0x2f]	7447	1			T2	1		T3	5		T14	2
valid_sources[0x30]	7129	1			T1	19		T2	1		T3	4
valid_sources[0x31]	7194	1			T3	4		T14	2		T20	21
valid_sources[0x32]	7319	1			T1	14		T2	2		T3	5
valid_sources[0x33]	7367	1			T1	19		T3	5		T20	8
valid_sources[0x34]	7483	1			T3	2		T20	30		T17	17
valid_sources[0x35]	7462	1			T1	19		T3	5		T20	6
valid_sources[0x36]	7926	1			T1	1		T2	1		T3	5
valid_sources[0x37]	7973	1			T2	1		T3	4		T14	2
valid_sources[0x38]	7677	1			T1	5		T3	5		T14	1
valid_sources[0x39]	7591	1			T1	19		T3	4		T20	10
valid_sources[0x3a]	8920	1			T1	7		T2	2		T3	5
valid_sources[0x3b]	8353	1			T2	3		T3	4		T21	7
valid_sources[0x3c]	7048	1			T3	5		T20	15		T17	52
valid_sources[0x3d]	8218	1			T1	6		T3	5		T20	32
valid_sources[0x3e]	7541	1			T3	5		T20	22		T17	20
valid_sources[0x3f]	8278	1			T3	4		T20	1		T17	3
valid_sources[0x40]	7968	1			T3	4		T20	28		T17	3
valid_sources[0x41]	7618	1			T3	3		T14	3		T20	14
valid_sources[0x42]	7992	1			T1	2		T3	4		T20	26
valid_sources[0x43]	7234	1			T1	10		T3	4		T20	14
valid_sources[0x44]	7578	1			T1	1		T2	1		T3	2
valid_sources[0x45]	7682	1			T1	9		T3	3		T20	24
valid_sources[0x46]	7864	1			T2	1		T3	5		T14	3
valid_sources[0x47]	7079	1			T1	6		T3	5		T20	4
valid_sources[0x48]	7590	1			T1	1		T3	5		T14	3
valid_sources[0x49]	8720	1			T1	1		T3	5		T14	4
valid_sources[0x4a]	7708	1			T2	1		T3	4		T20	13
valid_sources[0x4b]	8019	1			T1	3		T3	5		T20	21
valid_sources[0x4c]	7512	1			T3	4		T20	9		T17	16
valid_sources[0x4d]	7492	1			T2	1		T3	5		T20	9
valid_sources[0x4e]	7196	1			T3	5		T14	3		T20	12
valid_sources[0x4f]	7926	1			T1	13		T3	3		T20	13
valid_sources[0x50]	7531	1			T2	1		T3	5		T14	3
valid_sources[0x51]	9755	1			T3	4		T20	15		T17	9
valid_sources[0x52]	7867	1			T1	2		T2	1		T3	5
valid_sources[0x53]	8111	1			T1	9		T2	3		T3	4
valid_sources[0x54]	8298	1			T1	5		T2	2		T3	6
valid_sources[0x55]	7590	1			T2	1		T3	4		T5	2
valid_sources[0x56]	7017	1			T3	6		T20	7		T17	12
valid_sources[0x57]	7986	1			T1	1		T3	5		T18	65
valid_sources[0x58]	8416	1			T1	7		T3	5		T20	8
valid_sources[0x59]	7349	1			T3	4		T20	21		T17	23
valid_sources[0x5a]	7248	1			T3	5		T5	6		T20	18
valid_sources[0x5b]	9592	1			T2	3		T3	5		T20	22
valid_sources[0x5c]	8669	1			T1	5		T3	5		T14	4
valid_sources[0x5d]	8272	1			T1	3		T2	1		T3	5
valid_sources[0x5e]	8502	1			T3	5		T20	20		T17	1
valid_sources[0x5f]	8221	1			T1	14		T3	4		T14	1
valid_sources[0x60]	7668	1			T2	3		T3	4		T20	16
valid_sources[0x61]	7653	1			T1	5		T3	5		T20	7
valid_sources[0x62]	8782	1			T1	7		T3	4		T20	6
valid_sources[0x63]	8185	1			T1	3		T3	5		T20	11
valid_sources[0x64]	6977	1			T1	1		T2	2		T3	4
valid_sources[0x65]	7515	1			T1	1		T3	5		T21	3
valid_sources[0x66]	8189	1			T1	7		T3	5		T20	8
valid_sources[0x67]	7689	1			T2	2		T3	5		T20	25
valid_sources[0x68]	7580	1			T1	7		T3	5		T14	2
valid_sources[0x69]	7809	1			T3	4		T21	34		T20	8
valid_sources[0x6a]	7459	1			T2	1		T3	5		T20	11
valid_sources[0x6b]	7695	1			T1	3		T2	1		T3	5
valid_sources[0x6c]	7799	1			T2	4		T3	4		T21	17
valid_sources[0x6d]	7855	1			T1	3		T3	5		T14	1
valid_sources[0x6e]	8353	1			T2	4		T3	5		T5	29
valid_sources[0x6f]	7585	1			T3	4		T20	10		T17	7
valid_sources[0x70]	7639	1			T3	5		T14	4		T20	17
valid_sources[0x71]	7280	1			T1	6		T3	4		T14	2
valid_sources[0x72]	7830	1			T1	4		T3	4		T14	3
valid_sources[0x73]	7316	1			T1	3		T2	1		T3	4
valid_sources[0x74]	7013	1			T2	1		T3	5		T20	18
valid_sources[0x75]	7609	1			T3	5		T14	1		T20	6
valid_sources[0x76]	7913	1			T2	1		T3	4		T20	8
valid_sources[0x77]	7355	1			T1	4		T3	5		T20	7
valid_sources[0x78]	7360	1			T2	1		T3	4		T20	19
valid_sources[0x79]	7804	1			T1	4		T3	3		T14	6
valid_sources[0x7a]	8142	1			T1	3		T3	4		T20	23
valid_sources[0x7b]	7541	1			T3	5		T14	3		T20	27
valid_sources[0x7c]	8003	1			T1	2		T3	4		T14	1
valid_sources[0x7d]	7705	1			T2	1		T3	5		T20	13
valid_sources[0x7e]	7956	1			T1	13		T3	5		T20	22
valid_sources[0x7f]	7727	1			T3	5		T14	3		T20	2
valid_sources[0x80]	8222	1			T1	4		T2	3		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28523

1

T1

11

T2

4

T3

20

values[0x0]

all_enables

biggest_size

213604

1

T1

119

T2

21

T3

129

values[0x1]

all_enables

biggest_size

28738

1

T1

8

T2

2

T3

14