Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	316620998	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	316620998	0	0
T1	117768	3935	0	0
T2	47040	925	0	0
T3	6189232	831012	0	0
T4	41328	0	0	0
T5	4711224	84157	0	0
T6	8406776	203558	0	0
T14	11333392	211694	0	0
T15	0	3048	0	0
T17	7283920	313872	0	0
T18	0	82658	0	0
T19	0	2436	0	0
T20	3790416	77178	0	0
T21	7402472	237730	0	0
T22	0	1004	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	117768	112952	0	0
T2	47040	44184	0	0
T3	6189232	6189120	0	0
T4	41328	24752	0	0
T5	4711224	4709824	0	0
T6	8406776	8404704	0	0
T14	11333392	11330256	0	0
T17	7283920	7193144	0	0
T20	3790416	3787224	0	0
T21	7402472	7401072	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	117768	112952	0	0
T2	47040	44184	0	0
T3	6189232	6189120	0	0
T4	41328	24752	0	0
T5	4711224	4709824	0	0
T6	8406776	8404704	0	0
T14	11333392	11330256	0	0
T17	7283920	7193144	0	0
T20	3790416	3787224	0	0
T21	7402472	7401072	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	117768	112952	0	0
T2	47040	44184	0	0
T3	6189232	6189120	0	0
T4	41328	24752	0	0
T5	4711224	4709824	0	0
T6	8406776	8404704	0	0
T14	11333392	11330256	0	0
T17	7283920	7193144	0	0
T20	3790416	3787224	0	0
T21	7402472	7401072	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T14	56	56	0	0
T17	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	115551257	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	115551257	0	0
T1	2103	1532	0	0
T2	840	358	0	0
T3	110522	5183	0	0
T4	738	0	0	0
T5	84129	82760	0	0
T6	150121	84836	0	0
T14	202382	101353	0	0
T17	130070	124542	0	0
T18	0	28777	0	0
T20	67686	24485	0	0
T21	132187	130874	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	82368725	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	82368725	0	0
T1	2103	801	0	0
T2	840	189	0	0
T3	110522	410324	0	0
T4	738	0	0	0
T5	84129	309	0	0
T6	150121	38873	0	0
T14	202382	23184	0	0
T17	130070	69754	0	0
T18	0	18597	0	0
T20	67686	14105	0	0
T21	132187	53118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1358339	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1358339	0	0
T1	2103	33	0	0
T2	840	6	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	1771	0	0
T14	202382	4053	0	0
T15	0	255	0	0
T17	130070	1632	0	0
T18	0	525	0	0
T19	0	52	0	0
T20	67686	0	0	0
T21	132187	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2864972	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2864972	0	0
T1	2103	33	0	0
T2	840	6	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	3	0	0
T6	150121	866	0	0
T14	202382	1136	0	0
T15	0	255	0	0
T17	130070	1632	0	0
T18	0	525	0	0
T19	0	52	0	0
T20	67686	0	0	0
T21	132187	2597	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1373521	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1373521	0	0
T1	2103	26	0	0
T2	840	10	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	13	0	0
T6	150121	903	0	0
T14	202382	2169	0	0
T17	130070	1592	0	0
T18	0	1517	0	0
T19	0	47	0	0
T20	67686	0	0	0
T21	132187	4	0	0
T22	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3170281	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3170281	0	0
T1	2103	26	0	0
T2	840	10	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	4	0	0
T6	150121	720	0	0
T14	202382	1006	0	0
T17	130070	1592	0	0
T18	0	1517	0	0
T19	0	47	0	0
T20	67686	0	0	0
T21	132187	776	0	0
T22	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1325136	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1325136	0	0
T1	2103	31	0	0
T2	840	6	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	58	0	0
T6	150121	1659	0	0
T14	202382	1742	0	0
T17	130070	2733	0	0
T18	0	228	0	0
T19	0	44	0	0
T20	67686	0	0	0
T21	132187	20	0	0
T22	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2321525	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2321525	0	0
T1	2103	31	0	0
T2	840	6	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	162	0	0
T6	150121	1650	0	0
T14	202382	1158	0	0
T17	130070	2733	0	0
T18	0	228	0	0
T19	0	44	0	0
T20	67686	0	0	0
T21	132187	377	0	0
T22	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1330966	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1330966	0	0
T1	2103	32	0	0
T2	840	1	0	0
T3	110522	2135	0	0
T4	738	0	0	0
T5	84129	32	0	0
T6	150121	3434	0	0
T14	202382	2305	0	0
T17	130070	2288	0	0
T18	0	497	0	0
T20	67686	2822	0	0
T21	132187	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3164490	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3164490	0	0
T1	2103	32	0	0
T2	840	1	0	0
T3	110522	167721	0	0
T4	738	0	0	0
T5	84129	6	0	0
T6	150121	1693	0	0
T14	202382	7	0	0
T17	130070	2288	0	0
T18	0	497	0	0
T20	67686	2129	0	0
T21	132187	1999	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1405615	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1405615	0	0
T1	2103	28	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	43	0	0
T6	150121	352	0	0
T14	202382	2154	0	0
T15	0	212	0	0
T17	130070	1466	0	0
T18	0	529	0	0
T19	0	41	0	0
T20	67686	0	0	0
T21	132187	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3103125	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3103125	0	0
T1	2103	28	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	8	0	0
T6	150121	1501	0	0
T14	202382	257	0	0
T15	0	212	0	0
T17	130070	1466	0	0
T18	0	529	0	0
T19	0	41	0	0
T20	67686	0	0	0
T21	132187	925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1389015	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1389015	0	0
T1	2103	33	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	58	0	0
T6	150121	3500	0	0
T14	202382	2281	0	0
T15	0	296	0	0
T17	130070	2127	0	0
T18	0	243	0	0
T19	0	34	0	0
T20	67686	0	0	0
T21	132187	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2306748	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2306748	0	0
T1	2103	33	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	8	0	0
T6	150121	3890	0	0
T14	202382	948	0	0
T15	0	296	0	0
T17	130070	2127	0	0
T18	0	243	0	0
T19	0	34	0	0
T20	67686	0	0	0
T21	132187	618	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1365969	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1365969	0	0
T1	2103	22	0	0
T2	840	14	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	28	0	0
T6	150121	886	0	0
T14	202382	2804	0	0
T17	130070	3155	0	0
T18	0	525	0	0
T19	0	42	0	0
T20	67686	2596	0	0
T21	132187	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3507559	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3507559	0	0
T1	2103	22	0	0
T2	840	14	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	4	0	0
T6	150121	198	0	0
T14	202382	1109	0	0
T17	130070	3154	0	0
T18	0	525	0	0
T19	0	42	0	0
T20	67686	1826	0	0
T21	132187	439	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1365415	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1365415	0	0
T1	2103	35	0	0
T2	840	7	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	34	0	0
T6	150121	1445	0	0
T14	202382	3245	0	0
T17	130070	2254	0	0
T18	0	237	0	0
T19	0	51	0	0
T20	67686	0	0	0
T21	132187	41	0	0
T22	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2915550	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2915550	0	0
T1	2103	35	0	0
T2	840	7	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	1447	0	0
T14	202382	737	0	0
T17	130070	2254	0	0
T18	0	237	0	0
T19	0	51	0	0
T20	67686	0	0	0
T21	132187	3813	0	0
T22	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1381133	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1381133	0	0
T1	2103	20	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	28	0	0
T6	150121	1529	0	0
T14	202382	3335	0	0
T17	130070	1613	0	0
T18	0	986	0	0
T19	0	56	0	0
T20	67686	0	0	0
T21	132187	35	0	0
T22	0	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3361264	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3361264	0	0
T1	2103	20	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	10	0	0
T6	150121	2021	0	0
T14	202382	1001	0	0
T17	130070	1613	0	0
T18	0	986	0	0
T19	0	56	0	0
T20	67686	0	0	0
T21	132187	3333	0	0
T22	0	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1346407	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1346407	0	0
T1	2103	32	0	0
T2	840	1	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	44	0	0
T6	150121	1295	0	0
T14	202382	3482	0	0
T17	130070	2082	0	0
T18	0	298	0	0
T19	0	40	0	0
T20	67686	1864	0	0
T21	132187	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2481634	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2481634	0	0
T1	2103	32	0	0
T2	840	1	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	7	0	0
T6	150121	2944	0	0
T14	202382	1971	0	0
T17	130070	2081	0	0
T18	0	298	0	0
T19	0	40	0	0
T20	67686	823	0	0
T21	132187	3241	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1400940	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1400940	0	0
T1	2103	28	0	0
T2	840	2	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	17	0	0
T6	150121	210	0	0
T14	202382	728	0	0
T17	130070	1334	0	0
T18	0	1287	0	0
T19	0	52	0	0
T20	67686	0	0	0
T21	132187	39	0	0
T22	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2603222	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2603222	0	0
T1	2103	28	0	0
T2	840	2	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	3	0	0
T6	150121	190	0	0
T14	202382	532	0	0
T17	130070	1334	0	0
T18	0	1287	0	0
T19	0	52	0	0
T20	67686	0	0	0
T21	132187	3136	0	0
T22	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1425497	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1425497	0	0
T1	2103	25	0	0
T2	840	11	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	54	0	0
T14	202382	3883	0	0
T17	130070	2775	0	0
T18	0	774	0	0
T19	0	36	0	0
T20	67686	2469	0	0
T21	132187	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3167536	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3167536	0	0
T1	2103	25	0	0
T2	840	11	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	2	0	0
T6	150121	1345	0	0
T14	202382	817	0	0
T17	130070	2775	0	0
T18	0	774	0	0
T19	0	36	0	0
T20	67686	1925	0	0
T21	132187	1712	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1344489	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1344489	0	0
T1	2103	33	0	0
T2	840	7	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	23	0	0
T6	150121	2921	0	0
T14	202382	2420	0	0
T17	130070	1738	0	0
T18	0	243	0	0
T19	0	60	0	0
T20	67686	1662	0	0
T21	132187	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3244285	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3244285	0	0
T1	2103	33	0	0
T2	840	7	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	2599	0	0
T14	202382	1992	0	0
T17	130070	1738	0	0
T18	0	243	0	0
T19	0	60	0	0
T20	67686	1100	0	0
T21	132187	2593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1425768	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1425768	0	0
T1	2103	33	0	0
T2	840	8	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	10	0	0
T6	150121	1867	0	0
T14	202382	2444	0	0
T17	130070	2113	0	0
T18	0	801	0	0
T19	0	43	0	0
T20	67686	0	0	0
T21	132187	23	0	0
T22	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3313974	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3313974	0	0
T1	2103	33	0	0
T2	840	8	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	2	0	0
T6	150121	1953	0	0
T14	202382	877	0	0
T17	130070	2113	0	0
T18	0	801	0	0
T19	0	43	0	0
T20	67686	0	0	0
T21	132187	1484	0	0
T22	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1351243	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1351243	0	0
T1	2103	24	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	31	0	0
T6	150121	393	0	0
T14	202382	1022	0	0
T17	130070	1998	0	0
T18	0	1445	0	0
T19	0	44	0	0
T20	67686	3881	0	0
T21	132187	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2857581	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2857581	0	0
T1	2103	24	0	0
T2	840	4	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	119	0	0
T14	202382	311	0	0
T17	130070	1997	0	0
T18	0	1445	0	0
T19	0	44	0	0
T20	67686	1698	0	0
T21	132187	1186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1340438	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1340438	0	0
T1	2103	27	0	0
T2	840	11	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	48	0	0
T6	150121	3436	0	0
T14	202382	1541	0	0
T15	0	502	0	0
T17	130070	2507	0	0
T18	0	562	0	0
T19	0	69	0	0
T20	67686	0	0	0
T21	132187	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2841816	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2841816	0	0
T1	2103	27	0	0
T2	840	11	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	7	0	0
T6	150121	1606	0	0
T14	202382	586	0	0
T15	0	502	0	0
T17	130070	2506	0	0
T18	0	562	0	0
T19	0	69	0	0
T20	67686	0	0	0
T21	132187	3767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1356861	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1356861	0	0
T1	2103	34	0	0
T2	840	9	0	0
T3	110522	856	0	0
T4	738	0	0	0
T5	84129	14	0	0
T6	150121	612	0	0
T14	202382	1968	0	0
T17	130070	1488	0	0
T18	0	504	0	0
T19	0	50	0	0
T20	67686	0	0	0
T21	132187	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2613167	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2613167	0	0
T1	2103	34	0	0
T2	840	9	0	0
T3	110522	75477	0	0
T4	738	0	0	0
T5	84129	4	0	0
T6	150121	1513	0	0
T14	202382	841	0	0
T17	130070	1488	0	0
T18	0	504	0	0
T19	0	50	0	0
T20	67686	0	0	0
T21	132187	1410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1390300	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1390300	0	0
T1	2103	31	0	0
T2	840	9	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	56	0	0
T6	150121	2136	0	0
T14	202382	892	0	0
T17	130070	2636	0	0
T18	0	246	0	0
T19	0	40	0	0
T20	67686	0	0	0
T21	132187	29	0	0
T22	0	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2735452	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2735452	0	0
T1	2103	31	0	0
T2	840	9	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	12	0	0
T6	150121	1680	0	0
T14	202382	2	0	0
T17	130070	2636	0	0
T18	0	246	0	0
T19	0	40	0	0
T20	67686	0	0	0
T21	132187	1903	0	0
T22	0	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1359746	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1359746	0	0
T1	2103	36	0	0
T2	840	3	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	20	0	0
T6	150121	1322	0	0
T14	202382	920	0	0
T17	130070	2306	0	0
T18	0	783	0	0
T19	0	45	0	0
T20	67686	1806	0	0
T21	132187	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3314630	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3314630	0	0
T1	2103	36	0	0
T2	840	3	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	1964	0	0
T14	202382	206	0	0
T17	130070	2306	0	0
T18	0	783	0	0
T19	0	45	0	0
T20	67686	827	0	0
T21	132187	621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1401473	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1401473	0	0
T1	2103	36	0	0
T2	840	12	0	0
T3	110522	1278	0	0
T4	738	0	0	0
T5	84129	60	0	0
T6	150121	309	0	0
T14	202382	1591	0	0
T17	130070	3475	0	0
T18	0	268	0	0
T19	0	46	0	0
T20	67686	0	0	0
T21	132187	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3497583	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3497583	0	0
T1	2103	36	0	0
T2	840	12	0	0
T3	110522	96336	0	0
T4	738	0	0	0
T5	84129	10	0	0
T6	150121	186	0	0
T14	202382	797	0	0
T17	130070	3475	0	0
T18	0	268	0	0
T19	0	46	0	0
T20	67686	0	0	0
T21	132187	503	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1375665	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1375665	0	0
T1	2103	37	0	0
T2	840	5	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	24	0	0
T6	150121	2663	0	0
T14	202382	2692	0	0
T15	0	259	0	0
T17	130070	2700	0	0
T18	0	282	0	0
T19	0	55	0	0
T20	67686	0	0	0
T21	132187	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2998601	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2998601	0	0
T1	2103	37	0	0
T2	840	5	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	7	0	0
T6	150121	1283	0	0
T14	202382	783	0	0
T15	0	259	0	0
T17	130070	2700	0	0
T18	0	282	0	0
T19	0	55	0	0
T20	67686	0	0	0
T21	132187	3911	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1420594	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1420594	0	0
T1	2103	32	0	0
T2	840	11	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	29	0	0
T6	150121	844	0	0
T14	202382	3676	0	0
T17	130070	2619	0	0
T18	0	766	0	0
T19	0	40	0	0
T20	67686	2200	0	0
T21	132187	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3023118	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3023118	0	0
T1	2103	32	0	0
T2	840	11	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	7	0	0
T6	150121	2300	0	0
T14	202382	1050	0	0
T17	130070	2619	0	0
T18	0	766	0	0
T19	0	40	0	0
T20	67686	952	0	0
T21	132187	4411	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1410005	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1410005	0	0
T1	2103	28	0	0
T2	840	6	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	33	0	0
T6	150121	1534	0	0
T14	202382	2727	0	0
T17	130070	2189	0	0
T18	0	825	0	0
T19	0	49	0	0
T20	67686	1455	0	0
T21	132187	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3796695	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3796695	0	0
T1	2103	28	0	0
T2	840	6	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	9	0	0
T6	150121	1161	0	0
T14	202382	1141	0	0
T17	130070	2189	0	0
T18	0	825	0	0
T19	0	49	0	0
T20	67686	964	0	0
T21	132187	3261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1418568	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1418568	0	0
T1	2103	28	0	0
T2	840	7	0	0
T3	110522	913	0	0
T4	738	0	0	0
T5	84129	7	0	0
T6	150121	2584	0	0
T14	202382	2100	0	0
T17	130070	1550	0	0
T18	0	1002	0	0
T19	0	44	0	0
T20	67686	1343	0	0
T21	132187	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3855166	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3855166	0	0
T1	2103	28	0	0
T2	840	7	0	0
T3	110522	70789	0	0
T4	738	0	0	0
T5	84129	2	0	0
T6	150121	1189	0	0
T14	202382	984	0	0
T17	130070	1550	0	0
T18	0	1002	0	0
T19	0	44	0	0
T20	67686	948	0	0
T21	132187	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1341438	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1341438	0	0
T1	2103	18	0	0
T2	840	12	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	16	0	0
T6	150121	1752	0	0
T14	202382	2035	0	0
T17	130070	2934	0	0
T18	0	933	0	0
T19	0	52	0	0
T20	67686	2386	0	0
T21	132187	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2766582	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2766582	0	0
T1	2103	18	0	0
T2	840	12	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	3	0	0
T6	150121	769	0	0
T14	202382	731	0	0
T17	130070	2934	0	0
T18	0	933	0	0
T19	0	52	0	0
T20	67686	912	0	0
T21	132187	1172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1335605	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1335605	0	0
T1	2103	37	0	0
T2	840	5	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	26	0	0
T6	150121	834	0	0
T14	202382	2972	0	0
T17	130070	1714	0	0
T18	0	806	0	0
T19	0	48	0	0
T20	67686	0	0	0
T21	132187	25	0	0
T22	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	2598115	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	2598115	0	0
T1	2103	37	0	0
T2	840	5	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	5	0	0
T6	150121	1242	0	0
T14	202382	120	0	0
T17	130070	1714	0	0
T18	0	806	0	0
T19	0	48	0	0
T20	67686	0	0	0
T21	132187	1553	0	0
T22	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	1405242	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	1405242	0	0
T1	2103	22	0	0
T2	840	10	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	17	0	0
T6	150121	731	0	0
T14	202382	2792	0	0
T17	130070	2772	0	0
T18	0	530	0	0
T19	0	38	0	0
T20	67686	0	0	0
T21	132187	31	0	0
T22	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294305217	3130957	0	0
DepthKnown_A	294305217	294176015	0	0
RvalidKnown_A	294305217	294176015	0	0
WreadyKnown_A	294305217	294176015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	3130957	0	0
T1	2103	22	0	0
T2	840	10	0	0
T3	110522	0	0	0
T4	738	0	0	0
T5	84129	4	0	0
T6	150121	844	0	0
T14	202382	2084	0	0
T17	130070	2772	0	0
T18	0	530	0	0
T19	0	38	0	0
T20	67686	0	0	0
T21	132187	2377	0	0
T22	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294305217	294176015	0	0
T1	2103	2017	0	0
T2	840	789	0	0
T3	110522	110520	0	0
T4	738	442	0	0
T5	84129	84104	0	0
T6	150121	150084	0	0
T14	202382	202326	0	0
T17	130070	128449	0	0
T20	67686	67629	0	0
T21	132187	132162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0