Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1674708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263988

1

T1

11

T2

24

T3

175

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	655895	1			T1	27		T2	50		T3	454
values[0x0]	627618	1			T1	36		T2	50		T3	407
values[0x1]	655183	1			T1	37		T2	56		T3	389

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1297982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640714

1

T1

26

T2

55

T3

416

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8007	1			T1	1		T15	19		T5	2
valid_sources[0x01]	7573	1			T2	2		T3	1		T15	21
valid_sources[0x02]	7628	1			T1	3		T3	5		T4	7
valid_sources[0x03]	6972	1			T15	31		T5	10		T19	12
valid_sources[0x04]	7201	1			T15	19		T19	15		T21	5
valid_sources[0x05]	6862	1			T15	16		T5	8		T17	1
valid_sources[0x06]	6998	1			T15	21		T5	76		T19	4
valid_sources[0x07]	7406	1			T1	1		T15	14		T5	10
valid_sources[0x08]	6666	1			T3	4		T15	20		T5	5
valid_sources[0x09]	8421	1			T3	76		T15	19		T5	21
valid_sources[0x0a]	7467	1			T2	3		T3	53		T15	24
valid_sources[0x0b]	6780	1			T1	1		T15	17		T5	5
valid_sources[0x0c]	6446	1			T3	7		T15	27		T19	13
valid_sources[0x0d]	7003	1			T15	19		T19	10		T21	11
valid_sources[0x0e]	7261	1			T1	3		T15	15		T19	8
valid_sources[0x0f]	7255	1			T4	33		T15	15		T19	17
valid_sources[0x10]	8125	1			T15	26		T19	4		T21	11
valid_sources[0x11]	7059	1			T1	2		T3	8		T15	20
valid_sources[0x12]	6933	1			T3	1		T15	21		T19	9
valid_sources[0x13]	7265	1			T1	1		T2	7		T15	22
valid_sources[0x14]	7487	1			T1	1		T2	4		T15	15
valid_sources[0x15]	7263	1			T2	7		T3	16		T15	9
valid_sources[0x16]	7402	1			T3	5		T15	16		T5	7
valid_sources[0x17]	7764	1			T1	2		T15	14		T5	26
valid_sources[0x18]	6670	1			T15	22		T5	1		T19	7
valid_sources[0x19]	7071	1			T15	25		T5	30		T19	10
valid_sources[0x1a]	8446	1			T1	2		T3	11		T15	19
valid_sources[0x1b]	7245	1			T2	7		T15	21		T5	23
valid_sources[0x1c]	9208	1			T3	16		T15	14		T5	14
valid_sources[0x1d]	7451	1			T2	2		T15	13		T5	12
valid_sources[0x1e]	7893	1			T15	23		T5	8		T19	5
valid_sources[0x1f]	7208	1			T3	2		T15	19		T5	1
valid_sources[0x20]	6781	1			T15	27		T5	25		T19	14
valid_sources[0x21]	7421	1			T15	20		T5	23		T19	7
valid_sources[0x22]	7196	1			T15	10		T5	14		T19	6
valid_sources[0x23]	7601	1			T2	2		T15	21		T5	1
valid_sources[0x24]	6897	1			T15	16		T5	10		T19	7
valid_sources[0x25]	7536	1			T1	3		T15	21		T5	26
valid_sources[0x26]	7109	1			T3	2		T15	23		T19	14
valid_sources[0x27]	6924	1			T15	23		T5	11		T17	1
valid_sources[0x28]	7932	1			T15	21		T5	22		T19	10
valid_sources[0x29]	7616	1			T15	17		T5	25		T19	7
valid_sources[0x2a]	7580	1			T15	14		T19	11		T21	6
valid_sources[0x2b]	7542	1			T15	8		T5	16		T19	5
valid_sources[0x2c]	7673	1			T15	20		T5	2		T17	1
valid_sources[0x2d]	8322	1			T1	1		T15	16		T5	8
valid_sources[0x2e]	8862	1			T15	16		T5	29		T19	10
valid_sources[0x2f]	7731	1			T15	12		T5	8		T19	4
valid_sources[0x30]	7349	1			T15	17		T5	18		T19	13
valid_sources[0x31]	7106	1			T15	25		T5	21		T19	7
valid_sources[0x32]	8336	1			T15	23		T5	6		T19	13
valid_sources[0x33]	7586	1			T15	22		T19	5		T20	1
valid_sources[0x34]	7914	1			T15	28		T5	12		T19	10
valid_sources[0x35]	7118	1			T1	3		T15	19		T17	1
valid_sources[0x36]	6875	1			T15	22		T5	17		T19	8
valid_sources[0x37]	7146	1			T1	1		T15	21		T17	2
valid_sources[0x38]	8398	1			T15	16		T19	10		T21	10
valid_sources[0x39]	7877	1			T15	17		T19	4		T20	2
valid_sources[0x3a]	7872	1			T4	9		T15	18		T19	10
valid_sources[0x3b]	7392	1			T15	16		T5	4		T19	12
valid_sources[0x3c]	7357	1			T15	25		T19	10		T21	5
valid_sources[0x3d]	7762	1			T2	2		T3	3		T15	21
valid_sources[0x3e]	7441	1			T3	4		T15	14		T5	1
valid_sources[0x3f]	7214	1			T15	18		T5	8		T19	8
valid_sources[0x40]	7527	1			T3	83		T15	21		T19	13
valid_sources[0x41]	8019	1			T15	20		T5	5		T19	8
valid_sources[0x42]	7699	1			T15	19		T5	25		T17	1
valid_sources[0x43]	7079	1			T15	13		T5	15		T19	2
valid_sources[0x44]	7343	1			T1	2		T3	33		T15	15
valid_sources[0x45]	7557	1			T15	23		T19	12		T21	15
valid_sources[0x46]	7981	1			T15	22		T5	7		T19	11
valid_sources[0x47]	7350	1			T2	2		T3	9		T4	6
valid_sources[0x48]	8319	1			T15	18		T5	1		T19	16
valid_sources[0x49]	7433	1			T3	3		T15	10		T19	1
valid_sources[0x4a]	7764	1			T15	15		T19	7		T21	8
valid_sources[0x4b]	7437	1			T3	32		T15	20		T5	48
valid_sources[0x4c]	6556	1			T1	1		T3	1		T15	14
valid_sources[0x4d]	8239	1			T15	22		T19	12		T21	10
valid_sources[0x4e]	7156	1			T15	11		T19	6		T21	11
valid_sources[0x4f]	7518	1			T15	21		T5	7		T19	23
valid_sources[0x50]	6892	1			T2	1		T4	26		T15	27
valid_sources[0x51]	6871	1			T15	16		T5	5		T19	3
valid_sources[0x52]	7367	1			T1	3		T2	10		T15	22
valid_sources[0x53]	7035	1			T3	14		T15	12		T5	4
valid_sources[0x54]	6990	1			T1	2		T2	5		T15	18
valid_sources[0x55]	7307	1			T15	11		T5	6		T19	4
valid_sources[0x56]	7231	1			T2	2		T15	17		T5	15
valid_sources[0x57]	7990	1			T15	20		T17	1		T19	7
valid_sources[0x58]	6880	1			T15	15		T5	27		T19	6
valid_sources[0x59]	7722	1			T3	2		T15	19		T5	30
valid_sources[0x5a]	7571	1			T15	10		T5	5		T19	10
valid_sources[0x5b]	7110	1			T2	6		T3	15		T15	11
valid_sources[0x5c]	6826	1			T15	15		T5	3		T19	11
valid_sources[0x5d]	8038	1			T1	1		T15	18		T5	5
valid_sources[0x5e]	6939	1			T1	2		T3	65		T15	14
valid_sources[0x5f]	7179	1			T15	17		T5	15		T19	10
valid_sources[0x60]	7666	1			T2	4		T15	12		T5	4
valid_sources[0x61]	7968	1			T3	3		T15	23		T19	7
valid_sources[0x62]	7480	1			T15	17		T19	9		T21	3
valid_sources[0x63]	7301	1			T2	3		T15	17		T5	56
valid_sources[0x64]	7676	1			T15	20		T5	34		T19	6
valid_sources[0x65]	7104	1			T3	21		T15	12		T5	76
valid_sources[0x66]	7246	1			T15	21		T5	28		T19	8
valid_sources[0x67]	7669	1			T1	4		T15	14		T5	50
valid_sources[0x68]	8643	1			T1	1		T3	9		T15	13
valid_sources[0x69]	7629	1			T15	19		T5	1		T19	6
valid_sources[0x6a]	8695	1			T4	12		T15	21		T19	2
valid_sources[0x6b]	7189	1			T15	24		T19	7		T21	8
valid_sources[0x6c]	7336	1			T15	17		T5	17		T19	8
valid_sources[0x6d]	7859	1			T15	13		T5	4		T19	13
valid_sources[0x6e]	7398	1			T4	5		T15	20		T5	2
valid_sources[0x6f]	7453	1			T1	1		T15	12		T5	10
valid_sources[0x70]	7486	1			T15	15		T5	4		T19	9
valid_sources[0x71]	7341	1			T3	2		T15	15		T17	3
valid_sources[0x72]	7441	1			T15	18		T5	20		T19	3
valid_sources[0x73]	7519	1			T15	25		T5	23		T19	13
valid_sources[0x74]	8852	1			T15	14		T5	1		T17	3
valid_sources[0x75]	8046	1			T15	12		T5	6		T19	5
valid_sources[0x76]	8222	1			T15	18		T5	28		T19	11
valid_sources[0x77]	6865	1			T15	17		T5	9		T19	13
valid_sources[0x78]	8184	1			T15	20		T19	7		T21	9
valid_sources[0x79]	6998	1			T2	3		T4	2		T15	18
valid_sources[0x7a]	6987	1			T15	15		T5	1		T19	9
valid_sources[0x7b]	7063	1			T3	8		T15	18		T5	12
valid_sources[0x7c]	6674	1			T15	22		T19	12		T21	9
valid_sources[0x7d]	7215	1			T1	2		T15	20		T5	14
valid_sources[0x7e]	7502	1			T15	17		T19	5		T21	5
valid_sources[0x7f]	7457	1			T1	2		T15	23		T19	10
valid_sources[0x80]	7387	1			T15	16		T5	1		T19	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27984

1

T1

1

T2

1

T3

14

values[0x0]

all_enables

biggest_size

208396

1

T1

10

T2

22

T3

146

values[0x1]

all_enables

biggest_size

27608

1

T2

1

T3

15

T4

3