Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	329809909	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329809909	0	0
T1	7386665	174323	0	0
T2	8850240	158508	0	0
T3	7183064	1341172	0	0
T4	181216	3566	0	0
T5	8104488	177477	0	0
T15	5081272	107567	0	0
T16	46256	701	0	0
T17	698152	12954	0	0
T19	2698136	56538	0	0
T20	168000	2692	0	0
T21	55667	14585	0	0
T22	0	511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7520968	7517944	0	0
T2	8850240	8849680	0	0
T3	7183064	7182952	0	0
T4	181216	178920	0	0
T5	8104488	8104152	0	0
T15	5081272	5079088	0	0
T16	46256	41328	0	0
T17	698152	697200	0	0
T19	2698136	2697520	0	0
T20	168000	164808	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7520968	7517944	0	0
T2	8850240	8849680	0	0
T3	7183064	7182952	0	0
T4	181216	178920	0	0
T5	8104488	8104152	0	0
T15	5081272	5079088	0	0
T16	46256	41328	0	0
T17	698152	697200	0	0
T19	2698136	2697520	0	0
T20	168000	164808	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7520968	7517944	0	0
T2	8850240	8849680	0	0
T3	7183064	7182952	0	0
T4	181216	178920	0	0
T5	8104488	8104152	0	0
T15	5081272	5079088	0	0
T16	46256	41328	0	0
T17	698152	697200	0	0
T19	2698136	2697520	0	0
T20	168000	164808	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	119417699	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	119417699	0	0
T1	134303	72853	0	0
T2	158040	77476	0	0
T3	128269	609963	0	0
T4	3236	1470	0	0
T5	144723	141315	0	0
T15	90737	35524	0	0
T16	826	272	0	0
T17	12467	5261	0	0
T19	48181	25493	0	0
T20	3000	1248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	87592354	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	87592354	0	0
T1	134303	31971	0	0
T2	158040	15541	0	0
T3	128269	155673	0	0
T4	3236	1126	0	0
T5	144723	11686	0	0
T15	90737	18261	0	0
T16	826	143	0	0
T17	12467	3439	0	0
T19	48181	7163	0	0
T20	3000	312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1345628	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1345628	0	0
T1	134303	685	0	0
T2	158040	1949	0	0
T3	128269	12323	0	0
T4	3236	10	0	0
T5	144723	497	0	0
T15	90737	0	0	0
T16	826	3	0	0
T17	12467	144	0	0
T19	48181	718	0	0
T20	3000	14	0	0
T21	0	699	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2850911	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2850911	0	0
T1	134303	182	0	0
T2	158040	947	0	0
T3	128269	5789	0	0
T4	3236	5	0	0
T5	144723	121	0	0
T15	90737	0	0	0
T16	826	3	0	0
T17	12467	120	0	0
T19	48181	308	0	0
T20	3000	2	0	0
T21	0	337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1345589	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1345589	0	0
T1	134303	376	0	0
T2	158040	2586	0	0
T3	128269	12030	0	0
T4	3236	10	0	0
T5	144723	403	0	0
T15	90737	1205	0	0
T16	826	8	0	0
T17	12467	103	0	0
T19	48181	493	0	0
T20	3000	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3450141	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3450141	0	0
T1	134303	177	0	0
T2	158040	1100	0	0
T3	128269	6011	0	0
T4	3236	6	0	0
T5	144723	98	0	0
T15	90737	1105	0	0
T16	826	8	0	0
T17	12467	80	0	0
T19	48181	244	0	0
T20	3000	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1355064	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1355064	0	0
T1	134303	1458	0	0
T2	158040	1256	0	0
T3	128269	19688	0	0
T4	3236	30	0	0
T5	144723	465	0	0
T15	90737	1391	0	0
T16	826	6	0	0
T17	12467	94	0	0
T19	48181	455	0	0
T20	3000	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3268881	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3268881	0	0
T1	134303	522	0	0
T2	158040	724	0	0
T3	128269	8665	0	0
T4	3236	38	0	0
T5	144723	810	0	0
T15	90737	1076	0	0
T16	826	6	0	0
T17	12467	52	0	0
T19	48181	206	0	0
T20	3000	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1343530	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1343530	0	0
T1	134303	1459	0	0
T2	158040	823	0	0
T3	128269	15739	0	0
T4	3236	26	0	0
T5	144723	534	0	0
T15	90737	3537	0	0
T16	826	2	0	0
T17	12467	80	0	0
T19	48181	596	0	0
T20	3000	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3111820	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3111820	0	0
T1	134303	1729	0	0
T2	158040	873	0	0
T3	128269	6247	0	0
T4	3236	21	0	0
T5	144723	588	0	0
T15	90737	1444	0	0
T16	826	2	0	0
T17	12467	54	0	0
T19	48181	299	0	0
T20	3000	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1388265	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1388265	0	0
T1	134303	1047	0	0
T2	158040	863	0	0
T3	128269	16373	0	0
T4	3236	42	0	0
T5	144723	398	0	0
T15	90737	3672	0	0
T16	826	4	0	0
T17	12467	85	0	0
T19	48181	678	0	0
T20	3000	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2880887	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2880887	0	0
T1	134303	344	0	0
T2	158040	888	0	0
T3	128269	8229	0	0
T4	3236	31	0	0
T5	144723	89	0	0
T15	90737	1605	0	0
T16	826	4	0	0
T17	12467	87	0	0
T19	48181	235	0	0
T20	3000	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1363862	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1363862	0	0
T1	134303	669	0	0
T2	158040	1227	0	0
T3	128269	20150	0	0
T4	3236	17	0	0
T5	144723	523	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	88	0	0
T19	48181	613	0	0
T20	3000	44	0	0
T21	0	734	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2933533	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2933533	0	0
T1	134303	766	0	0
T2	158040	100	0	0
T3	128269	4649	0	0
T4	3236	36	0	0
T5	144723	1323	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	67	0	0
T19	48181	225	0	0
T20	3000	21	0	0
T21	0	276	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1341981	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1341981	0	0
T1	134303	1713	0	0
T2	158040	121	0	0
T3	128269	11762	0	0
T4	3236	0	0	0
T5	144723	492	0	0
T15	90737	0	0	0
T16	826	4	0	0
T17	12467	111	0	0
T19	48181	568	0	0
T20	3000	19	0	0
T21	0	878	0	0
T22	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3164060	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3164060	0	0
T1	134303	1007	0	0
T2	158040	245	0	0
T3	128269	4579	0	0
T4	3236	0	0	0
T5	144723	925	0	0
T15	90737	0	0	0
T16	826	4	0	0
T17	12467	64	0	0
T19	48181	255	0	0
T20	3000	15	0	0
T21	0	323	0	0
T22	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1330154	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1330154	0	0
T1	134303	1036	0	0
T2	158040	1516	0	0
T3	128269	16487	0	0
T4	3236	10	0	0
T5	144723	554	0	0
T15	90737	1790	0	0
T16	826	4	0	0
T17	12467	102	0	0
T19	48181	739	0	0
T20	3000	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3661872	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3661872	0	0
T1	134303	802	0	0
T2	158040	168	0	0
T3	128269	3948	0	0
T4	3236	0	0	0
T5	144723	384	0	0
T15	90737	843	0	0
T16	826	4	0	0
T17	12467	83	0	0
T19	48181	280	0	0
T20	3000	1	0	0
T21	0	310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1276118	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1276118	0	0
T1	134303	899	0	0
T2	158040	1671	0	0
T3	128269	17634	0	0
T4	3236	36	0	0
T5	144723	389	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	72	0	0
T19	48181	675	0	0
T20	3000	3	0	0
T21	0	614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3129898	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3129898	0	0
T1	134303	592	0	0
T2	158040	441	0	0
T3	128269	6011	0	0
T4	3236	11	0	0
T5	144723	774	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	66	0	0
T19	48181	320	0	0
T20	3000	1	0	0
T21	0	193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1330212	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1330212	0	0
T1	134303	643	0	0
T2	158040	1767	0	0
T3	128269	13707	0	0
T4	3236	36	0	0
T5	144723	438	0	0
T15	90737	2155	0	0
T16	826	8	0	0
T17	12467	88	0	0
T19	48181	478	0	0
T20	3000	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3344311	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3344311	0	0
T1	134303	1382	0	0
T2	158040	279	0	0
T3	128269	4283	0	0
T4	3236	43	0	0
T5	144723	112	0	0
T15	90737	946	0	0
T16	826	8	0	0
T17	12467	32	0	0
T19	48181	259	0	0
T20	3000	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1396877	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1396877	0	0
T1	134303	2397	0	0
T2	158040	3028	0	0
T3	128269	16810	0	0
T4	3236	24	0	0
T5	144723	385	0	0
T15	90737	2459	0	0
T16	826	3	0	0
T17	12467	137	0	0
T19	48181	586	0	0
T20	3000	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2615020	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2615020	0	0
T1	134303	1614	0	0
T2	158040	768	0	0
T3	128269	6952	0	0
T4	3236	33	0	0
T5	144723	738	0	0
T15	90737	1121	0	0
T16	826	3	0	0
T17	12467	121	0	0
T19	48181	289	0	0
T20	3000	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1352151	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1352151	0	0
T1	134303	2716	0	0
T2	158040	1382	0	0
T3	128269	15558	0	0
T4	3236	35	0	0
T5	144723	442	0	0
T15	90737	0	0	0
T16	826	4	0	0
T17	12467	67	0	0
T19	48181	741	0	0
T20	3000	37	0	0
T21	0	898	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3617239	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3617239	0	0
T1	134303	2512	0	0
T2	158040	470	0	0
T3	128269	7219	0	0
T4	3236	69	0	0
T5	144723	1043	0	0
T15	90737	0	0	0
T16	826	4	0	0
T17	12467	42	0	0
T19	48181	277	0	0
T20	3000	6	0	0
T21	0	323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1352399	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1352399	0	0
T1	134303	733	0	0
T2	158040	459	0	0
T3	128269	11537	0	0
T4	3236	23	0	0
T5	144723	535	0	0
T15	90737	1345	0	0
T16	826	4	0	0
T17	12467	55	0	0
T19	48181	698	0	0
T20	3000	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3510295	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3510295	0	0
T1	134303	467	0	0
T2	158040	1	0	0
T3	128269	6284	0	0
T4	3236	17	0	0
T5	144723	121	0	0
T15	90737	945	0	0
T16	826	4	0	0
T17	12467	34	0	0
T19	48181	285	0	0
T20	3000	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1367118	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1367118	0	0
T1	134303	2889	0	0
T2	158040	1967	0	0
T3	128269	17757	0	0
T4	3236	23	0	0
T5	144723	422	0	0
T15	90737	4368	0	0
T16	826	4	0	0
T17	12467	53	0	0
T19	48181	577	0	0
T20	3000	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2794217	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2794217	0	0
T1	134303	1717	0	0
T2	158040	574	0	0
T3	128269	5364	0	0
T4	3236	6	0	0
T5	144723	107	0	0
T15	90737	2013	0	0
T16	826	4	0	0
T17	12467	53	0	0
T19	48181	285	0	0
T20	3000	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1363147	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1363147	0	0
T1	134303	666	0	0
T2	158040	1327	0	0
T3	128269	19311	0	0
T4	3236	20	0	0
T5	144723	501	0	0
T15	90737	1663	0	0
T16	826	1	0	0
T17	12467	132	0	0
T19	48181	465	0	0
T20	3000	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3129308	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3129308	0	0
T1	134303	664	0	0
T2	158040	376	0	0
T3	128269	6837	0	0
T4	3236	27	0	0
T5	144723	111	0	0
T15	90737	1240	0	0
T16	826	1	0	0
T17	12467	68	0	0
T19	48181	224	0	0
T20	3000	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1327441	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1327441	0	0
T1	134303	672	0	0
T2	158040	1484	0	0
T3	128269	14029	0	0
T4	3236	5	0	0
T5	144723	463	0	0
T15	90737	0	0	0
T16	826	10	0	0
T17	12467	135	0	0
T19	48181	706	0	0
T20	3000	35	0	0
T21	0	715	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3982469	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3982469	0	0
T1	134303	1719	0	0
T2	158040	426	0	0
T3	128269	3289	0	0
T4	3236	5	0	0
T5	144723	108	0	0
T15	90737	0	0	0
T16	826	10	0	0
T17	12467	113	0	0
T19	48181	297	0	0
T20	3000	5	0	0
T21	0	253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1342724	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1342724	0	0
T1	134303	1294	0	0
T2	158040	1324	0	0
T3	128269	10608	0	0
T4	3236	10	0	0
T5	144723	460	0	0
T15	90737	2445	0	0
T16	826	6	0	0
T17	12467	57	0	0
T19	48181	551	0	0
T20	3000	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3277502	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3277502	0	0
T1	134303	1082	0	0
T2	158040	688	0	0
T3	128269	3851	0	0
T4	3236	17	0	0
T5	144723	324	0	0
T15	90737	1113	0	0
T16	826	6	0	0
T17	12467	29	0	0
T19	48181	249	0	0
T20	3000	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1326547	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1326547	0	0
T1	134303	3015	0	0
T2	158040	3542	0	0
T3	128269	20339	0	0
T4	3236	0	0	0
T5	144723	513	0	0
T15	90737	2109	0	0
T16	826	3	0	0
T17	12467	61	0	0
T19	48181	593	0	0
T20	3000	47	0	0
T21	0	706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3327792	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3327792	0	0
T1	134303	2902	0	0
T2	158040	734	0	0
T3	128269	5422	0	0
T4	3236	0	0	0
T5	144723	527	0	0
T15	90737	1007	0	0
T16	826	3	0	0
T17	12467	47	0	0
T19	48181	264	0	0
T20	3000	21	0	0
T21	0	260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1339494	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1339494	0	0
T1	134303	2396	0	0
T2	158040	1281	0	0
T3	128269	14862	0	0
T4	3236	9	0	0
T5	144723	412	0	0
T15	90737	1962	0	0
T16	826	8	0	0
T17	12467	79	0	0
T19	48181	636	0	0
T20	3000	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3409195	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3409195	0	0
T1	134303	1398	0	0
T2	158040	516	0	0
T3	128269	4911	0	0
T4	3236	16	0	0
T5	144723	477	0	0
T15	90737	807	0	0
T16	826	8	0	0
T17	12467	61	0	0
T19	48181	270	0	0
T20	3000	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1307144	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1307144	0	0
T1	134303	2146	0	0
T2	158040	2301	0	0
T3	128269	18882	0	0
T4	3236	20	0	0
T5	144723	382	0	0
T15	90737	1601	0	0
T16	826	7	0	0
T17	12467	68	0	0
T19	48181	549	0	0
T20	3000	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3132546	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3132546	0	0
T1	134303	2181	0	0
T2	158040	829	0	0
T3	128269	7207	0	0
T4	3236	5	0	0
T5	144723	95	0	0
T15	90737	690	0	0
T16	826	7	0	0
T17	12467	96	0	0
T19	48181	242	0	0
T20	3000	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1343775	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1343775	0	0
T1	134303	158	0	0
T2	158040	2115	0	0
T3	128269	15582	0	0
T4	3236	0	0	0
T5	144723	510	0	0
T15	90737	1372	0	0
T16	826	9	0	0
T17	12467	94	0	0
T19	48181	586	0	0
T20	3000	61	0	0
T21	0	821	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3442516	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3442516	0	0
T1	134303	395	0	0
T2	158040	1495	0	0
T3	128269	6961	0	0
T4	3236	0	0	0
T5	144723	108	0	0
T15	90737	1115	0	0
T16	826	9	0	0
T17	12467	71	0	0
T19	48181	300	0	0
T20	3000	34	0	0
T21	0	411	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1318197	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1318197	0	0
T1	134303	19	0	0
T2	158040	2297	0	0
T3	128269	12862	0	0
T4	3236	14	0	0
T5	144723	441	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	116	0	0
T19	48181	769	0	0
T20	3000	36	0	0
T21	0	629	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3635624	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3635624	0	0
T2	158040	269	0	0
T3	128269	6205	0	0
T4	3236	6	0	0
T5	144723	106	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	105	0	0
T19	48181	302	0	0
T20	3000	6	0	0
T21	55667	271	0	0
T22	0	405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1338304	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1338304	0	0
T1	134303	1289	0	0
T2	158040	2008	0	0
T3	128269	14111	0	0
T4	3236	0	0	0
T5	144723	491	0	0
T15	90737	2448	0	0
T16	826	5	0	0
T17	12467	84	0	0
T19	48181	655	0	0
T20	3000	3	0	0
T21	0	620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3159910	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3159910	0	0
T1	134303	1070	0	0
T2	158040	328	0	0
T3	128269	3702	0	0
T4	3236	0	0	0
T5	144723	913	0	0
T15	90737	1190	0	0
T16	826	5	0	0
T17	12467	70	0	0
T19	48181	213	0	0
T20	3000	1	0	0
T21	0	292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1319864	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1319864	0	0
T1	134303	968	0	0
T2	158040	3182	0	0
T3	128269	16810	0	0
T4	3236	25	0	0
T5	144723	473	0	0
T15	90737	0	0	0
T16	826	4	0	0
T17	12467	86	0	0
T19	48181	652	0	0
T20	3000	32	0	0
T21	0	683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3106810	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3106810	0	0
T1	134303	1394	0	0
T2	158040	780	0	0
T3	128269	5354	0	0
T4	3236	30	0	0
T5	144723	112	0	0
T15	90737	0	0	0
T16	826	4	0	0
T17	12467	58	0	0
T19	48181	241	0	0
T20	3000	18	0	0
T21	0	291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1351227	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1351227	0	0
T1	134303	2884	0	0
T2	158040	4123	0	0
T3	128269	11453	0	0
T4	3236	23	0	0
T5	144723	493	0	0
T15	90737	0	0	0
T16	826	6	0	0
T17	12467	94	0	0
T19	48181	672	0	0
T20	3000	8	0	0
T21	0	778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	3094738	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	3094738	0	0
T1	134303	1456	0	0
T2	158040	59	0	0
T3	128269	6103	0	0
T4	3236	34	0	0
T5	144723	112	0	0
T15	90737	0	0	0
T16	826	6	0	0
T17	12467	67	0	0
T19	48181	292	0	0
T20	3000	9	0	0
T21	0	321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1322920	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1322920	0	0
T1	134303	916	0	0
T2	158040	2879	0	0
T3	128269	15180	0	0
T4	3236	23	0	0
T5	144723	579	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	67	0	0
T19	48181	646	0	0
T20	3000	24	0	0
T21	0	810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2749686	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2749686	0	0
T1	134303	664	0	0
T2	158040	709	0	0
T3	128269	4364	0	0
T4	3236	34	0	0
T5	144723	134	0	0
T15	90737	0	0	0
T16	826	7	0	0
T17	12467	60	0	0
T19	48181	297	0	0
T20	3000	7	0	0
T21	0	334	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	1293223	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	1293223	0	0
T1	134303	2385	0	0
T2	158040	1472	0	0
T3	128269	18280	0	0
T4	3236	6	0	0
T5	144723	596	0	0
T15	90737	0	0	0
T16	826	2	0	0
T17	12467	67	0	0
T19	48181	627	0	0
T20	3000	1	0	0
T21	0	561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296075675	2835720	0	0
DepthKnown_A	296075675	295954485	0	0
RvalidKnown_A	296075675	295954485	0	0
WreadyKnown_A	296075675	295954485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	2835720	0	0
T1	134303	3233	0	0
T2	158040	754	0	0
T3	128269	7236	0	0
T4	3236	3	0	0
T5	144723	1325	0	0
T15	90737	0	0	0
T16	826	2	0	0
T17	12467	35	0	0
T19	48181	202	0	0
T20	3000	1	0	0
T21	0	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296075675	295954485	0	0
T1	134303	134249	0	0
T2	158040	158030	0	0
T3	128269	128267	0	0
T4	3236	3195	0	0
T5	144723	144717	0	0
T15	90737	90698	0	0
T16	826	738	0	0
T17	12467	12450	0	0
T19	48181	48170	0	0
T20	3000	2943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0