Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1910687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

300210

1

T1

193

T2

1304

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	746496	1			T1	904		T2	2974		T3	65
values[0x0]	718669	1			T1	161		T2	3055		T3	47
values[0x1]	745732	1			T1	928		T2	3010		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1481766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

729131

1

T1

747

T2

3071

T3

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8333	1			T1	8		T2	24		T15	9
valid_sources[0x01]	8528	1			T1	4		T2	49		T4	5
valid_sources[0x02]	8191	1			T1	5		T2	24		T3	1
valid_sources[0x03]	8463	1			T1	6		T2	24		T4	1
valid_sources[0x04]	8675	1			T1	8		T2	37		T15	4
valid_sources[0x05]	8097	1			T1	12		T2	28		T3	1
valid_sources[0x06]	8785	1			T1	7		T2	28		T5	4
valid_sources[0x07]	7814	1			T1	5		T2	20		T15	6
valid_sources[0x08]	8607	1			T1	8		T2	15		T3	1
valid_sources[0x09]	8690	1			T1	9		T2	47		T5	1
valid_sources[0x0a]	8571	1			T1	12		T2	23		T5	1
valid_sources[0x0b]	8101	1			T1	9		T2	67		T3	1
valid_sources[0x0c]	9228	1			T1	9		T2	41		T5	2
valid_sources[0x0d]	8573	1			T1	9		T2	23		T15	5
valid_sources[0x0e]	7811	1			T1	7		T2	43		T15	4
valid_sources[0x0f]	8955	1			T1	5		T2	27		T3	1
valid_sources[0x10]	9466	1			T1	7		T2	35		T3	1
valid_sources[0x11]	7829	1			T1	5		T2	63		T3	2
valid_sources[0x12]	8280	1			T1	8		T2	53		T3	1
valid_sources[0x13]	8291	1			T1	5		T2	31		T5	1
valid_sources[0x14]	8255	1			T1	7		T2	17		T3	1
valid_sources[0x15]	7945	1			T1	6		T2	26		T4	1
valid_sources[0x16]	8222	1			T1	6		T2	17		T15	6
valid_sources[0x17]	8458	1			T1	15		T2	14		T15	4
valid_sources[0x18]	9217	1			T1	3		T2	49		T3	1
valid_sources[0x19]	10595	1			T1	12		T2	18		T4	1
valid_sources[0x1a]	8780	1			T1	8		T2	32		T4	1
valid_sources[0x1b]	8415	1			T1	4		T2	33		T3	1
valid_sources[0x1c]	8747	1			T1	7		T2	42		T3	1
valid_sources[0x1d]	8958	1			T1	4		T2	22		T3	1
valid_sources[0x1e]	8058	1			T1	5		T2	29		T4	1
valid_sources[0x1f]	9183	1			T1	6		T2	18		T4	1
valid_sources[0x20]	8708	1			T1	12		T2	24		T3	2
valid_sources[0x21]	8542	1			T1	8		T2	39		T3	2
valid_sources[0x22]	8756	1			T1	6		T2	56		T15	1
valid_sources[0x23]	9334	1			T1	8		T2	24		T3	4
valid_sources[0x24]	8218	1			T1	8		T2	12		T3	1
valid_sources[0x25]	8727	1			T1	6		T2	62		T4	1
valid_sources[0x26]	7952	1			T1	9		T2	23		T3	1
valid_sources[0x27]	7997	1			T1	3		T2	22		T3	5
valid_sources[0x28]	8528	1			T1	5		T2	39		T3	2
valid_sources[0x29]	8661	1			T1	4		T2	14		T3	2
valid_sources[0x2a]	7758	1			T1	9		T2	18		T3	1
valid_sources[0x2b]	9490	1			T1	6		T2	22		T3	1
valid_sources[0x2c]	9766	1			T1	12		T2	39		T3	1
valid_sources[0x2d]	8419	1			T1	17		T2	35		T15	12
valid_sources[0x2e]	7914	1			T1	4		T2	47		T15	9
valid_sources[0x2f]	8156	1			T1	7		T2	29		T5	1
valid_sources[0x30]	8971	1			T1	11		T2	26		T4	1
valid_sources[0x31]	9030	1			T1	4		T2	16		T4	2
valid_sources[0x32]	8484	1			T1	11		T2	27		T3	1
valid_sources[0x33]	8122	1			T1	9		T2	37		T5	1
valid_sources[0x34]	8770	1			T1	6		T2	66		T3	2
valid_sources[0x35]	8715	1			T1	3		T2	44		T15	13
valid_sources[0x36]	9014	1			T1	7		T2	17		T3	1
valid_sources[0x37]	8307	1			T1	3		T2	49		T3	1
valid_sources[0x38]	7979	1			T1	7		T2	53		T3	1
valid_sources[0x39]	8961	1			T1	12		T2	19		T3	1
valid_sources[0x3a]	7848	1			T1	7		T2	19		T3	1
valid_sources[0x3b]	9057	1			T1	4		T2	42		T15	8
valid_sources[0x3c]	9379	1			T1	7		T2	28		T15	11
valid_sources[0x3d]	8184	1			T1	3		T2	38		T5	2
valid_sources[0x3e]	8115	1			T1	18		T2	44		T15	10
valid_sources[0x3f]	8466	1			T1	17		T2	20		T5	3
valid_sources[0x40]	8806	1			T1	5		T2	39		T15	11
valid_sources[0x41]	10876	1			T1	5		T2	19		T3	1
valid_sources[0x42]	8770	1			T1	12		T2	33		T4	28
valid_sources[0x43]	9115	1			T1	11		T2	50		T4	3
valid_sources[0x44]	8298	1			T1	9		T2	24		T3	1
valid_sources[0x45]	9257	1			T1	6		T2	37		T4	10
valid_sources[0x46]	8701	1			T1	6		T2	28		T3	1
valid_sources[0x47]	9227	1			T1	9		T2	45		T3	1
valid_sources[0x48]	8739	1			T1	6		T2	32		T4	5
valid_sources[0x49]	8834	1			T1	8		T2	39		T3	1
valid_sources[0x4a]	8152	1			T1	6		T2	35		T3	1
valid_sources[0x4b]	8651	1			T1	11		T2	42		T3	1
valid_sources[0x4c]	8563	1			T1	9		T2	32		T5	5
valid_sources[0x4d]	9610	1			T1	12		T2	20		T3	1
valid_sources[0x4e]	7652	1			T1	14		T2	48		T3	1
valid_sources[0x4f]	8357	1			T1	6		T2	25		T3	1
valid_sources[0x50]	9309	1			T1	4		T2	40		T3	2
valid_sources[0x51]	9263	1			T1	8		T2	38		T4	2
valid_sources[0x52]	8592	1			T1	8		T2	36		T15	18
valid_sources[0x53]	8082	1			T1	5		T2	51		T15	8
valid_sources[0x54]	8275	1			T1	4		T2	54		T3	1
valid_sources[0x55]	8055	1			T1	2		T2	76		T4	3
valid_sources[0x56]	8732	1			T1	7		T2	21		T3	1
valid_sources[0x57]	8521	1			T1	5		T2	53		T3	1
valid_sources[0x58]	8120	1			T1	9		T2	27		T4	1
valid_sources[0x59]	8855	1			T1	8		T2	21		T3	2
valid_sources[0x5a]	8121	1			T1	4		T2	41		T3	1
valid_sources[0x5b]	8887	1			T1	14		T2	32		T3	2
valid_sources[0x5c]	8616	1			T1	10		T2	20		T5	2
valid_sources[0x5d]	9124	1			T1	5		T2	41		T15	13
valid_sources[0x5e]	9459	1			T1	2		T2	46		T4	1
valid_sources[0x5f]	8595	1			T1	7		T2	47		T15	1
valid_sources[0x60]	8759	1			T1	6		T2	34		T5	3
valid_sources[0x61]	9168	1			T1	8		T2	67		T3	1
valid_sources[0x62]	8414	1			T1	6		T2	18		T4	1
valid_sources[0x63]	9850	1			T1	9		T2	36		T3	1
valid_sources[0x64]	8647	1			T1	15		T2	54		T3	2
valid_sources[0x65]	8531	1			T1	8		T2	57		T3	1
valid_sources[0x66]	8739	1			T1	3		T2	37		T15	7
valid_sources[0x67]	7967	1			T1	6		T2	47		T3	1
valid_sources[0x68]	9387	1			T1	5		T2	21		T3	2
valid_sources[0x69]	8707	1			T1	6		T2	42		T3	1
valid_sources[0x6a]	8273	1			T1	4		T2	59		T3	1
valid_sources[0x6b]	8309	1			T1	7		T2	55		T3	1
valid_sources[0x6c]	8588	1			T1	7		T2	32		T5	1
valid_sources[0x6d]	8360	1			T1	11		T2	16		T3	1
valid_sources[0x6e]	7836	1			T1	5		T2	74		T4	2
valid_sources[0x6f]	8684	1			T1	11		T2	29		T3	1
valid_sources[0x70]	10471	1			T1	4		T2	37		T3	1
valid_sources[0x71]	9756	1			T1	10		T2	77		T5	1
valid_sources[0x72]	8392	1			T1	11		T2	48		T3	1
valid_sources[0x73]	9246	1			T1	5		T2	59		T4	2
valid_sources[0x74]	8717	1			T1	7		T2	38		T3	1
valid_sources[0x75]	7813	1			T1	8		T2	38		T15	12
valid_sources[0x76]	9701	1			T1	6		T2	12		T15	5
valid_sources[0x77]	8040	1			T1	7		T2	23		T15	11
valid_sources[0x78]	8883	1			T1	8		T2	21		T4	1
valid_sources[0x79]	9361	1			T1	5		T2	21		T4	1
valid_sources[0x7a]	9107	1			T1	6		T2	23		T3	1
valid_sources[0x7b]	8147	1			T1	6		T2	45		T4	1
valid_sources[0x7c]	9592	1			T1	9		T2	17		T3	1
valid_sources[0x7d]	8378	1			T1	9		T2	50		T15	17
valid_sources[0x7e]	8692	1			T1	9		T2	30		T4	3
valid_sources[0x7f]	7881	1			T1	10		T2	26		T5	3
valid_sources[0x80]	8339	1			T1	9		T2	37		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31397

1

T1

61

T2

148

T3

1

values[0x0]

all_enables

biggest_size

237739

1

T1

63

T2

1028

T3

13

values[0x1]

all_enables

biggest_size

31074

1

T1

69

T2

128

T3

2