Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	339169573	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339169573	0	0
T1	4641952	202503	0	0
T2	964432	41814	0	0
T3	5082168	90545	0	0
T4	8964984	162392	0	0
T5	4916744	87484	0	0
T15	257880	11460	0	0
T16	26701192	544701	0	0
T17	335720	6790	0	0
T18	36568	603	0	0
T19	6155912	264828	0	0
T20	0	390	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4641952	4551456	0	0
T2	964432	928256	0	0
T3	5082168	5079928	0	0
T4	8964984	8935248	0	0
T5	4916744	4913216	0	0
T15	257880	257208	0	0
T16	26701192	26689432	0	0
T17	335720	333816	0	0
T18	36568	33544	0	0
T19	6155912	6028400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4641952	4551456	0	0
T2	964432	928256	0	0
T3	5082168	5079928	0	0
T4	8964984	8935248	0	0
T5	4916744	4913216	0	0
T15	257880	257208	0	0
T16	26701192	26689432	0	0
T17	335720	333816	0	0
T18	36568	33544	0	0
T19	6155912	6028400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4641952	4551456	0	0
T2	964432	928256	0	0
T3	5082168	5079928	0	0
T4	8964984	8935248	0	0
T5	4916744	4913216	0	0
T15	257880	257208	0	0
T16	26701192	26689432	0	0
T17	335720	333816	0	0
T18	36568	33544	0	0
T19	6155912	6028400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	128862374	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	128862374	0	0
T1	82892	78232	0	0
T2	17222	15999	0	0
T3	90753	87962	0	0
T4	160089	65873	0	0
T5	87799	85550	0	0
T15	4605	4467	0	0
T16	476807	213190	0	0
T17	5995	2792	0	0
T18	653	278	0	0
T19	109927	103021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	85137337	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	85137337	0	0
T1	82892	44377	0	0
T2	17222	9039	0	0
T3	90753	897	0	0
T4	160089	24465	0	0
T5	87799	593	0	0
T15	4605	2331	0	0
T16	476807	111374	0	0
T17	5995	1204	0	0
T18	653	167	0	0
T19	109927	57168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1526816	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1526816	0	0
T1	82892	1438	0	0
T2	17222	420	0	0
T3	90753	73	0	0
T4	160089	440	0	0
T5	87799	16	0	0
T15	4605	99	0	0
T16	476807	7174	0	0
T17	5995	15	0	0
T18	653	0	0	0
T19	109927	1856	0	0
T20	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2668362	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2668362	0	0
T1	82892	1438	0	0
T2	17222	420	0	0
T3	90753	13	0	0
T4	160089	241	0	0
T5	87799	4	0	0
T15	4605	99	0	0
T16	476807	6735	0	0
T17	5995	28	0	0
T18	653	0	0	0
T19	109927	1856	0	0
T20	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1478792	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1478792	0	0
T1	82892	969	0	0
T2	17222	182	0	0
T3	90753	16	0	0
T4	160089	575	0	0
T5	87799	17	0	0
T15	4605	76	0	0
T16	476807	4832	0	0
T17	5995	108	0	0
T18	653	5	0	0
T19	109927	1541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3121878	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3121878	0	0
T1	82892	968	0	0
T2	17222	181	0	0
T3	90753	4	0	0
T4	160089	316	0	0
T5	87799	5	0	0
T15	4605	76	0	0
T16	476807	3712	0	0
T17	5995	113	0	0
T18	653	5	0	0
T19	109927	1539	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1507881	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1507881	0	0
T1	82892	962	0	0
T2	17222	401	0	0
T3	90753	7	0	0
T4	160089	473	0	0
T5	87799	17	0	0
T15	4605	76	0	0
T16	476807	5742	0	0
T17	5995	11	0	0
T18	653	2	0	0
T19	109927	2073	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2442719	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2442719	0	0
T1	82892	962	0	0
T2	17222	401	0	0
T3	90753	1	0	0
T4	160089	250	0	0
T5	87799	4	0	0
T15	4605	76	0	0
T16	476807	4297	0	0
T17	5995	16	0	0
T18	653	2	0	0
T19	109927	2073	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1525118	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1525118	0	0
T1	82892	1467	0	0
T2	17222	199	0	0
T3	90753	10	0	0
T4	160089	3391	0	0
T5	87799	34	0	0
T15	4605	94	0	0
T16	476807	2901	0	0
T17	5995	58	0	0
T18	653	9	0	0
T19	109927	2989	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2957187	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2957187	0	0
T1	82892	1467	0	0
T2	17222	199	0	0
T3	90753	2	0	0
T4	160089	1365	0	0
T5	87799	8	0	0
T15	4605	94	0	0
T16	476807	2650	0	0
T17	5995	51	0	0
T18	653	9	0	0
T19	109927	2988	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1559204	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1559204	0	0
T1	82892	904	0	0
T2	17222	183	0	0
T3	90753	24	0	0
T4	160089	3654	0	0
T5	87799	43	0	0
T15	4605	77	0	0
T16	476807	2688	0	0
T17	5995	59	0	0
T18	653	3	0	0
T19	109927	1925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2980418	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2980418	0	0
T1	82892	904	0	0
T2	17222	183	0	0
T3	90753	9	0	0
T4	160089	2675	0	0
T5	87799	9	0	0
T15	4605	77	0	0
T16	476807	2307	0	0
T17	5995	24	0	0
T18	653	3	0	0
T19	109927	1924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1514777	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1514777	0	0
T1	82892	1158	0	0
T2	17222	459	0	0
T3	90753	36	0	0
T4	160089	638	0	0
T5	87799	28	0	0
T15	4605	72	0	0
T16	476807	3335	0	0
T17	5995	55	0	0
T18	653	4	0	0
T19	109927	1972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3170413	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3170413	0	0
T1	82892	1158	0	0
T2	17222	458	0	0
T3	90753	8	0	0
T4	160089	187	0	0
T5	87799	4	0	0
T15	4605	72	0	0
T16	476807	2723	0	0
T17	5995	26	0	0
T18	653	4	0	0
T19	109927	1972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1525829	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1525829	0	0
T1	82892	1232	0	0
T2	17222	413	0	0
T3	90753	37	0	0
T4	160089	2413	0	0
T5	87799	42	0	0
T15	4605	102	0	0
T16	476807	2521	0	0
T17	5995	43	0	0
T18	653	5	0	0
T19	109927	2595	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3022800	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3022800	0	0
T1	82892	1232	0	0
T2	17222	413	0	0
T3	90753	7	0	0
T4	160089	928	0	0
T5	87799	9	0	0
T15	4605	102	0	0
T16	476807	2164	0	0
T17	5995	34	0	0
T18	653	5	0	0
T19	109927	2595	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1494088	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1494088	0	0
T1	82892	1242	0	0
T2	17222	439	0	0
T3	90753	38	0	0
T4	160089	5233	0	0
T5	87799	42	0	0
T15	4605	83	0	0
T16	476807	4595	0	0
T17	5995	41	0	0
T18	653	2	0	0
T19	109927	1525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3289463	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3289463	0	0
T1	82892	1242	0	0
T2	17222	439	0	0
T3	90753	8	0	0
T4	160089	2068	0	0
T5	87799	6	0	0
T15	4605	83	0	0
T16	476807	3502	0	0
T17	5995	25	0	0
T18	653	2	0	0
T19	109927	1525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1496342	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1496342	0	0
T1	82892	1241	0	0
T2	17222	217	0	0
T3	90753	28	0	0
T4	160089	523	0	0
T5	87799	32	0	0
T15	4605	72	0	0
T16	476807	4013	0	0
T17	5995	7	0	0
T18	653	1	0	0
T19	109927	1515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2748787	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2748787	0	0
T1	82892	1241	0	0
T2	17222	217	0	0
T3	90753	8	0	0
T4	160089	240	0	0
T5	87799	8	0	0
T15	4605	72	0	0
T16	476807	3426	0	0
T17	5995	9	0	0
T18	653	1	0	0
T19	109927	1515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1542354	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1542354	0	0
T1	82892	944	0	0
T2	17222	220	0	0
T3	90753	18	0	0
T4	160089	607	0	0
T5	87799	14	0	0
T15	4605	102	0	0
T16	476807	6033	0	0
T17	5995	122	0	0
T18	653	0	0	0
T19	109927	1790	0	0
T20	0	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3755037	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3755037	0	0
T1	82892	944	0	0
T2	17222	220	0	0
T3	90753	6	0	0
T4	160089	287	0	0
T5	87799	2	0	0
T15	4605	102	0	0
T16	476807	5285	0	0
T17	5995	78	0	0
T18	653	0	0	0
T19	109927	1790	0	0
T20	0	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1543413	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1543413	0	0
T1	82892	1681	0	0
T2	17222	470	0	0
T3	90753	57	0	0
T4	160089	4186	0	0
T5	87799	38	0	0
T15	4605	81	0	0
T16	476807	7656	0	0
T17	5995	78	0	0
T18	653	4	0	0
T19	109927	2279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2693364	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2693364	0	0
T1	82892	1681	0	0
T2	17222	470	0	0
T3	90753	12	0	0
T4	160089	2309	0	0
T5	87799	7	0	0
T15	4605	81	0	0
T16	476807	5652	0	0
T17	5995	93	0	0
T18	653	4	0	0
T19	109927	2279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1498017	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1498017	0	0
T1	82892	1906	0	0
T2	17222	461	0	0
T3	90753	20	0	0
T4	160089	560	0	0
T5	87799	15	0	0
T15	4605	81	0	0
T16	476807	3819	0	0
T17	5995	80	0	0
T18	653	2	0	0
T19	109927	2252	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3287552	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3287552	0	0
T1	82892	1906	0	0
T2	17222	461	0	0
T3	90753	6	0	0
T4	160089	233	0	0
T5	87799	6	0	0
T15	4605	81	0	0
T16	476807	3338	0	0
T17	5995	59	0	0
T18	653	2	0	0
T19	109927	2250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1532517	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1532517	0	0
T1	82892	1854	0	0
T2	17222	200	0	0
T3	90753	9	0	0
T4	160089	547	0	0
T5	87799	24	0	0
T15	4605	79	0	0
T16	476807	5069	0	0
T17	5995	31	0	0
T18	653	1	0	0
T19	109927	2057	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3131548	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3131548	0	0
T1	82892	1854	0	0
T2	17222	200	0	0
T3	90753	2	0	0
T4	160089	278	0	0
T5	87799	5	0	0
T15	4605	79	0	0
T16	476807	4249	0	0
T17	5995	47	0	0
T18	653	1	0	0
T19	109927	2057	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1519782	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1519782	0	0
T1	82892	1707	0	0
T2	17222	208	0	0
T3	90753	17	0	0
T4	160089	5156	0	0
T5	87799	34	0	0
T15	4605	99	0	0
T16	476807	3186	0	0
T17	5995	66	0	0
T18	653	2	0	0
T19	109927	1568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3404733	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3404733	0	0
T1	82892	1707	0	0
T2	17222	208	0	0
T3	90753	3	0	0
T4	160089	2108	0	0
T5	87799	5	0	0
T15	4605	99	0	0
T16	476807	2806	0	0
T17	5995	27	0	0
T18	653	2	0	0
T19	109927	1568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1502632	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1502632	0	0
T1	82892	1435	0	0
T2	17222	407	0	0
T3	90753	28	0	0
T4	160089	784	0	0
T5	87799	11	0	0
T15	4605	92	0	0
T16	476807	9733	0	0
T17	5995	44	0	0
T18	653	4	0	0
T19	109927	1301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2560598	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2560598	0	0
T1	82892	1435	0	0
T2	17222	407	0	0
T3	90753	6	0	0
T4	160089	245	0	0
T5	87799	4	0	0
T15	4605	92	0	0
T16	476807	7146	0	0
T17	5995	20	0	0
T18	653	4	0	0
T19	109927	1301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1590539	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1590539	0	0
T1	82892	1259	0	0
T2	17222	199	0	0
T3	90753	17	0	0
T4	160089	571	0	0
T5	87799	18	0	0
T15	4605	92	0	0
T16	476807	4763	0	0
T17	5995	38	0	0
T18	653	3	0	0
T19	109927	1727	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3171268	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3171268	0	0
T1	82892	1259	0	0
T2	17222	199	0	0
T3	90753	4	0	0
T4	160089	177	0	0
T5	87799	4	0	0
T15	4605	92	0	0
T16	476807	3987	0	0
T17	5995	90	0	0
T18	653	3	0	0
T19	109927	1727	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1506105	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1506105	0	0
T1	82892	1469	0	0
T2	17222	519	0	0
T3	90753	41	0	0
T4	160089	4213	0	0
T5	87799	23	0	0
T15	4605	78	0	0
T16	476807	3114	0	0
T17	5995	26	0	0
T18	653	3	0	0
T19	109927	2460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3553462	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3553462	0	0
T1	82892	1469	0	0
T2	17222	518	0	0
T3	90753	8	0	0
T4	160089	1904	0	0
T5	87799	5	0	0
T15	4605	78	0	0
T16	476807	2695	0	0
T17	5995	15	0	0
T18	653	3	0	0
T19	109927	2460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1477336	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1477336	0	0
T1	82892	1175	0	0
T2	17222	386	0	0
T3	90753	25	0	0
T4	160089	2834	0	0
T5	87799	53	0	0
T15	4605	100	0	0
T16	476807	5140	0	0
T17	5995	32	0	0
T18	653	2	0	0
T19	109927	1760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3424593	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3424593	0	0
T1	82892	1175	0	0
T2	17222	385	0	0
T3	90753	8	0	0
T4	160089	1413	0	0
T5	87799	440	0	0
T15	4605	100	0	0
T16	476807	4016	0	0
T17	5995	19	0	0
T18	653	2	0	0
T19	109927	1760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1565574	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1565574	0	0
T1	82892	1207	0	0
T2	17222	193	0	0
T3	90753	31	0	0
T4	160089	826	0	0
T5	87799	19	0	0
T15	4605	87	0	0
T16	476807	2843	0	0
T17	5995	75	0	0
T18	653	4	0	0
T19	109927	1854	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3558825	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3558825	0	0
T1	82892	1207	0	0
T2	17222	193	0	0
T3	90753	6	0	0
T4	160089	275	0	0
T5	87799	4	0	0
T15	4605	87	0	0
T16	476807	2528	0	0
T17	5995	36	0	0
T18	653	4	0	0
T19	109927	1854	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1554213	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1554213	0	0
T1	82892	1413	0	0
T2	17222	208	0	0
T3	90753	26	0	0
T4	160089	455	0	0
T5	87799	32	0	0
T15	4605	100	0	0
T16	476807	2994	0	0
T17	5995	13	0	0
T18	653	2	0	0
T19	109927	2238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3104833	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3104833	0	0
T1	82892	1413	0	0
T2	17222	208	0	0
T3	90753	6	0	0
T4	160089	226	0	0
T5	87799	9	0	0
T15	4605	100	0	0
T16	476807	2535	0	0
T17	5995	10	0	0
T18	653	2	0	0
T19	109927	2238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1520967	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1520967	0	0
T1	82892	1679	0	0
T2	17222	443	0	0
T3	90753	40	0	0
T4	160089	531	0	0
T5	87799	20	0	0
T15	4605	72	0	0
T16	476807	2950	0	0
T17	5995	63	0	0
T18	653	4	0	0
T19	109927	3058	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3354824	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3354824	0	0
T1	82892	1679	0	0
T2	17222	443	0	0
T3	90753	9	0	0
T4	160089	277	0	0
T5	87799	6	0	0
T15	4605	72	0	0
T16	476807	2514	0	0
T17	5995	59	0	0
T18	653	4	0	0
T19	109927	3058	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1525036	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1525036	0	0
T1	82892	1239	0	0
T2	17222	222	0	0
T3	90753	33	0	0
T4	160089	555	0	0
T5	87799	34	0	0
T15	4605	77	0	0
T16	476807	4646	0	0
T17	5995	40	0	0
T18	653	3	0	0
T19	109927	1621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3215669	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3215669	0	0
T1	82892	1238	0	0
T2	17222	222	0	0
T3	90753	5	0	0
T4	160089	234	0	0
T5	87799	7	0	0
T15	4605	77	0	0
T16	476807	3764	0	0
T17	5995	17	0	0
T18	653	3	0	0
T19	109927	1621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1518067	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1518067	0	0
T1	82892	1707	0	0
T2	17222	213	0	0
T3	90753	34	0	0
T4	160089	2704	0	0
T5	87799	32	0	0
T15	4605	82	0	0
T16	476807	7402	0	0
T17	5995	81	0	0
T18	653	2	0	0
T19	109927	2053	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3431191	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3431191	0	0
T1	82892	1707	0	0
T2	17222	213	0	0
T3	90753	7	0	0
T4	160089	1324	0	0
T5	87799	6	0	0
T15	4605	82	0	0
T16	476807	5950	0	0
T17	5995	44	0	0
T18	653	2	0	0
T19	109927	2053	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1512312	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1512312	0	0
T1	82892	2212	0	0
T2	17222	189	0	0
T3	90753	44	0	0
T4	160089	3383	0	0
T5	87799	23	0	0
T15	4605	86	0	0
T16	476807	4933	0	0
T17	5995	127	0	0
T18	653	2	0	0
T19	109927	2339	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2708366	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2708366	0	0
T1	82892	2212	0	0
T2	17222	189	0	0
T3	90753	10	0	0
T4	160089	1925	0	0
T5	87799	5	0	0
T15	4605	86	0	0
T16	476807	3884	0	0
T17	5995	75	0	0
T18	653	2	0	0
T19	109927	2339	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1530718	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1530718	0	0
T1	82892	1665	0	0
T2	17222	435	0	0
T3	90753	42	0	0
T4	160089	530	0	0
T5	87799	32	0	0
T15	4605	97	0	0
T16	476807	2909	0	0
T17	5995	63	0	0
T18	653	3	0	0
T19	109927	1274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3301086	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3301086	0	0
T1	82892	1665	0	0
T2	17222	435	0	0
T3	90753	728	0	0
T4	160089	227	0	0
T5	87799	7	0	0
T15	4605	97	0	0
T16	476807	2555	0	0
T17	5995	70	0	0
T18	653	3	0	0
T19	109927	1274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1487675	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1487675	0	0
T1	82892	2408	0	0
T2	17222	215	0	0
T3	90753	21	0	0
T4	160089	2491	0	0
T5	87799	16	0	0
T15	4605	84	0	0
T16	476807	2925	0	0
T17	5995	59	0	0
T18	653	5	0	0
T19	109927	1505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	2736963	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	2736963	0	0
T1	82892	2408	0	0
T2	17222	215	0	0
T3	90753	6	0	0
T4	160089	1124	0	0
T5	87799	7	0	0
T15	4605	84	0	0
T16	476807	2345	0	0
T17	5995	50	0	0
T18	653	5	0	0
T19	109927	1505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	1515373	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	1515373	0	0
T1	82892	2375	0	0
T2	17222	289	0	0
T3	90753	17	0	0
T4	160089	657	0	0
T5	87799	40	0	0
T15	4605	91	0	0
T16	476807	2843	0	0
T17	5995	155	0	0
T18	653	2	0	0
T19	109927	1196	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304555489	3302446	0	0
DepthKnown_A	304555489	304431482	0	0
RvalidKnown_A	304555489	304431482	0	0
WreadyKnown_A	304555489	304431482	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	3302446	0	0
T1	82892	2375	0	0
T2	17222	289	0	0
T3	90753	5	0	0
T4	160089	288	0	0
T5	87799	6	0	0
T15	4605	91	0	0
T16	476807	2613	0	0
T17	5995	69	0	0
T18	653	2	0	0
T19	109927	1195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304555489	304431482	0	0
T1	82892	81276	0	0
T2	17222	16576	0	0
T3	90753	90713	0	0
T4	160089	159558	0	0
T5	87799	87736	0	0
T15	4605	4593	0	0
T16	476807	476597	0	0
T17	5995	5961	0	0
T18	653	599	0	0
T19	109927	107650	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0