Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1695893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

267883

1

T1

38

T2

18

T3

655

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	663630	1			T1	155		T2	45		T3	1610
values[0x0]	637026	1			T1	28		T2	51		T3	1602
values[0x1]	663120	1			T1	157		T2	62		T3	1543

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1315710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

648066

1

T1

135

T2

52

T3

1523

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7509	1			T1	1		T3	9		T4	29
valid_sources[0x01]	8019	1			T1	2		T3	19		T4	25
valid_sources[0x02]	8072	1			T1	1		T3	9		T4	12
valid_sources[0x03]	8121	1			T1	2		T3	31		T4	28
valid_sources[0x04]	7457	1			T1	1		T3	15		T4	11
valid_sources[0x05]	6934	1			T1	3		T3	8		T4	25
valid_sources[0x06]	7957	1			T3	12		T4	27		T19	2
valid_sources[0x07]	7918	1			T1	2		T3	16		T4	19
valid_sources[0x08]	7363	1			T1	2		T3	19		T4	32
valid_sources[0x09]	7747	1			T1	3		T3	6		T4	34
valid_sources[0x0a]	7626	1			T3	18		T4	18		T21	2
valid_sources[0x0b]	8811	1			T1	3		T3	29		T4	36
valid_sources[0x0c]	7688	1			T3	20		T4	51		T21	2
valid_sources[0x0d]	7575	1			T1	3		T3	20		T4	19
valid_sources[0x0e]	6710	1			T1	2		T3	25		T4	55
valid_sources[0x0f]	7132	1			T1	2		T3	25		T4	15
valid_sources[0x10]	7998	1			T1	2		T3	29		T4	20
valid_sources[0x11]	8661	1			T1	4		T3	4		T4	5
valid_sources[0x12]	8162	1			T1	1		T3	9		T4	13
valid_sources[0x13]	7809	1			T1	3		T3	38		T4	8
valid_sources[0x14]	7421	1			T1	1		T3	9		T4	9
valid_sources[0x15]	8032	1			T1	2		T3	9		T4	28
valid_sources[0x16]	7119	1			T1	2		T3	15		T4	42
valid_sources[0x17]	7357	1			T1	1		T3	5		T4	7
valid_sources[0x18]	6694	1			T1	4		T3	30		T4	27
valid_sources[0x19]	9128	1			T1	2		T3	14		T4	18
valid_sources[0x1a]	7743	1			T1	4		T3	16		T4	53
valid_sources[0x1b]	6788	1			T1	1		T3	22		T4	27
valid_sources[0x1c]	7011	1			T3	17		T4	10		T20	1
valid_sources[0x1d]	7148	1			T1	2		T3	26		T4	34
valid_sources[0x1e]	7095	1			T1	3		T3	17		T4	25
valid_sources[0x1f]	6774	1			T1	1		T3	23		T4	17
valid_sources[0x20]	7367	1			T1	2		T3	58		T4	41
valid_sources[0x21]	7121	1			T1	2		T3	25		T4	28
valid_sources[0x22]	7390	1			T3	22		T4	4		T20	1
valid_sources[0x23]	8503	1			T1	2		T3	23		T4	23
valid_sources[0x24]	6931	1			T1	2		T3	4		T4	27
valid_sources[0x25]	7418	1			T1	3		T3	30		T4	6
valid_sources[0x26]	8009	1			T1	2		T3	15		T4	32
valid_sources[0x27]	7395	1			T3	17		T4	17		T21	5
valid_sources[0x28]	8284	1			T1	2		T3	10		T4	19
valid_sources[0x29]	8454	1			T1	2		T3	32		T4	18
valid_sources[0x2a]	7536	1			T1	1		T3	21		T4	24
valid_sources[0x2b]	7815	1			T1	1		T3	20		T4	31
valid_sources[0x2c]	7590	1			T3	23		T4	63		T20	1
valid_sources[0x2d]	8814	1			T3	12		T4	22		T17	1
valid_sources[0x2e]	7644	1			T2	38		T3	23		T4	18
valid_sources[0x2f]	7254	1			T3	5		T4	5		T17	1
valid_sources[0x30]	6774	1			T1	1		T3	26		T4	59
valid_sources[0x31]	6948	1			T1	1		T3	9		T4	19
valid_sources[0x32]	7345	1			T1	2		T3	20		T4	25
valid_sources[0x33]	7835	1			T1	1		T3	22		T4	65
valid_sources[0x34]	6687	1			T1	2		T3	4		T4	12
valid_sources[0x35]	9362	1			T3	6		T4	12		T17	1
valid_sources[0x36]	8894	1			T1	2		T3	13		T4	19
valid_sources[0x37]	8088	1			T1	3		T3	15		T4	36
valid_sources[0x38]	7119	1			T3	12		T4	29		T17	1
valid_sources[0x39]	7949	1			T3	14		T4	16		T21	1
valid_sources[0x3a]	9344	1			T1	2		T3	35		T4	12
valid_sources[0x3b]	7050	1			T1	1		T3	25		T4	12
valid_sources[0x3c]	7178	1			T1	1		T3	33		T4	10
valid_sources[0x3d]	8045	1			T3	2		T4	15		T19	12
valid_sources[0x3e]	7272	1			T3	15		T4	38		T18	1
valid_sources[0x3f]	8015	1			T1	1		T3	15		T4	28
valid_sources[0x40]	6429	1			T1	4		T3	26		T4	27
valid_sources[0x41]	10096	1			T1	1		T3	20		T4	14
valid_sources[0x42]	7036	1			T3	16		T4	32		T17	2
valid_sources[0x43]	6636	1			T1	1		T3	32		T4	22
valid_sources[0x44]	8368	1			T1	3		T3	6		T4	16
valid_sources[0x45]	7845	1			T1	2		T3	31		T4	14
valid_sources[0x46]	7778	1			T1	1		T3	5		T4	14
valid_sources[0x47]	7234	1			T3	23		T4	33		T18	1
valid_sources[0x48]	7070	1			T1	1		T3	18		T4	28
valid_sources[0x49]	8220	1			T3	21		T4	29		T21	9
valid_sources[0x4a]	7893	1			T1	1		T3	14		T4	24
valid_sources[0x4b]	7045	1			T1	1		T3	25		T4	28
valid_sources[0x4c]	8489	1			T1	2		T3	12		T4	13
valid_sources[0x4d]	7009	1			T1	1		T3	3		T4	28
valid_sources[0x4e]	8213	1			T1	2		T3	17		T4	35
valid_sources[0x4f]	6998	1			T3	13		T4	24		T18	1
valid_sources[0x50]	8277	1			T3	32		T4	17		T18	1
valid_sources[0x51]	7170	1			T1	2		T3	18		T4	21
valid_sources[0x52]	7812	1			T1	2		T3	12		T4	19
valid_sources[0x53]	8239	1			T1	3		T2	13		T3	14
valid_sources[0x54]	7036	1			T1	2		T3	15		T4	22
valid_sources[0x55]	6603	1			T1	3		T3	19		T4	30
valid_sources[0x56]	6651	1			T1	1		T3	18		T4	11
valid_sources[0x57]	7706	1			T1	2		T3	23		T4	22
valid_sources[0x58]	7587	1			T1	1		T3	42		T4	15
valid_sources[0x59]	7881	1			T1	1		T3	39		T4	29
valid_sources[0x5a]	8714	1			T3	24		T4	9		T19	7
valid_sources[0x5b]	7229	1			T1	2		T3	8		T4	30
valid_sources[0x5c]	8472	1			T1	4		T2	79		T3	15
valid_sources[0x5d]	7990	1			T1	2		T3	5		T4	19
valid_sources[0x5e]	7596	1			T1	2		T3	9		T4	37
valid_sources[0x5f]	8045	1			T1	2		T3	12		T4	8
valid_sources[0x60]	7080	1			T1	1		T3	22		T4	44
valid_sources[0x61]	7349	1			T1	2		T3	7		T4	19
valid_sources[0x62]	8869	1			T3	43		T4	31		T17	1
valid_sources[0x63]	8053	1			T3	11		T4	30		T19	8
valid_sources[0x64]	7421	1			T1	1		T3	20		T4	10
valid_sources[0x65]	7863	1			T1	3		T3	19		T4	21
valid_sources[0x66]	7465	1			T1	2		T3	18		T4	11
valid_sources[0x67]	9341	1			T1	3		T3	19		T4	27
valid_sources[0x68]	7989	1			T3	13		T4	34		T20	38
valid_sources[0x69]	7823	1			T1	4		T3	30		T4	14
valid_sources[0x6a]	7409	1			T3	22		T4	16		T20	2
valid_sources[0x6b]	7585	1			T3	25		T4	14		T18	2
valid_sources[0x6c]	7781	1			T3	18		T4	20		T20	1
valid_sources[0x6d]	7284	1			T1	2		T3	36		T4	55
valid_sources[0x6e]	7129	1			T1	5		T3	12		T4	34
valid_sources[0x6f]	8267	1			T3	26		T4	12		T18	1
valid_sources[0x70]	8228	1			T1	3		T3	19		T4	10
valid_sources[0x71]	7925	1			T1	2		T3	18		T4	14
valid_sources[0x72]	7508	1			T1	2		T3	13		T4	18
valid_sources[0x73]	7784	1			T1	1		T3	20		T4	10
valid_sources[0x74]	7307	1			T3	29		T4	19		T20	2
valid_sources[0x75]	9533	1			T1	1		T3	16		T4	16
valid_sources[0x76]	8057	1			T1	1		T3	13		T4	29
valid_sources[0x77]	7935	1			T3	32		T4	20		T21	19
valid_sources[0x78]	7976	1			T1	1		T3	20		T4	18
valid_sources[0x79]	7306	1			T1	1		T3	32		T4	8
valid_sources[0x7a]	7634	1			T3	18		T4	16		T18	1
valid_sources[0x7b]	7394	1			T1	1		T4	20		T21	7
valid_sources[0x7c]	7123	1			T1	2		T3	6		T4	7
valid_sources[0x7d]	6701	1			T1	3		T3	38		T4	21
valid_sources[0x7e]	7703	1			T1	1		T3	12		T4	13
valid_sources[0x7f]	7899	1			T3	34		T4	11		T17	1
valid_sources[0x80]	7413	1			T3	20		T4	22		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28233

1

T1

16

T2

1

T3

61

values[0x0]

all_enables

biggest_size

211648

1

T1

12

T2

16

T3

534

values[0x1]

all_enables

biggest_size

28002

1

T1

10

T2

1

T3

60