Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	335216103	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50232	50232	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335216103	0	0
T1	9511432	171015	0	0
T2	230664	4163	0	0
T3	278880	19017	0	0
T4	8333360	195998	0	0
T14	142240	2767	0	0
T17	1459584	29972	0	0
T18	245616	10902	0	0
T19	741496	16409	0	0
T20	1440880	65317	0	0
T21	172592	7533	0	0
T22	0	64611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9511432	9507400	0	0
T2	230664	230160	0	0
T3	278880	277816	0	0
T4	8333360	8300936	0	0
T14	142240	141680	0	0
T17	1459584	1456616	0	0
T18	245616	244832	0	0
T19	741496	714616	0	0
T20	1440880	1396640	0	0
T21	172592	171248	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9511432	9507400	0	0
T2	230664	230160	0	0
T3	278880	277816	0	0
T4	8333360	8300936	0	0
T14	142240	141680	0	0
T17	1459584	1456616	0	0
T18	245616	244832	0	0
T19	741496	714616	0	0
T20	1440880	1396640	0	0
T21	172592	171248	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9511432	9507400	0	0
T2	230664	230160	0	0
T3	278880	277816	0	0
T4	8333360	8300936	0	0
T14	142240	141680	0	0
T17	1459584	1456616	0	0
T18	245616	244832	0	0
T19	741496	714616	0	0
T20	1440880	1396640	0	0
T21	172592	171248	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50232	50232	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	119640130	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	119640130	0	0
T1	169847	78830	0	0
T2	4119	1943	0	0
T3	4980	4756	0	0
T4	148810	69249	0	0
T14	2540	1263	0	0
T17	26064	11149	0	0
T18	4386	4233	0	0
T19	13241	6503	0	0
T20	25730	22825	0	0
T21	3082	2921	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	88838457	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	88838457	0	0
T1	169847	22364	0	0
T2	4119	473	0	0
T3	4980	4755	0	0
T4	148810	47818	0	0
T14	2540	355	0	0
T17	26064	10090	0	0
T18	4386	2223	0	0
T19	13241	3596	0	0
T20	25730	14486	0	0
T21	3082	1538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1452252	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1452252	0	0
T1	169847	1573	0	0
T2	4119	42	0	0
T3	4980	0	0	0
T4	148810	781	0	0
T14	2540	55	0	0
T17	26064	95	0	0
T18	4386	78	0	0
T19	13241	60	0	0
T20	25730	512	0	0
T21	3082	61	0	0
T22	0	2624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3623118	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3623118	0	0
T1	169847	647	0	0
T2	4119	21	0	0
T3	4980	0	0	0
T4	148810	922	0	0
T14	2540	18	0	0
T17	26064	81	0	0
T18	4386	78	0	0
T19	13241	73	0	0
T20	25730	512	0	0
T21	3082	61	0	0
T22	0	3239	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1431382	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1431382	0	0
T1	169847	1378	0	0
T2	4119	55	0	0
T3	4980	202	0	0
T4	148810	934	0	0
T14	2540	44	0	0
T17	26064	180	0	0
T18	4386	97	0	0
T19	13241	57	0	0
T20	25730	228	0	0
T21	3082	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	4113114	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	4113114	0	0
T1	169847	612	0	0
T2	4119	18	0	0
T3	4980	202	0	0
T4	148810	980	0	0
T14	2540	13	0	0
T17	26064	146	0	0
T18	4386	97	0	0
T19	13241	50	0	0
T20	25730	228	0	0
T21	3082	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1450934	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1450934	0	0
T1	169847	1481	0	0
T2	4119	46	0	0
T3	4980	495	0	0
T4	148810	2738	0	0
T14	2540	31	0	0
T17	26064	132	0	0
T18	4386	71	0	0
T19	13241	90	0	0
T20	25730	739	0	0
T21	3082	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3284259	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3284259	0	0
T1	169847	578	0	0
T2	4119	24	0	0
T3	4980	495	0	0
T4	148810	3376	0	0
T14	2540	9	0	0
T17	26064	148	0	0
T18	4386	71	0	0
T19	13241	101	0	0
T20	25730	739	0	0
T21	3082	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1426471	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1426471	0	0
T1	169847	3446	0	0
T2	4119	58	0	0
T3	4980	507	0	0
T4	148810	2419	0	0
T14	2540	12	0	0
T17	26064	186	0	0
T18	4386	77	0	0
T19	13241	140	0	0
T20	25730	468	0	0
T21	3082	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3626961	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3626961	0	0
T1	169847	1356	0	0
T2	4119	32	0	0
T3	4980	507	0	0
T4	148810	2989	0	0
T14	2540	1	0	0
T17	26064	165	0	0
T18	4386	77	0	0
T19	13241	158	0	0
T20	25730	468	0	0
T21	3082	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1442734	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1442734	0	0
T1	169847	1480	0	0
T2	4119	17	0	0
T3	4980	209	0	0
T4	148810	825	0	0
T14	2540	18	0	0
T17	26064	231	0	0
T18	4386	97	0	0
T19	13241	99	0	0
T20	25730	693	0	0
T21	3082	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3683352	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3683352	0	0
T1	169847	553	0	0
T2	4119	13	0	0
T3	4980	209	0	0
T4	148810	717	0	0
T14	2540	10	0	0
T17	26064	160	0	0
T18	4386	97	0	0
T19	13241	121	0	0
T20	25730	693	0	0
T21	3082	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1434738	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1434738	0	0
T1	169847	2760	0	0
T2	4119	85	0	0
T3	4980	299	0	0
T4	148810	979	0	0
T14	2540	42	0	0
T17	26064	179	0	0
T18	4386	77	0	0
T19	13241	70	0	0
T20	25730	811	0	0
T21	3082	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3114346	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3114346	0	0
T1	169847	1040	0	0
T2	4119	20	0	0
T3	4980	299	0	0
T4	148810	870	0	0
T14	2540	10	0	0
T17	26064	179	0	0
T18	4386	77	0	0
T19	13241	92	0	0
T20	25730	811	0	0
T21	3082	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1432198	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1432198	0	0
T1	169847	1311	0	0
T2	4119	49	0	0
T3	4980	0	0	0
T4	148810	805	0	0
T14	2540	34	0	0
T17	26064	211	0	0
T18	4386	82	0	0
T19	13241	128	0	0
T20	25730	207	0	0
T21	3082	51	0	0
T22	0	2862	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3451870	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3451870	0	0
T1	169847	453	0	0
T2	4119	7	0	0
T3	4980	0	0	0
T4	148810	817	0	0
T14	2540	31	0	0
T17	26064	202	0	0
T18	4386	82	0	0
T19	13241	105	0	0
T20	25730	206	0	0
T21	3082	51	0	0
T22	0	2924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1422738	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1422738	0	0
T1	169847	1385	0	0
T2	4119	25	0	0
T3	4980	203	0	0
T4	148810	907	0	0
T14	2540	31	0	0
T17	26064	151	0	0
T18	4386	74	0	0
T19	13241	59	0	0
T20	25730	494	0	0
T21	3082	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2452922	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2452922	0	0
T1	169847	573	0	0
T2	4119	8	0	0
T3	4980	203	0	0
T4	148810	897	0	0
T14	2540	17	0	0
T17	26064	144	0	0
T18	4386	74	0	0
T19	13241	76	0	0
T20	25730	494	0	0
T21	3082	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1453050	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1453050	0	0
T1	169847	1262	0	0
T2	4119	54	0	0
T3	4980	245	0	0
T4	148810	838	0	0
T14	2540	47	0	0
T17	26064	195	0	0
T18	4386	77	0	0
T19	13241	63	0	0
T20	25730	239	0	0
T21	3082	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3499442	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3499442	0	0
T1	169847	506	0	0
T2	4119	7	0	0
T3	4980	245	0	0
T4	148810	889	0	0
T14	2540	41	0	0
T17	26064	186	0	0
T18	4386	77	0	0
T19	13241	108	0	0
T20	25730	239	0	0
T21	3082	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1386974	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1386974	0	0
T1	169847	1543	0	0
T2	4119	28	0	0
T3	4980	231	0	0
T4	148810	847	0	0
T14	2540	37	0	0
T17	26064	181	0	0
T18	4386	100	0	0
T19	13241	106	0	0
T20	25730	435	0	0
T21	3082	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2741343	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2741343	0	0
T1	169847	589	0	0
T2	4119	9	0	0
T3	4980	231	0	0
T4	148810	904	0	0
T14	2540	31	0	0
T17	26064	160	0	0
T18	4386	100	0	0
T19	13241	118	0	0
T20	25730	434	0	0
T21	3082	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1448190	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1448190	0	0
T1	169847	1381	0	0
T2	4119	29	0	0
T3	4980	483	0	0
T4	148810	3569	0	0
T14	2540	24	0	0
T17	26064	159	0	0
T18	4386	92	0	0
T19	13241	79	0	0
T20	25730	574	0	0
T21	3082	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2977483	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2977483	0	0
T1	169847	694	0	0
T2	4119	4	0	0
T3	4980	483	0	0
T4	148810	3258	0	0
T14	2540	15	0	0
T17	26064	123	0	0
T18	4386	92	0	0
T19	13241	65	0	0
T20	25730	574	0	0
T21	3082	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1429598	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1429598	0	0
T1	169847	1260	0	0
T2	4119	37	0	0
T3	4980	0	0	0
T4	148810	619	0	0
T14	2540	52	0	0
T17	26064	198	0	0
T18	4386	79	0	0
T19	13241	59	0	0
T20	25730	661	0	0
T21	3082	61	0	0
T22	0	703	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3142728	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3142728	0	0
T1	169847	577	0	0
T2	4119	8	0	0
T3	4980	0	0	0
T4	148810	745	0	0
T14	2540	18	0	0
T17	26064	192	0	0
T18	4386	79	0	0
T19	13241	76	0	0
T20	25730	661	0	0
T21	3082	61	0	0
T22	0	854	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1468138	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1468138	0	0
T1	169847	3500	0	0
T2	4119	21	0	0
T3	4980	0	0	0
T4	148810	777	0	0
T14	2540	46	0	0
T17	26064	105	0	0
T18	4386	95	0	0
T19	13241	93	0	0
T20	25730	475	0	0
T21	3082	69	0	0
T22	0	2440	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3003601	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3003601	0	0
T1	169847	1411	0	0
T2	4119	9	0	0
T3	4980	0	0	0
T4	148810	779	0	0
T14	2540	22	0	0
T17	26064	152	0	0
T18	4386	95	0	0
T19	13241	105	0	0
T20	25730	474	0	0
T21	3082	69	0	0
T22	0	2659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1449283	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1449283	0	0
T1	169847	1237	0	0
T2	4119	44	0	0
T3	4980	204	0	0
T4	148810	6275	0	0
T14	2540	36	0	0
T17	26064	224	0	0
T18	4386	92	0	0
T19	13241	170	0	0
T20	25730	237	0	0
T21	3082	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3279868	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3279868	0	0
T1	169847	565	0	0
T2	4119	13	0	0
T3	4980	204	0	0
T4	148810	5884	0	0
T14	2540	12	0	0
T17	26064	158	0	0
T18	4386	92	0	0
T19	13241	128	0	0
T20	25730	237	0	0
T21	3082	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1414062	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1414062	0	0
T1	169847	1495	0	0
T2	4119	79	0	0
T3	4980	544	0	0
T4	148810	1162	0	0
T14	2540	26	0	0
T17	26064	142	0	0
T18	4386	77	0	0
T19	13241	64	0	0
T20	25730	535	0	0
T21	3082	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3379438	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3379438	0	0
T1	169847	621	0	0
T2	4119	40	0	0
T3	4980	544	0	0
T4	148810	926	0	0
T14	2540	13	0	0
T17	26064	141	0	0
T18	4386	77	0	0
T19	13241	89	0	0
T20	25730	535	0	0
T21	3082	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1426235	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1426235	0	0
T1	169847	1086	0	0
T2	4119	61	0	0
T3	4980	0	0	0
T4	148810	839	0	0
T14	2540	47	0	0
T17	26064	151	0	0
T18	4386	84	0	0
T19	13241	38	0	0
T20	25730	253	0	0
T21	3082	48	0	0
T22	0	2703	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2545353	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2545353	0	0
T1	169847	452	0	0
T2	4119	28	0	0
T3	4980	0	0	0
T4	148810	883	0	0
T14	2540	18	0	0
T17	26064	164	0	0
T18	4386	84	0	0
T19	13241	53	0	0
T20	25730	252	0	0
T21	3082	48	0	0
T22	0	2718	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1454350	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1454350	0	0
T1	169847	1361	0	0
T2	4119	7	0	0
T3	4980	273	0	0
T4	148810	3299	0	0
T14	2540	17	0	0
T17	26064	150	0	0
T18	4386	65	0	0
T19	13241	106	0	0
T20	25730	254	0	0
T21	3082	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2846124	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2846124	0	0
T1	169847	611	0	0
T2	4119	11	0	0
T3	4980	273	0	0
T4	148810	3124	0	0
T14	2540	11	0	0
T17	26064	151	0	0
T18	4386	65	0	0
T19	13241	133	0	0
T20	25730	254	0	0
T21	3082	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1478225	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1478225	0	0
T1	169847	1717	0	0
T2	4119	72	0	0
T3	4980	0	0	0
T4	148810	785	0	0
T14	2540	6	0	0
T17	26064	78	0	0
T18	4386	92	0	0
T19	13241	60	0	0
T20	25730	470	0	0
T21	3082	68	0	0
T22	0	875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3457580	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3457580	0	0
T1	169847	597	0	0
T2	4119	34	0	0
T3	4980	0	0	0
T4	148810	748	0	0
T14	2540	8	0	0
T17	26064	116	0	0
T18	4386	92	0	0
T19	13241	45	0	0
T20	25730	470	0	0
T21	3082	68	0	0
T22	0	774	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1438078	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1438078	0	0
T1	169847	1531	0	0
T2	4119	86	0	0
T3	4980	292	0	0
T4	148810	792	0	0
T14	2540	29	0	0
T17	26064	232	0	0
T18	4386	72	0	0
T19	13241	125	0	0
T20	25730	737	0	0
T21	3082	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2962245	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2962245	0	0
T1	169847	575	0	0
T2	4119	38	0	0
T3	4980	292	0	0
T4	148810	830	0	0
T14	2540	10	0	0
T17	26064	219	0	0
T18	4386	72	0	0
T19	13241	156	0	0
T20	25730	737	0	0
T21	3082	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1469091	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1469091	0	0
T1	169847	1397	0	0
T2	4119	77	0	0
T3	4980	0	0	0
T4	148810	753	0	0
T14	2540	34	0	0
T17	26064	238	0	0
T18	4386	103	0	0
T19	13241	105	0	0
T20	25730	824	0	0
T21	3082	52	0	0
T22	0	852	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3599373	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3599373	0	0
T1	169847	514	0	0
T2	4119	28	0	0
T3	4980	0	0	0
T4	148810	793	0	0
T14	2540	9	0	0
T17	26064	143	0	0
T18	4386	103	0	0
T19	13241	110	0	0
T20	25730	824	0	0
T21	3082	52	0	0
T22	0	799	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1409971	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1409971	0	0
T1	169847	1522	0	0
T2	4119	67	0	0
T3	4980	0	0	0
T4	148810	841	0	0
T14	2540	6	0	0
T17	26064	138	0	0
T18	4386	84	0	0
T19	13241	508	0	0
T20	25730	224	0	0
T21	3082	66	0	0
T22	0	5587	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3755699	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3755699	0	0
T1	169847	690	0	0
T2	4119	36	0	0
T3	4980	0	0	0
T4	148810	980	0	0
T14	2540	2	0	0
T17	26064	134	0	0
T18	4386	84	0	0
T19	13241	468	0	0
T20	25730	224	0	0
T21	3082	66	0	0
T22	0	7092	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1421271	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1421271	0	0
T1	169847	1592	0	0
T2	4119	23	0	0
T3	4980	0	0	0
T4	148810	901	0	0
T14	2540	15	0	0
T17	26064	158	0	0
T18	4386	83	0	0
T19	13241	350	0	0
T20	25730	454	0	0
T21	3082	49	0	0
T22	0	1015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3504802	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3504802	0	0
T1	169847	559	0	0
T2	4119	10	0	0
T3	4980	0	0	0
T4	148810	921	0	0
T14	2540	3	0	0
T17	26064	130	0	0
T18	4386	83	0	0
T19	13241	320	0	0
T20	25730	454	0	0
T21	3082	49	0	0
T22	0	868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1435836	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1435836	0	0
T1	169847	3763	0	0
T2	4119	71	0	0
T3	4980	283	0	0
T4	148810	953	0	0
T14	2540	18	0	0
T17	26064	152	0	0
T18	4386	81	0	0
T19	13241	63	0	0
T20	25730	696	0	0
T21	3082	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3225798	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3225798	0	0
T1	169847	1392	0	0
T2	4119	10	0	0
T3	4980	283	0	0
T4	148810	1019	0	0
T14	2540	11	0	0
T17	26064	177	0	0
T18	4386	81	0	0
T19	13241	88	0	0
T20	25730	696	0	0
T21	3082	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1492435	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1492435	0	0
T1	169847	1440	0	0
T2	4119	18	0	0
T3	4980	0	0	0
T4	148810	648	0	0
T14	2540	36	0	0
T17	26064	142	0	0
T18	4386	89	0	0
T19	13241	107	0	0
T20	25730	1032	0	0
T21	3082	68	0	0
T22	0	876	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3927199	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3927199	0	0
T1	169847	550	0	0
T2	4119	6	0	0
T3	4980	0	0	0
T4	148810	607	0	0
T14	2540	8	0	0
T17	26064	192	0	0
T18	4386	89	0	0
T19	13241	105	0	0
T20	25730	1032	0	0
T21	3082	68	0	0
T22	0	835	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1432002	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1432002	0	0
T1	169847	2752	0	0
T2	4119	45	0	0
T3	4980	283	0	0
T4	148810	849	0	0
T14	2540	0	0	0
T17	26064	157	0	0
T18	4386	66	0	0
T19	13241	80	0	0
T20	25730	481	0	0
T21	3082	49	0	0
T22	0	3007	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2743063	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2743063	0	0
T1	169847	1234	0	0
T2	4119	15	0	0
T3	4980	283	0	0
T4	148810	816	0	0
T14	2540	0	0	0
T17	26064	107	0	0
T18	4386	66	0	0
T19	13241	94	0	0
T20	25730	481	0	0
T21	3082	49	0	0
T22	0	3055	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1447004	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1447004	0	0
T1	169847	1415	0	0
T2	4119	33	0	0
T3	4980	0	0	0
T4	148810	889	0	0
T14	2540	16	0	0
T17	26064	206	0	0
T18	4386	78	0	0
T19	13241	91	0	0
T20	25730	474	0	0
T21	3082	62	0	0
T22	0	4511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	3475366	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	3475366	0	0
T1	169847	543	0	0
T2	4119	6	0	0
T3	4980	0	0	0
T4	148810	976	0	0
T14	2540	3	0	0
T17	26064	216	0	0
T18	4386	78	0	0
T19	13241	109	0	0
T20	25730	474	0	0
T21	3082	62	0	0
T22	0	4621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	1466346	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	1466346	0	0
T1	169847	3746	0	0
T2	4119	45	0	0
T3	4980	0	0	0
T4	148810	3110	0	0
T14	2540	36	0	0
T17	26064	154	0	0
T18	4386	61	0	0
T19	13241	99	0	0
T20	25730	798	0	0
T21	3082	43	0	0
T22	0	2952	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306179047	2407483	0	0
DepthKnown_A	306179047	306054013	0	0
RvalidKnown_A	306179047	306054013	0	0
WreadyKnown_A	306179047	306054013	0	0
gen_passthru_fifo.paramCheckPass	897	897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	2407483	0	0
T1	169847	1515	0	0
T2	4119	18	0	0
T3	4980	0	0	0
T4	148810	3147	0	0
T14	2540	10	0	0
T17	26064	122	0	0
T18	4386	61	0	0
T19	13241	95	0	0
T20	25730	798	0	0
T21	3082	43	0	0
T22	0	3166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306179047	306054013	0	0
T1	169847	169775	0	0
T2	4119	4110	0	0
T3	4980	4961	0	0
T4	148810	148231	0	0
T14	2540	2530	0	0
T17	26064	26011	0	0
T18	4386	4372	0	0
T19	13241	12761	0	0
T20	25730	24940	0	0
T21	3082	3058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	897	897	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0