Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1703226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269193

1

T1

396

T2

361

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	665825	1			T1	964		T2	909		T3	56
values[0x0]	640494	1			T1	1023		T2	849		T3	11
values[0x1]	666100	1			T1	1013		T2	925		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1321089	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

651330

1

T1

981

T2

899

T3

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7325	1			T2	4		T3	1		T4	67
valid_sources[0x01]	7700	1			T1	3		T2	13		T4	11
valid_sources[0x02]	7190	1			T1	25		T2	24		T4	35
valid_sources[0x03]	9357	1			T2	10		T4	45		T14	4
valid_sources[0x04]	8024	1			T1	18		T2	9		T3	1
valid_sources[0x05]	6834	1			T2	23		T4	5		T14	8
valid_sources[0x06]	7062	1			T2	14		T3	2		T4	18
valid_sources[0x07]	7437	1			T1	18		T2	23		T4	22
valid_sources[0x08]	7657	1			T1	10		T2	3		T4	33
valid_sources[0x09]	7144	1			T1	52		T2	9		T4	15
valid_sources[0x0a]	7292	1			T2	3		T4	28		T14	5
valid_sources[0x0b]	8617	1			T1	8		T2	12		T4	24
valid_sources[0x0c]	8094	1			T1	11		T2	2		T4	16
valid_sources[0x0d]	7542	1			T2	10		T3	2		T4	8
valid_sources[0x0e]	7319	1			T2	1		T3	2		T4	34
valid_sources[0x0f]	6713	1			T1	1		T2	8		T4	12
valid_sources[0x10]	8287	1			T1	4		T2	22		T3	1
valid_sources[0x11]	7471	1			T1	1		T2	9		T4	7
valid_sources[0x12]	6736	1			T2	12		T4	19		T14	3
valid_sources[0x13]	7571	1			T1	16		T2	8		T4	24
valid_sources[0x14]	7418	1			T1	36		T2	12		T4	15
valid_sources[0x15]	7649	1			T2	19		T3	1		T4	20
valid_sources[0x16]	6958	1			T2	10		T3	2		T4	18
valid_sources[0x17]	8337	1			T2	15		T4	25		T14	4
valid_sources[0x18]	7140	1			T1	17		T2	13		T3	1
valid_sources[0x19]	7508	1			T1	1		T2	8		T4	43
valid_sources[0x1a]	7114	1			T2	18		T4	9		T14	5
valid_sources[0x1b]	7525	1			T2	18		T4	25		T14	5
valid_sources[0x1c]	8090	1			T2	6		T3	1		T4	13
valid_sources[0x1d]	7325	1			T1	14		T2	18		T4	30
valid_sources[0x1e]	8263	1			T2	4		T4	64		T14	7
valid_sources[0x1f]	8098	1			T1	18		T2	22		T4	16
valid_sources[0x20]	7265	1			T1	13		T2	8		T3	1
valid_sources[0x21]	7673	1			T1	15		T2	18		T4	53
valid_sources[0x22]	10081	1			T1	11		T2	7		T4	23
valid_sources[0x23]	7938	1			T2	26		T4	35		T14	7
valid_sources[0x24]	7163	1			T2	13		T3	2		T4	45
valid_sources[0x25]	7354	1			T1	19		T2	5		T4	21
valid_sources[0x26]	9229	1			T1	5		T2	3		T3	2
valid_sources[0x27]	7707	1			T2	10		T4	24		T14	11
valid_sources[0x28]	8073	1			T1	3		T2	16		T3	2
valid_sources[0x29]	7366	1			T2	4		T3	1		T4	23
valid_sources[0x2a]	7622	1			T1	12		T2	9		T4	43
valid_sources[0x2b]	7243	1			T2	8		T4	7		T12	2
valid_sources[0x2c]	8247	1			T2	4		T4	38		T14	7
valid_sources[0x2d]	6820	1			T1	10		T2	13		T4	19
valid_sources[0x2e]	7574	1			T1	6		T2	21		T4	18
valid_sources[0x2f]	7461	1			T2	10		T3	1		T4	35
valid_sources[0x30]	7254	1			T1	10		T2	5		T4	28
valid_sources[0x31]	7331	1			T1	2		T2	29		T3	1
valid_sources[0x32]	6993	1			T1	6		T2	14		T4	34
valid_sources[0x33]	7181	1			T1	17		T2	6		T3	1
valid_sources[0x34]	9437	1			T1	10		T2	10		T3	1
valid_sources[0x35]	7301	1			T1	8		T2	14		T4	21
valid_sources[0x36]	6768	1			T1	2		T2	11		T4	15
valid_sources[0x37]	6761	1			T1	29		T2	8		T3	1
valid_sources[0x38]	7994	1			T1	5		T2	11		T3	1
valid_sources[0x39]	7001	1			T1	28		T2	8		T3	3
valid_sources[0x3a]	6536	1			T2	12		T4	17		T14	12
valid_sources[0x3b]	7289	1			T1	14		T2	11		T4	19
valid_sources[0x3c]	8118	1			T2	7		T4	52		T14	6
valid_sources[0x3d]	7872	1			T1	3		T2	5		T3	2
valid_sources[0x3e]	7000	1			T1	9		T2	18		T4	40
valid_sources[0x3f]	7418	1			T1	12		T4	17		T14	5
valid_sources[0x40]	7603	1			T1	18		T2	12		T4	45
valid_sources[0x41]	8255	1			T1	2		T2	11		T3	1
valid_sources[0x42]	8298	1			T1	5		T2	9		T3	1
valid_sources[0x43]	6890	1			T1	2		T2	12		T4	22
valid_sources[0x44]	7432	1			T1	33		T2	11		T4	41
valid_sources[0x45]	7960	1			T1	36		T2	11		T4	18
valid_sources[0x46]	8034	1			T2	11		T3	1		T4	33
valid_sources[0x47]	7646	1			T1	28		T2	20		T4	12
valid_sources[0x48]	7407	1			T1	1		T2	7		T4	55
valid_sources[0x49]	6410	1			T1	7		T2	4		T4	15
valid_sources[0x4a]	7296	1			T2	5		T4	48		T12	1
valid_sources[0x4b]	8408	1			T2	14		T3	1		T4	61
valid_sources[0x4c]	7780	1			T1	21		T2	3		T3	1
valid_sources[0x4d]	7546	1			T1	1		T2	12		T4	45
valid_sources[0x4e]	7494	1			T1	34		T2	15		T4	26
valid_sources[0x4f]	7675	1			T2	2		T4	66		T12	1
valid_sources[0x50]	8076	1			T1	4		T2	14		T4	9
valid_sources[0x51]	7929	1			T2	4		T3	2		T4	15
valid_sources[0x52]	8499	1			T1	10		T2	10		T4	41
valid_sources[0x53]	7909	1			T1	15		T2	21		T3	1
valid_sources[0x54]	7410	1			T1	36		T2	4		T3	1
valid_sources[0x55]	9975	1			T1	6		T2	10		T4	13
valid_sources[0x56]	7861	1			T1	7		T2	3		T4	49
valid_sources[0x57]	7400	1			T1	21		T2	10		T4	14
valid_sources[0x58]	7471	1			T1	11		T2	7		T3	1
valid_sources[0x59]	7052	1			T1	3		T2	2		T3	1
valid_sources[0x5a]	7994	1			T1	7		T2	6		T4	17
valid_sources[0x5b]	7157	1			T1	3		T2	6		T3	1
valid_sources[0x5c]	7232	1			T1	13		T2	12		T3	1
valid_sources[0x5d]	8996	1			T1	19		T2	15		T4	26
valid_sources[0x5e]	8080	1			T4	22		T14	6		T16	1
valid_sources[0x5f]	7576	1			T1	6		T2	2		T4	7
valid_sources[0x60]	9048	1			T1	1		T2	11		T3	1
valid_sources[0x61]	7784	1			T1	27		T2	5		T4	27
valid_sources[0x62]	7965	1			T1	45		T2	11		T3	1
valid_sources[0x63]	8696	1			T2	7		T4	37		T14	8
valid_sources[0x64]	8428	1			T1	12		T2	15		T3	1
valid_sources[0x65]	7291	1			T2	11		T4	40		T14	7
valid_sources[0x66]	9727	1			T1	11		T2	10		T4	23
valid_sources[0x67]	7117	1			T1	32		T2	19		T4	27
valid_sources[0x68]	7558	1			T1	18		T2	14		T3	2
valid_sources[0x69]	7492	1			T2	9		T4	19		T14	5
valid_sources[0x6a]	7847	1			T1	6		T2	12		T4	12
valid_sources[0x6b]	7560	1			T2	4		T4	27		T12	1
valid_sources[0x6c]	8032	1			T1	54		T2	1		T3	2
valid_sources[0x6d]	7926	1			T1	80		T2	12		T3	1
valid_sources[0x6e]	9009	1			T1	2		T2	20		T4	41
valid_sources[0x6f]	7782	1			T2	18		T3	1		T4	43
valid_sources[0x70]	7453	1			T2	13		T4	23		T14	10
valid_sources[0x71]	7285	1			T1	6		T2	13		T4	55
valid_sources[0x72]	7962	1			T1	14		T2	6		T4	13
valid_sources[0x73]	7883	1			T2	8		T3	1		T4	18
valid_sources[0x74]	7250	1			T1	21		T2	22		T4	16
valid_sources[0x75]	7640	1			T1	8		T2	15		T3	2
valid_sources[0x76]	7349	1			T2	19		T4	2		T12	2
valid_sources[0x77]	6950	1			T2	1		T4	9		T14	3
valid_sources[0x78]	8196	1			T1	16		T2	6		T4	32
valid_sources[0x79]	7540	1			T1	35		T2	15		T4	8
valid_sources[0x7a]	8160	1			T1	31		T2	20		T4	39
valid_sources[0x7b]	8713	1			T1	4		T2	10		T4	42
valid_sources[0x7c]	6906	1			T1	35		T2	14		T4	26
valid_sources[0x7d]	7728	1			T1	8		T2	9		T3	3
valid_sources[0x7e]	9226	1			T1	11		T4	30		T12	1
valid_sources[0x7f]	7081	1			T1	12		T2	10		T3	1
valid_sources[0x80]	7182	1			T2	9		T4	15		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28245

1

T1

37

T2

56

T3

4

values[0x0]

all_enables

biggest_size

212802

1

T1

328

T2

261

T3

1

values[0x1]

all_enables

biggest_size

28146

1

T1

31

T2

44

T3

1