Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	323978120	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	323978120	0	0
T1	330232	14704	0	0
T2	3462592	71497	0	0
T3	3725456	81088	0	0
T4	875952	33622	0	0
T12	205464	3688	0	0
T13	53144	1636	0	0
T14	1712368	46882	0	0
T15	14342944	356406	0	0
T16	116312	4840	0	0
T17	13492584	2241283	0	0
T18	0	1031222	0	0
T19	0	33037	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	330232	329168	0	0
T2	3462592	3457944	0	0
T3	3725456	3724952	0	0
T4	875952	828016	0	0
T12	205464	202272	0	0
T13	53144	51464	0	0
T14	1712368	1709848	0	0
T15	14342944	14341824	0	0
T16	116312	115136	0	0
T17	13492584	13492360	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	330232	329168	0	0
T2	3462592	3457944	0	0
T3	3725456	3724952	0	0
T4	875952	828016	0	0
T12	205464	202272	0	0
T13	53144	51464	0	0
T14	1712368	1709848	0	0
T15	14342944	14341824	0	0
T16	116312	115136	0	0
T17	13492584	13492360	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	330232	329168	0	0
T2	3462592	3457944	0	0
T3	3725456	3724952	0	0
T4	875952	828016	0	0
T12	205464	202272	0	0
T13	53144	51464	0	0
T14	1712368	1709848	0	0
T15	14342944	14341824	0	0
T16	116312	115136	0	0
T17	13492584	13492360	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	120963427	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	120963427	0	0
T1	5897	5706	0	0
T2	61832	27349	0	0
T3	66526	34971	0	0
T4	15642	13334	0	0
T12	3669	1564	0	0
T13	949	746	0	0
T14	30578	10965	0	0
T15	256124	164637	0	0
T16	2077	1891	0	0
T17	240939	236463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	83853580	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	83853580	0	0
T1	5897	3000	0	0
T2	61832	23331	0	0
T3	66526	14387	0	0
T4	15642	7617	0	0
T12	3669	643	0	0
T13	949	426	0	0
T14	30578	12476	0	0
T15	256124	63278	0	0
T16	2077	983	0	0
T17	240939	996666	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1341540	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1341540	0	0
T1	5897	118	0	0
T2	61832	261	0	0
T3	66526	810	0	0
T4	15642	317	0	0
T12	3669	13	0	0
T13	949	11	0	0
T14	30578	998	0	0
T15	256124	1928	0	0
T16	2077	29	0	0
T17	240939	439	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3146712	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3146712	0	0
T1	5897	118	0	0
T2	61832	353	0	0
T3	66526	700	0	0
T4	15642	317	0	0
T12	3669	12	0	0
T13	949	11	0	0
T14	30578	1524	0	0
T15	256124	2996	0	0
T16	2077	29	0	0
T17	240939	36614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1342586	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1342586	0	0
T1	5897	94	0	0
T2	61832	399	0	0
T3	66526	708	0	0
T4	15642	418	0	0
T12	3669	31	0	0
T13	949	13	0	0
T14	30578	0	0	0
T15	256124	505	0	0
T16	2077	41	0	0
T17	240939	436	0	0
T18	0	1224	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3168881	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3168881	0	0
T1	5897	94	0	0
T2	61832	365	0	0
T3	66526	502	0	0
T4	15642	418	0	0
T12	3669	20	0	0
T13	949	13	0	0
T14	30578	0	0	0
T15	256124	697	0	0
T16	2077	41	0	0
T17	240939	38439	0	0
T18	0	93507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1337838	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1337838	0	0
T1	5897	122	0	0
T2	61832	348	0	0
T3	66526	639	0	0
T4	15642	413	0	0
T12	3669	20	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	5510	0	0
T16	2077	37	0	0
T17	240939	407	0	0
T19	0	1863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3379213	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3379213	0	0
T1	5897	122	0	0
T2	61832	354	0	0
T3	66526	430	0	0
T4	15642	413	0	0
T12	3669	22	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	4048	0	0
T16	2077	37	0	0
T17	240939	34981	0	0
T19	0	925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1364195	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1364195	0	0
T1	5897	124	0	0
T2	61832	327	0	0
T3	66526	516	0	0
T4	15642	420	0	0
T12	3669	0	0	0
T13	949	7	0	0
T14	30578	1961	0	0
T15	256124	1096	0	0
T16	2077	41	0	0
T17	240939	471	0	0
T19	0	1762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3063914	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3063914	0	0
T1	5897	124	0	0
T2	61832	321	0	0
T3	66526	402	0	0
T4	15642	420	0	0
T12	3669	0	0	0
T13	949	7	0	0
T14	30578	2442	0	0
T15	256124	2204	0	0
T16	2077	41	0	0
T17	240939	34649	0	0
T19	0	943	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1373154	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1373154	0	0
T1	5897	114	0	0
T2	61832	364	0	0
T3	66526	564	0	0
T4	15642	107	0	0
T12	3669	17	0	0
T13	949	5	0	0
T14	30578	1629	0	0
T15	256124	2800	0	0
T16	2077	34	0	0
T17	240939	421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3215750	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3215750	0	0
T1	5897	114	0	0
T2	61832	406	0	0
T3	66526	509	0	0
T4	15642	107	0	0
T12	3669	2	0	0
T13	949	5	0	0
T14	30578	1773	0	0
T15	256124	2724	0	0
T16	2077	34	0	0
T17	240939	37173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1297968	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1297968	0	0
T1	5897	106	0	0
T2	61832	528	0	0
T3	66526	772	0	0
T4	15642	397	0	0
T12	3669	30	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	3444	0	0
T16	2077	27	0	0
T17	240939	522	0	0
T19	0	1721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2944489	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2944489	0	0
T1	5897	106	0	0
T2	61832	534	0	0
T3	66526	677	0	0
T4	15642	397	0	0
T12	3669	29	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	2828	0	0
T16	2077	27	0	0
T17	240939	38235	0	0
T19	0	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1354073	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1354073	0	0
T1	5897	107	0	0
T2	61832	364	0	0
T3	66526	691	0	0
T4	15642	122	0	0
T12	3669	76	0	0
T13	949	12	0	0
T14	30578	0	0	0
T15	256124	2335	0	0
T16	2077	35	0	0
T17	240939	418	0	0
T18	0	1324	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2952030	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2952030	0	0
T1	5897	107	0	0
T2	61832	400	0	0
T3	66526	559	0	0
T4	15642	122	0	0
T12	3669	71	0	0
T13	949	12	0	0
T14	30578	0	0	0
T15	256124	2357	0	0
T16	2077	35	0	0
T17	240939	38659	0	0
T18	0	101946	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1318918	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1318918	0	0
T1	5897	115	0	0
T2	61832	399	0	0
T3	66526	517	0	0
T4	15642	833	0	0
T12	3669	70	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	1825	0	0
T16	2077	34	0	0
T17	240939	442	0	0
T19	0	1526	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3251839	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3251839	0	0
T1	5897	115	0	0
T2	61832	501	0	0
T3	66526	558	0	0
T4	15642	833	0	0
T12	3669	37	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	1408	0	0
T16	2077	34	0	0
T17	240939	32399	0	0
T19	0	996	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1356871	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1356871	0	0
T1	5897	96	0	0
T2	61832	367	0	0
T3	66526	685	0	0
T4	15642	117	0	0
T12	3669	25	0	0
T13	949	12	0	0
T14	30578	0	0	0
T15	256124	2699	0	0
T16	2077	36	0	0
T17	240939	401	0	0
T18	0	2530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3071569	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3071569	0	0
T1	5897	96	0	0
T2	61832	280	0	0
T3	66526	572	0	0
T4	15642	117	0	0
T12	3669	14	0	0
T13	949	12	0	0
T14	30578	0	0	0
T15	256124	2506	0	0
T16	2077	36	0	0
T17	240939	37570	0	0
T18	0	193039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1374503	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1374503	0	0
T1	5897	116	0	0
T2	61832	289	0	0
T3	66526	608	0	0
T4	15642	383	0	0
T12	3669	31	0	0
T13	949	7	0	0
T14	30578	2251	0	0
T15	256124	3399	0	0
T16	2077	38	0	0
T17	240939	359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2972666	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2972666	0	0
T1	5897	116	0	0
T2	61832	368	0	0
T3	66526	369	0	0
T4	15642	383	0	0
T12	3669	24	0	0
T13	949	7	0	0
T14	30578	2289	0	0
T15	256124	2413	0	0
T16	2077	38	0	0
T17	240939	27745	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1410736	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1410736	0	0
T1	5897	106	0	0
T2	61832	424	0	0
T3	66526	571	0	0
T4	15642	101	0	0
T12	3669	9	0	0
T13	949	6	0	0
T14	30578	0	0	0
T15	256124	1999	0	0
T16	2077	33	0	0
T17	240939	488	0	0
T18	0	1031	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3337356	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3337356	0	0
T1	5897	106	0	0
T2	61832	451	0	0
T3	66526	594	0	0
T4	15642	101	0	0
T12	3669	14	0	0
T13	949	6	0	0
T14	30578	0	0	0
T15	256124	2345	0	0
T16	2077	33	0	0
T17	240939	38606	0	0
T18	0	76367	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1323553	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1323553	0	0
T1	5897	110	0	0
T2	61832	339	0	0
T3	66526	779	0	0
T4	15642	380	0	0
T12	3669	33	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	683	0	0
T16	2077	33	0	0
T17	240939	447	0	0
T19	0	1782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2621088	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2621088	0	0
T1	5897	110	0	0
T2	61832	319	0	0
T3	66526	633	0	0
T4	15642	380	0	0
T12	3669	30	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	366	0	0
T16	2077	33	0	0
T17	240939	35638	0	0
T19	0	822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1338401	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1338401	0	0
T1	5897	92	0	0
T2	61832	388	0	0
T3	66526	666	0	0
T4	15642	389	0	0
T12	3669	7	0	0
T13	949	6	0	0
T14	30578	0	0	0
T15	256124	2419	0	0
T16	2077	36	0	0
T17	240939	450	0	0
T18	0	1042	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3681352	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3681352	0	0
T1	5897	92	0	0
T2	61832	337	0	0
T3	66526	498	0	0
T4	15642	389	0	0
T12	3669	3	0	0
T13	949	6	0	0
T14	30578	0	0	0
T15	256124	3203	0	0
T16	2077	36	0	0
T17	240939	36101	0	0
T18	0	81605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1350912	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1350912	0	0
T1	5897	102	0	0
T2	61832	482	0	0
T3	66526	621	0	0
T4	15642	92	0	0
T12	3669	27	0	0
T13	949	9	0	0
T14	30578	0	0	0
T15	256124	2645	0	0
T16	2077	45	0	0
T17	240939	519	0	0
T19	0	2010	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2562526	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2562526	0	0
T1	5897	102	0	0
T2	61832	535	0	0
T3	66526	478	0	0
T4	15642	92	0	0
T12	3669	33	0	0
T13	949	9	0	0
T14	30578	0	0	0
T15	256124	2823	0	0
T16	2077	45	0	0
T17	240939	41515	0	0
T19	0	1054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1369235	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1369235	0	0
T1	5897	119	0	0
T2	61832	290	0	0
T3	66526	591	0	0
T4	15642	116	0	0
T12	3669	23	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	3320	0	0
T16	2077	42	0	0
T17	240939	376	0	0
T18	0	1298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3178553	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3178553	0	0
T1	5897	119	0	0
T2	61832	331	0	0
T3	66526	584	0	0
T4	15642	116	0	0
T12	3669	52	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	2321	0	0
T16	2077	42	0	0
T17	240939	34321	0	0
T18	0	101540	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1311088	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1311088	0	0
T1	5897	117	0	0
T2	61832	453	0	0
T3	66526	682	0	0
T4	15642	325	0	0
T12	3669	32	0	0
T13	949	3	0	0
T14	30578	0	0	0
T15	256124	1571	0	0
T16	2077	42	0	0
T17	240939	437	0	0
T19	0	1859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3089205	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3089205	0	0
T1	5897	117	0	0
T2	61832	386	0	0
T3	66526	518	0	0
T4	15642	324	0	0
T12	3669	17	0	0
T13	949	3	0	0
T14	30578	0	0	0
T15	256124	2011	0	0
T16	2077	42	0	0
T17	240939	32881	0	0
T19	0	942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1312237	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1312237	0	0
T1	5897	105	0	0
T2	61832	491	0	0
T3	66526	638	0	0
T4	15642	112	0	0
T12	3669	47	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	1731	0	0
T16	2077	36	0	0
T17	240939	422	0	0
T19	0	1971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3218779	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3218779	0	0
T1	5897	105	0	0
T2	61832	463	0	0
T3	66526	617	0	0
T4	15642	112	0	0
T12	3669	17	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	1696	0	0
T16	2077	36	0	0
T17	240939	32411	0	0
T19	0	1041	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1349491	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1349491	0	0
T1	5897	115	0	0
T2	61832	227	0	0
T3	66526	605	0	0
T4	15642	110	0	0
T12	3669	53	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	1252	0	0
T16	2077	38	0	0
T17	240939	492	0	0
T19	0	1816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3619043	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3619043	0	0
T1	5897	115	0	0
T2	61832	299	0	0
T3	66526	495	0	0
T4	15642	110	0	0
T12	3669	53	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	1127	0	0
T16	2077	38	0	0
T17	240939	44663	0	0
T19	0	904	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1339822	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1339822	0	0
T1	5897	105	0	0
T2	61832	410	0	0
T3	66526	657	0	0
T4	15642	125	0	0
T12	3669	29	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	3675	0	0
T16	2077	29	0	0
T17	240939	439	0	0
T18	0	1319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3288738	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3288738	0	0
T1	5897	105	0	0
T2	61832	371	0	0
T3	66526	701	0	0
T4	15642	125	0	0
T12	3669	29	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	2298	0	0
T16	2077	29	0	0
T17	240939	36965	0	0
T18	0	103645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1300160	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1300160	0	0
T1	5897	113	0	0
T2	61832	440	0	0
T3	66526	537	0	0
T4	15642	121	0	0
T12	3669	34	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	1423	0	0
T16	2077	35	0	0
T17	240939	358	0	0
T19	0	1920	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2410073	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2410073	0	0
T1	5897	113	0	0
T2	61832	393	0	0
T3	66526	453	0	0
T4	15642	121	0	0
T12	3669	12	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	2165	0	0
T16	2077	35	0	0
T17	240939	33974	0	0
T19	0	1006	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1323162	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1323162	0	0
T1	5897	99	0	0
T2	61832	464	0	0
T3	66526	698	0	0
T4	15642	125	0	0
T12	3669	45	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	2764	0	0
T16	2077	26	0	0
T17	240939	445	0	0
T19	0	1701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2420136	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2420136	0	0
T1	5897	99	0	0
T2	61832	392	0	0
T3	66526	571	0	0
T4	15642	125	0	0
T12	3669	29	0	0
T13	949	10	0	0
T14	30578	0	0	0
T15	256124	1232	0	0
T16	2077	26	0	0
T17	240939	36999	0	0
T19	0	983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1366736	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1366736	0	0
T1	5897	126	0	0
T2	61832	537	0	0
T3	66526	679	0	0
T4	15642	109	0	0
T12	3669	46	0	0
T13	949	11	0	0
T14	30578	0	0	0
T15	256124	3513	0	0
T16	2077	49	0	0
T17	240939	480	0	0
T18	0	928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3385663	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3385663	0	0
T1	5897	126	0	0
T2	61832	457	0	0
T3	66526	577	0	0
T4	15642	109	0	0
T12	3669	12	0	0
T13	949	11	0	0
T14	30578	0	0	0
T15	256124	6003	0	0
T16	2077	49	0	0
T17	240939	43926	0	0
T18	0	68551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1371317	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1371317	0	0
T1	5897	128	0	0
T2	61832	378	0	0
T3	66526	540	0	0
T4	15642	117	0	0
T12	3669	14	0	0
T13	949	8	0	0
T14	30578	0	0	0
T15	256124	2766	0	0
T16	2077	34	0	0
T17	240939	446	0	0
T18	0	1029	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3616492	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3616492	0	0
T1	5897	128	0	0
T2	61832	353	0	0
T3	66526	408	0	0
T4	15642	117	0	0
T12	3669	13	0	0
T13	949	8	0	0
T14	30578	0	0	0
T15	256124	1722	0	0
T16	2077	34	0	0
T17	240939	33019	0	0
T18	0	86385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1345696	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1345696	0	0
T1	5897	122	0	0
T2	61832	408	0	0
T3	66526	675	0	0
T4	15642	95	0	0
T12	3669	20	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	1683	0	0
T16	2077	41	0	0
T17	240939	489	0	0
T18	0	1341	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2432828	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2432828	0	0
T1	5897	122	0	0
T2	61832	362	0	0
T3	66526	557	0	0
T4	15642	95	0	0
T12	3669	8	0	0
T13	949	7	0	0
T14	30578	0	0	0
T15	256124	2032	0	0
T16	2077	41	0	0
T17	240939	35209	0	0
T18	0	111571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1335717	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1335717	0	0
T1	5897	105	0	0
T2	61832	317	0	0
T3	66526	579	0	0
T4	15642	122	0	0
T12	3669	16	0	0
T13	949	13	0	0
T14	30578	1801	0	0
T15	256124	3575	0	0
T16	2077	39	0	0
T17	240939	481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	3137705	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	3137705	0	0
T1	5897	105	0	0
T2	61832	316	0	0
T3	66526	385	0	0
T4	15642	122	0	0
T12	3669	15	0	0
T13	949	13	0	0
T14	30578	2108	0	0
T15	256124	3153	0	0
T16	2077	39	0	0
T17	240939	42774	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1310834	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1310834	0	0
T1	5897	114	0	0
T2	61832	455	0	0
T3	66526	708	0	0
T4	15642	110	0	0
T12	3669	19	0	0
T13	949	9	0	0
T14	30578	0	0	0
T15	256124	2727	0	0
T16	2077	31	0	0
T17	240939	467	0	0
T19	0	1589	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2955627	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2955627	0	0
T1	5897	114	0	0
T2	61832	328	0	0
T3	66526	575	0	0
T4	15642	110	0	0
T12	3669	14	0	0
T13	949	9	0	0
T14	30578	0	0	0
T15	256124	2552	0	0
T16	2077	31	0	0
T17	240939	42298	0	0
T19	0	930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	1370321	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	1370321	0	0
T1	5897	109	0	0
T2	61832	313	0	0
T3	66526	607	0	0
T4	15642	260	0	0
T12	3669	71	0	0
T13	949	8	0	0
T14	30578	2325	0	0
T15	256124	1926	0	0
T16	2077	42	0	0
T17	240939	497	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296903281	2747822	0	0
DepthKnown_A	296903281	296783766	0	0
RvalidKnown_A	296903281	296783766	0	0
WreadyKnown_A	296903281	296783766	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	2747822	0	0
T1	5897	109	0	0
T2	61832	380	0	0
T3	66526	465	0	0
T4	15642	260	0	0
T12	3669	61	0	0
T13	949	8	0	0
T14	30578	2340	0	0
T15	256124	2048	0	0
T16	2077	42	0	0
T17	240939	38341	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296903281	296783766	0	0
T1	5897	5878	0	0
T2	61832	61749	0	0
T3	66526	66517	0	0
T4	15642	14786	0	0
T12	3669	3612	0	0
T13	949	919	0	0
T14	30578	30533	0	0
T15	256124	256104	0	0
T16	2077	2056	0	0
T17	240939	240935	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0