Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1652175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261076

1

T4

137

T1

3242

T2

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647885	1			T4	385		T1	7685		T2	20
values[0x0]	618072	1			T4	383		T1	7626		T2	5
values[0x1]	647294	1			T4	327		T1	7649		T2	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1280304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632947

1

T4

344

T1

7622

T2

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7266	1			T1	97		T15	11		T19	7
valid_sources[0x01]	7325	1			T1	97		T2	1		T15	11
valid_sources[0x02]	8256	1			T4	12		T1	94		T15	12
valid_sources[0x03]	7145	1			T1	66		T2	1		T15	8
valid_sources[0x04]	8046	1			T4	20		T1	121		T15	11
valid_sources[0x05]	8169	1			T4	31		T1	104		T15	10
valid_sources[0x06]	7377	1			T1	120		T15	11		T18	22
valid_sources[0x07]	7507	1			T1	61		T15	10		T18	32
valid_sources[0x08]	7124	1			T1	79		T2	1		T15	11
valid_sources[0x09]	8053	1			T1	84		T15	11		T19	7
valid_sources[0x0a]	7154	1			T4	5		T1	71		T15	11
valid_sources[0x0b]	7767	1			T1	85		T15	14		T19	5
valid_sources[0x0c]	7002	1			T1	102		T15	11		T19	7
valid_sources[0x0d]	7458	1			T4	12		T1	87		T15	12
valid_sources[0x0e]	6966	1			T1	69		T15	11		T19	4
valid_sources[0x0f]	7359	1			T4	20		T1	87		T3	4
valid_sources[0x10]	7270	1			T1	85		T15	12		T18	11
valid_sources[0x11]	7300	1			T4	6		T1	92		T15	11
valid_sources[0x12]	7137	1			T4	20		T1	72		T15	9
valid_sources[0x13]	7621	1			T1	105		T15	11		T18	22
valid_sources[0x14]	7133	1			T1	81		T15	11		T18	50
valid_sources[0x15]	7246	1			T1	83		T2	1		T3	3
valid_sources[0x16]	7593	1			T4	11		T1	130		T15	11
valid_sources[0x17]	7262	1			T4	12		T1	62		T15	11
valid_sources[0x18]	7556	1			T1	144		T15	10		T18	19
valid_sources[0x19]	7687	1			T1	113		T15	11		T18	45
valid_sources[0x1a]	7079	1			T4	10		T1	94		T15	10
valid_sources[0x1b]	7105	1			T1	97		T15	11		T18	18
valid_sources[0x1c]	7909	1			T1	107		T15	11		T18	20
valid_sources[0x1d]	7397	1			T4	14		T1	66		T15	11
valid_sources[0x1e]	7543	1			T1	134		T15	11		T19	5
valid_sources[0x1f]	7414	1			T1	70		T2	2		T15	11
valid_sources[0x20]	6958	1			T1	71		T15	9		T18	21
valid_sources[0x21]	8058	1			T4	7		T1	129		T15	12
valid_sources[0x22]	7294	1			T1	69		T15	11		T18	37
valid_sources[0x23]	7412	1			T1	70		T15	10		T18	32
valid_sources[0x24]	8023	1			T1	124		T2	1		T15	9
valid_sources[0x25]	7188	1			T1	79		T2	1		T15	8
valid_sources[0x26]	8325	1			T1	68		T15	11		T19	7
valid_sources[0x27]	7326	1			T4	10		T1	66		T15	9
valid_sources[0x28]	7295	1			T4	18		T1	60		T15	11
valid_sources[0x29]	7080	1			T4	10		T1	89		T15	12
valid_sources[0x2a]	7413	1			T1	53		T15	11		T18	1
valid_sources[0x2b]	6960	1			T1	102		T15	11		T18	2
valid_sources[0x2c]	8310	1			T4	13		T1	139		T15	9
valid_sources[0x2d]	7050	1			T1	78		T3	4		T15	11
valid_sources[0x2e]	6959	1			T1	112		T15	11		T18	7
valid_sources[0x2f]	10166	1			T1	69		T15	11		T18	21
valid_sources[0x30]	7950	1			T1	72		T15	11		T18	8
valid_sources[0x31]	8210	1			T1	152		T15	11		T19	5
valid_sources[0x32]	7780	1			T1	78		T15	10		T19	5
valid_sources[0x33]	7366	1			T1	102		T15	11		T18	8
valid_sources[0x34]	7517	1			T1	86		T15	11		T18	26
valid_sources[0x35]	6967	1			T1	91		T2	1		T15	11
valid_sources[0x36]	7323	1			T4	20		T1	69		T15	10
valid_sources[0x37]	6959	1			T1	60		T15	10		T18	5
valid_sources[0x38]	6988	1			T1	84		T2	1		T15	10
valid_sources[0x39]	7320	1			T1	87		T15	10		T18	25
valid_sources[0x3a]	6794	1			T1	86		T3	1		T15	12
valid_sources[0x3b]	7498	1			T1	56		T15	11		T19	7
valid_sources[0x3c]	7617	1			T1	61		T15	11		T19	7
valid_sources[0x3d]	7085	1			T1	99		T2	1		T15	11
valid_sources[0x3e]	7210	1			T1	78		T2	1		T15	12
valid_sources[0x3f]	7516	1			T1	113		T2	1		T15	12
valid_sources[0x40]	8620	1			T1	124		T15	10		T18	3
valid_sources[0x41]	10578	1			T1	97		T15	11		T18	30
valid_sources[0x42]	8084	1			T1	120		T15	11		T19	6
valid_sources[0x43]	7006	1			T4	25		T1	85		T15	10
valid_sources[0x44]	7574	1			T4	7		T1	44		T15	11
valid_sources[0x45]	7214	1			T1	93		T15	10		T19	6
valid_sources[0x46]	6988	1			T1	64		T15	11		T18	48
valid_sources[0x47]	7302	1			T1	72		T15	10		T19	7
valid_sources[0x48]	7424	1			T1	73		T3	1		T15	12
valid_sources[0x49]	7124	1			T1	149		T15	11		T19	7
valid_sources[0x4a]	7263	1			T1	82		T15	9		T18	21
valid_sources[0x4b]	7473	1			T1	128		T15	10		T19	7
valid_sources[0x4c]	7678	1			T4	10		T1	87		T15	10
valid_sources[0x4d]	6781	1			T1	87		T15	12		T18	30
valid_sources[0x4e]	7574	1			T1	79		T15	9		T18	4
valid_sources[0x4f]	7084	1			T1	129		T15	12		T18	13
valid_sources[0x50]	6987	1			T1	114		T2	1		T15	10
valid_sources[0x51]	7751	1			T4	14		T1	53		T15	13
valid_sources[0x52]	7191	1			T4	17		T1	88		T15	11
valid_sources[0x53]	6836	1			T1	124		T15	12		T18	7
valid_sources[0x54]	7050	1			T1	64		T15	12		T18	9
valid_sources[0x55]	7123	1			T4	9		T1	96		T15	12
valid_sources[0x56]	7277	1			T4	18		T1	105		T15	10
valid_sources[0x57]	7254	1			T1	78		T2	1		T15	12
valid_sources[0x58]	7649	1			T1	93		T15	11		T18	2
valid_sources[0x59]	6845	1			T1	75		T15	10		T19	4
valid_sources[0x5a]	9212	1			T1	87		T15	11		T18	56
valid_sources[0x5b]	7241	1			T1	112		T2	1		T15	10
valid_sources[0x5c]	7153	1			T1	98		T15	11		T18	1
valid_sources[0x5d]	7812	1			T1	76		T2	1		T15	11
valid_sources[0x5e]	7765	1			T1	124		T15	11		T18	12
valid_sources[0x5f]	7489	1			T1	109		T15	12		T18	8
valid_sources[0x60]	7615	1			T1	71		T3	3		T15	10
valid_sources[0x61]	8584	1			T1	71		T15	10		T18	45
valid_sources[0x62]	8368	1			T1	112		T15	12		T18	8
valid_sources[0x63]	7825	1			T4	10		T1	113		T15	11
valid_sources[0x64]	7669	1			T1	107		T15	13		T18	26
valid_sources[0x65]	7195	1			T4	11		T1	125		T15	13
valid_sources[0x66]	7539	1			T1	120		T15	10		T19	7
valid_sources[0x67]	7731	1			T1	101		T15	12		T18	22
valid_sources[0x68]	8477	1			T1	47		T15	10		T19	6
valid_sources[0x69]	7465	1			T1	75		T2	1		T3	1
valid_sources[0x6a]	7782	1			T4	10		T1	133		T15	9
valid_sources[0x6b]	7140	1			T1	98		T3	1		T15	12
valid_sources[0x6c]	7451	1			T1	106		T15	10		T19	6
valid_sources[0x6d]	8056	1			T4	14		T1	70		T15	12
valid_sources[0x6e]	6910	1			T4	18		T1	65		T15	10
valid_sources[0x6f]	7530	1			T1	71		T15	11		T18	2
valid_sources[0x70]	7393	1			T1	103		T15	11		T18	1
valid_sources[0x71]	7236	1			T1	106		T15	12		T18	12
valid_sources[0x72]	7956	1			T1	52		T15	11		T18	21
valid_sources[0x73]	7411	1			T1	50		T2	1		T15	11
valid_sources[0x74]	9437	1			T1	77		T15	11		T18	6
valid_sources[0x75]	7305	1			T1	86		T2	1		T15	10
valid_sources[0x76]	7400	1			T4	7		T1	107		T15	11
valid_sources[0x77]	6760	1			T1	123		T15	11		T18	10
valid_sources[0x78]	7310	1			T4	18		T1	129		T15	11
valid_sources[0x79]	7330	1			T4	23		T1	90		T15	9
valid_sources[0x7a]	7123	1			T1	101		T15	13		T19	7
valid_sources[0x7b]	7593	1			T4	15		T1	73		T2	1
valid_sources[0x7c]	7422	1			T1	75		T15	13		T18	2
valid_sources[0x7d]	7561	1			T1	155		T15	11		T18	22
valid_sources[0x7e]	7639	1			T1	81		T15	11		T19	6
valid_sources[0x7f]	7111	1			T4	12		T1	114		T3	1
valid_sources[0x80]	6983	1			T1	67		T15	11		T19	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27571

1

T4

15

T1

306

T2

3

values[0x0]

all_enables

biggest_size

205878

1

T4

112

T1

2618

T2

3

values[0x1]

all_enables

biggest_size

27627

1

T4

10

T1

318

T2

1