Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	324161841	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	324161841	0	0
T1	30065168	809307	0	0
T2	1169168	29981	0	0
T3	840616	14410	0	0
T4	139048	4376	0	0
T15	15156344	1143586	0	0
T16	233072	8011	0	0
T17	7846552	242474	0	0
T18	13498520	2056871	0	0
T19	7331240	1097294	0	0
T20	4138904	89299	0	0
T21	0	66362	0	0
T22	0	46054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	30065168	30053968	0	0
T2	1169168	1167040	0	0
T3	840616	805560	0	0
T4	139048	137480	0	0
T15	15156344	15155896	0	0
T16	233072	230440	0	0
T17	7846552	7842856	0	0
T18	13498520	13498184	0	0
T19	7331240	7331072	0	0
T20	4138904	4135544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	30065168	30053968	0	0
T2	1169168	1167040	0	0
T3	840616	805560	0	0
T4	139048	137480	0	0
T15	15156344	15155896	0	0
T16	233072	230440	0	0
T17	7846552	7842856	0	0
T18	13498520	13498184	0	0
T19	7331240	7331072	0	0
T20	4138904	4135544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	30065168	30053968	0	0
T2	1169168	1167040	0	0
T3	840616	805560	0	0
T4	139048	137480	0	0
T15	15156344	15155896	0	0
T16	233072	230440	0	0
T17	7846552	7842856	0	0
T18	13498520	13498184	0	0
T19	7331240	7331072	0	0
T20	4138904	4135544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	117375632	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	117375632	0	0
T1	536878	282413	0	0
T2	20878	13069	0	0
T3	15011	6425	0	0
T4	2483	1095	0	0
T15	270649	13103	0	0
T16	4162	3664	0	0
T17	140117	138243	0	0
T18	241045	237806	0	0
T19	130915	7125	0	0
T20	73909	38022	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	85787560	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	85787560	0	0
T1	536878	183530	0	0
T2	20878	5707	0	0
T3	15011	1846	0	0
T4	2483	1095	0	0
T15	270649	101648	0	0
T16	4162	2135	0	0
T17	140117	51728	0	0
T18	241045	905020	0	0
T19	130915	541522	0	0
T20	73909	15667	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1373468	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1373468	0	0
T1	536878	7869	0	0
T2	20878	170	0	0
T3	15011	93	0	0
T4	2483	32	0	0
T15	270649	0	0	0
T16	4162	47	0	0
T17	140117	30	0	0
T18	241045	386	0	0
T19	130915	0	0	0
T20	73909	727	0	0
T21	0	27	0	0
T22	0	1044	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3716443	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3716443	0	0
T1	536878	7938	0	0
T2	20878	271	0	0
T3	15011	67	0	0
T4	2483	32	0	0
T15	270649	0	0	0
T16	4162	47	0	0
T17	140117	2718	0	0
T18	241045	28974	0	0
T19	130915	0	0	0
T20	73909	514	0	0
T21	0	2405	0	0
T22	0	2490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1281302	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1281302	0	0
T1	536878	5561	0	0
T2	20878	130	0	0
T3	15011	340	0	0
T4	2483	30	0	0
T15	270649	2279	0	0
T16	4162	46	0	0
T17	140117	9	0	0
T18	241045	425	0	0
T19	130915	0	0	0
T20	73909	745	0	0
T21	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3205781	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3205781	0	0
T1	536878	5918	0	0
T2	20878	118	0	0
T3	15011	128	0	0
T4	2483	30	0	0
T15	270649	185632	0	0
T16	4162	46	0	0
T17	140117	949	0	0
T18	241045	40362	0	0
T19	130915	0	0	0
T20	73909	748	0	0
T21	0	1471	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1356814	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1356814	0	0
T1	536878	9319	0	0
T2	20878	209	0	0
T3	15011	85	0	0
T4	2483	33	0	0
T15	270649	2657	0	0
T16	4162	41	0	0
T17	140117	54	0	0
T18	241045	348	0	0
T19	130915	0	0	0
T20	73909	935	0	0
T21	0	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3578100	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3578100	0	0
T1	536878	9262	0	0
T2	20878	239	0	0
T3	15011	38	0	0
T4	2483	33	0	0
T15	270649	204947	0	0
T16	4162	41	0	0
T17	140117	3192	0	0
T18	241045	28300	0	0
T19	130915	0	0	0
T20	73909	796	0	0
T21	0	6220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1307730	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1307730	0	0
T1	536878	2238	0	0
T2	20878	192	0	0
T3	15011	118	0	0
T4	2483	38	0	0
T15	270649	0	0	0
T16	4162	41	0	0
T17	140117	4	0	0
T18	241045	384	0	0
T19	130915	0	0	0
T20	73909	851	0	0
T21	0	39	0	0
T22	0	4437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2739066	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2739066	0	0
T1	536878	2174	0	0
T2	20878	170	0	0
T3	15011	44	0	0
T4	2483	38	0	0
T15	270649	0	0	0
T16	4162	41	0	0
T17	140117	380	0	0
T18	241045	32150	0	0
T19	130915	0	0	0
T20	73909	602	0	0
T21	0	2243	0	0
T22	0	2912	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1351184	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1351184	0	0
T1	536878	3655	0	0
T2	20878	293	0	0
T3	15011	129	0	0
T4	2483	40	0	0
T15	270649	0	0	0
T16	4162	35	0	0
T17	140117	32	0	0
T18	241045	449	0	0
T19	130915	0	0	0
T20	73909	757	0	0
T21	0	29	0	0
T22	0	1563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2742137	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2742137	0	0
T1	536878	3730	0	0
T2	20878	266	0	0
T3	15011	52	0	0
T4	2483	40	0	0
T15	270649	0	0	0
T16	4162	35	0	0
T17	140117	2849	0	0
T18	241045	37063	0	0
T19	130915	0	0	0
T20	73909	610	0	0
T21	0	694	0	0
T22	0	1068	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1310620	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1310620	0	0
T1	536878	7377	0	0
T2	20878	299	0	0
T3	15011	95	0	0
T4	2483	33	0	0
T15	270649	1257	0	0
T16	4162	50	0	0
T17	140117	19	0	0
T18	241045	368	0	0
T19	130915	919	0	0
T20	73909	801	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2346505	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2346505	0	0
T1	536878	7625	0	0
T2	20878	270	0	0
T3	15011	77	0	0
T4	2483	33	0	0
T15	270649	105571	0	0
T16	4162	50	0	0
T17	140117	241	0	0
T18	241045	31147	0	0
T19	130915	64214	0	0
T20	73909	561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1361441	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1361441	0	0
T1	536878	3685	0	0
T2	20878	286	0	0
T3	15011	117	0	0
T4	2483	43	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	23	0	0
T18	241045	355	0	0
T19	130915	1190	0	0
T20	73909	665	0	0
T21	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3828534	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3828534	0	0
T1	536878	3945	0	0
T2	20878	275	0	0
T3	15011	48	0	0
T4	2483	43	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	1428	0	0
T18	241045	33165	0	0
T19	130915	91479	0	0
T20	73909	551	0	0
T21	0	3402	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1337643	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1337643	0	0
T1	536878	6213	0	0
T2	20878	170	0	0
T3	15011	675	0	0
T4	2483	40	0	0
T15	270649	918	0	0
T16	4162	36	0	0
T17	140117	14	0	0
T18	241045	441	0	0
T19	130915	0	0	0
T20	73909	796	0	0
T21	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3005550	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3005550	0	0
T1	536878	5824	0	0
T2	20878	178	0	0
T3	15011	301	0	0
T4	2483	40	0	0
T15	270649	70991	0	0
T16	4162	36	0	0
T17	140117	525	0	0
T18	241045	39856	0	0
T19	130915	0	0	0
T20	73909	580	0	0
T21	0	1322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1361321	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1361321	0	0
T1	536878	6572	0	0
T2	20878	263	0	0
T3	15011	98	0	0
T4	2483	42	0	0
T15	270649	0	0	0
T16	4162	34	0	0
T17	140117	37	0	0
T18	241045	446	0	0
T19	130915	0	0	0
T20	73909	606	0	0
T21	0	41	0	0
T22	0	3045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3483135	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3483135	0	0
T1	536878	6818	0	0
T2	20878	298	0	0
T3	15011	52	0	0
T4	2483	42	0	0
T15	270649	0	0	0
T16	4162	34	0	0
T17	140117	2532	0	0
T18	241045	31835	0	0
T19	130915	0	0	0
T20	73909	473	0	0
T21	0	2417	0	0
T22	0	1505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1295885	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1295885	0	0
T1	536878	3878	0	0
T2	20878	187	0	0
T3	15011	96	0	0
T4	2483	50	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	44	0	0
T18	241045	439	0	0
T19	130915	0	0	0
T20	73909	841	0	0
T21	0	23	0	0
T22	0	587	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2698163	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2698163	0	0
T1	536878	4077	0	0
T2	20878	219	0	0
T3	15011	22	0	0
T4	2483	50	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	3242	0	0
T18	241045	38463	0	0
T19	130915	0	0	0
T20	73909	586	0	0
T21	0	1559	0	0
T22	0	1965	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1340798	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1340798	0	0
T1	536878	3719	0	0
T2	20878	207	0	0
T3	15011	294	0	0
T4	2483	52	0	0
T15	270649	872	0	0
T16	4162	54	0	0
T17	140117	21	0	0
T18	241045	390	0	0
T19	130915	0	0	0
T20	73909	655	0	0
T21	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3228109	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3228109	0	0
T1	536878	3946	0	0
T2	20878	214	0	0
T3	15011	132	0	0
T4	2483	52	0	0
T15	270649	72669	0	0
T16	4162	54	0	0
T17	140117	1223	0	0
T18	241045	34432	0	0
T19	130915	0	0	0
T20	73909	587	0	0
T21	0	2426	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1378914	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1378914	0	0
T1	536878	8499	0	0
T2	20878	163	0	0
T3	15011	442	0	0
T4	2483	38	0	0
T15	270649	0	0	0
T16	4162	54	0	0
T17	140117	10	0	0
T18	241045	342	0	0
T19	130915	0	0	0
T20	73909	675	0	0
T21	0	23	0	0
T22	0	1582	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3356121	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3356121	0	0
T1	536878	8603	0	0
T2	20878	88	0	0
T3	15011	150	0	0
T4	2483	38	0	0
T15	270649	0	0	0
T16	4162	54	0	0
T17	140117	3	0	0
T18	241045	30652	0	0
T19	130915	0	0	0
T20	73909	604	0	0
T21	0	2553	0	0
T22	0	2532	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1353893	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1353893	0	0
T1	536878	12269	0	0
T2	20878	133	0	0
T3	15011	98	0	0
T4	2483	42	0	0
T15	270649	0	0	0
T16	4162	32	0	0
T17	140117	47	0	0
T18	241045	401	0	0
T19	130915	1006	0	0
T20	73909	752	0	0
T21	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3199988	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3199988	0	0
T1	536878	12225	0	0
T2	20878	169	0	0
T3	15011	28	0	0
T4	2483	42	0	0
T15	270649	0	0	0
T16	4162	32	0	0
T17	140117	3343	0	0
T18	241045	41944	0	0
T19	130915	73203	0	0
T20	73909	602	0	0
T21	0	1532	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1296973	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1296973	0	0
T1	536878	3859	0	0
T2	20878	136	0	0
T3	15011	116	0	0
T4	2483	52	0	0
T15	270649	0	0	0
T16	4162	44	0	0
T17	140117	23	0	0
T18	241045	356	0	0
T19	130915	0	0	0
T20	73909	878	0	0
T21	0	20	0	0
T22	0	1442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2388843	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2388843	0	0
T1	536878	4448	0	0
T2	20878	160	0	0
T3	15011	71	0	0
T4	2483	52	0	0
T15	270649	0	0	0
T16	4162	44	0	0
T17	140117	1826	0	0
T18	241045	30616	0	0
T19	130915	0	0	0
T20	73909	624	0	0
T21	0	2309	0	0
T22	0	2370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1312164	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1312164	0	0
T1	536878	8954	0	0
T2	20878	243	0	0
T3	15011	222	0	0
T4	2483	43	0	0
T15	270649	0	0	0
T16	4162	42	0	0
T17	140117	23	0	0
T18	241045	408	0	0
T19	130915	1057	0	0
T20	73909	758	0	0
T21	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3277250	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3277250	0	0
T1	536878	8932	0	0
T2	20878	297	0	0
T3	15011	63	0	0
T4	2483	43	0	0
T15	270649	0	0	0
T16	4162	42	0	0
T17	140117	2404	0	0
T18	241045	30788	0	0
T19	130915	86568	0	0
T20	73909	539	0	0
T21	0	2723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1304932	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1304932	0	0
T1	536878	4362	0	0
T2	20878	182	0	0
T3	15011	115	0	0
T4	2483	39	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	18	0	0
T18	241045	346	0	0
T19	130915	0	0	0
T20	73909	669	0	0
T21	0	32	0	0
T22	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3463303	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3463303	0	0
T1	536878	4335	0	0
T2	20878	225	0	0
T3	15011	64	0	0
T4	2483	39	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	2725	0	0
T18	241045	27858	0	0
T19	130915	0	0	0
T20	73909	661	0	0
T21	0	2632	0	0
T22	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1350428	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1350428	0	0
T1	536878	11502	0	0
T2	20878	135	0	0
T3	15011	129	0	0
T4	2483	41	0	0
T15	270649	0	0	0
T16	4162	44	0	0
T17	140117	43	0	0
T18	241045	386	0	0
T19	130915	1034	0	0
T20	73909	840	0	0
T21	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2866287	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2866287	0	0
T1	536878	11913	0	0
T2	20878	174	0	0
T3	15011	49	0	0
T4	2483	41	0	0
T15	270649	0	0	0
T16	4162	44	0	0
T17	140117	2636	0	0
T18	241045	36078	0	0
T19	130915	74005	0	0
T20	73909	525	0	0
T21	0	2413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1348006	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1348006	0	0
T1	536878	4986	0	0
T2	20878	112	0	0
T3	15011	135	0	0
T4	2483	23	0	0
T15	270649	0	0	0
T16	4162	38	0	0
T17	140117	14	0	0
T18	241045	349	0	0
T19	130915	1045	0	0
T20	73909	623	0	0
T21	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3431663	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3431663	0	0
T1	536878	5790	0	0
T2	20878	163	0	0
T3	15011	85	0	0
T4	2483	23	0	0
T15	270649	0	0	0
T16	4162	38	0	0
T17	140117	1629	0	0
T18	241045	30925	0	0
T19	130915	80044	0	0
T20	73909	518	0	0
T21	0	921	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1356267	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1356267	0	0
T1	536878	4206	0	0
T2	20878	249	0	0
T3	15011	98	0	0
T4	2483	45	0	0
T15	270649	1137	0	0
T16	4162	35	0	0
T17	140117	47	0	0
T18	241045	415	0	0
T19	130915	0	0	0
T20	73909	807	0	0
T21	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3129067	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3129067	0	0
T1	536878	4383	0	0
T2	20878	257	0	0
T3	15011	18	0	0
T4	2483	45	0	0
T15	270649	89426	0	0
T16	4162	35	0	0
T17	140117	3266	0	0
T18	241045	34020	0	0
T19	130915	0	0	0
T20	73909	583	0	0
T21	0	2446	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1350538	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1350538	0	0
T1	536878	4303	0	0
T2	20878	216	0	0
T3	15011	117	0	0
T4	2483	28	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	53	0	0
T18	241045	461	0	0
T19	130915	0	0	0
T20	73909	656	0	0
T21	0	79	0	0
T22	0	2089	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2581714	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2581714	0	0
T1	536878	4205	0	0
T2	20878	202	0	0
T3	15011	43	0	0
T4	2483	28	0	0
T15	270649	0	0	0
T16	4162	39	0	0
T17	140117	2430	0	0
T18	241045	37351	0	0
T19	130915	0	0	0
T20	73909	544	0	0
T21	0	5304	0	0
T22	0	281	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1341956	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1341956	0	0
T1	536878	4138	0	0
T2	20878	136	0	0
T3	15011	106	0	0
T4	2483	50	0	0
T15	270649	0	0	0
T16	4162	33	0	0
T17	140117	24	0	0
T18	241045	491	0	0
T19	130915	0	0	0
T20	73909	768	0	0
T21	0	31	0	0
T22	0	1755	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3076460	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3076460	0	0
T1	536878	4150	0	0
T2	20878	125	0	0
T3	15011	17	0	0
T4	2483	50	0	0
T15	270649	0	0	0
T16	4162	33	0	0
T17	140117	1697	0	0
T18	241045	34693	0	0
T19	130915	0	0	0
T20	73909	538	0	0
T21	0	2003	0	0
T22	0	518	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1343194	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1343194	0	0
T1	536878	5251	0	0
T2	20878	268	0	0
T3	15011	71	0	0
T4	2483	47	0	0
T15	270649	0	0	0
T16	4162	33	0	0
T17	140117	8	0	0
T18	241045	426	0	0
T19	130915	0	0	0
T20	73909	638	0	0
T21	0	21	0	0
T22	0	2370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	2618909	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	2618909	0	0
T1	536878	6077	0	0
T2	20878	218	0	0
T3	15011	15	0	0
T4	2483	47	0	0
T15	270649	0	0	0
T16	4162	33	0	0
T17	140117	354	0	0
T18	241045	41139	0	0
T19	130915	0	0	0
T20	73909	508	0	0
T21	0	1885	0	0
T22	0	1803	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1360231	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1360231	0	0
T1	536878	7259	0	0
T2	20878	240	0	0
T3	15011	150	0	0
T4	2483	47	0	0
T15	270649	0	0	0
T16	4162	34	0	0
T17	140117	24	0	0
T18	241045	352	0	0
T19	130915	0	0	0
T20	73909	553	0	0
T21	0	57	0	0
T22	0	1112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3017058	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3017058	0	0
T1	536878	8268	0	0
T2	20878	249	0	0
T3	15011	89	0	0
T4	2483	47	0	0
T15	270649	0	0	0
T16	4162	34	0	0
T17	140117	698	0	0
T18	241045	30032	0	0
T19	130915	0	0	0
T20	73909	429	0	0
T21	0	6014	0	0
T22	0	1301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1395743	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1395743	0	0
T1	536878	12851	0	0
T2	20878	284	0	0
T3	15011	91	0	0
T4	2483	34	0	0
T15	270649	0	0	0
T16	4162	34	0	0
T17	140117	34	0	0
T18	241045	349	0	0
T19	130915	0	0	0
T20	73909	923	0	0
T21	0	35	0	0
T22	0	1644	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3673156	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3673156	0	0
T1	536878	15400	0	0
T2	20878	250	0	0
T3	15011	37	0	0
T4	2483	34	0	0
T15	270649	0	0	0
T16	4162	34	0	0
T17	140117	1480	0	0
T18	241045	22764	0	0
T19	130915	0	0	0
T20	73909	714	0	0
T21	0	3117	0	0
T22	0	1105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1298335	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1298335	0	0
T1	536878	4320	0	0
T2	20878	168	0	0
T3	15011	86	0	0
T4	2483	50	0	0
T15	270649	2532	0	0
T16	4162	63	0	0
T17	140117	69	0	0
T18	241045	364	0	0
T19	130915	874	0	0
T20	73909	629	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3588131	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3588131	0	0
T1	536878	4866	0	0
T2	20878	202	0	0
T3	15011	19	0	0
T4	2483	50	0	0
T15	270649	192284	0	0
T16	4162	63	0	0
T17	140117	4692	0	0
T18	241045	31295	0	0
T19	130915	72009	0	0
T20	73909	593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1295378	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1295378	0	0
T1	536878	5266	0	0
T2	20878	229	0	0
T3	15011	140	0	0
T4	2483	41	0	0
T15	270649	1073	0	0
T16	4162	40	0	0
T17	140117	20	0	0
T18	241045	354	0	0
T19	130915	0	0	0
T20	73909	683	0	0
T21	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3567013	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3567013	0	0
T1	536878	5718	0	0
T2	20878	192	0	0
T3	15011	31	0	0
T4	2483	41	0	0
T15	270649	94590	0	0
T16	4162	40	0	0
T17	140117	820	0	0
T18	241045	35966	0	0
T19	130915	0	0	0
T20	73909	514	0	0
T21	0	2744	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	1338645	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	1338645	0	0
T1	536878	5416	0	0
T2	20878	198	0	0
T3	15011	110	0	0
T4	2483	40	0	0
T15	270649	0	0	0
T16	4162	40	0	0
T17	140117	31	0	0
T18	241045	372	0	0
T19	130915	0	0	0
T20	73909	712	0	0
T21	0	21	0	0
T22	0	1696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	291325723	3088360	0	0
DepthKnown_A	291325723	291204839	0	0
RvalidKnown_A	291325723	291204839	0	0
WreadyKnown_A	291325723	291204839	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	3088360	0	0
T1	536878	5267	0	0
T2	20878	218	0	0
T3	15011	33	0	0
T4	2483	40	0	0
T15	270649	0	0	0
T16	4162	40	0	0
T17	140117	2446	0	0
T18	241045	31574	0	0
T19	130915	0	0	0
T20	73909	563	0	0
T21	0	2821	0	0
T22	0	1817	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291325723	291204839	0	0
T1	536878	536678	0	0
T2	20878	20840	0	0
T3	15011	14385	0	0
T4	2483	2455	0	0
T15	270649	270641	0	0
T16	4162	4115	0	0
T17	140117	140051	0	0
T18	241045	241039	0	0
T19	130915	130912	0	0
T20	73909	73849	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0