Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1644398	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259163

1

T1

78

T2

94

T3

113

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	643822	1			T1	380		T2	233		T3	291
values[0x0]	614876	1			T1	74		T2	228		T3	287
values[0x1]	644863	1			T1	383		T2	214		T3	302

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1274488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

629073

1

T1

309

T2

211

T3

283

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7045	1			T1	4		T3	1		T13	6
valid_sources[0x01]	6911	1			T1	2		T2	3		T13	7
valid_sources[0x02]	7356	1			T1	2		T13	2		T17	22
valid_sources[0x03]	6966	1			T2	3		T3	10		T13	5
valid_sources[0x04]	7322	1			T1	4		T2	6		T13	3
valid_sources[0x05]	7387	1			T1	1		T15	7		T13	9
valid_sources[0x06]	7372	1			T1	1		T2	1		T13	4
valid_sources[0x07]	7545	1			T1	2		T2	20		T13	10
valid_sources[0x08]	7380	1			T1	4		T15	5		T16	2
valid_sources[0x09]	7886	1			T1	9		T2	5		T13	8
valid_sources[0x0a]	7029	1			T1	2		T2	2		T3	8
valid_sources[0x0b]	7191	1			T1	1		T13	5		T17	23
valid_sources[0x0c]	7278	1			T1	1		T2	1		T13	11
valid_sources[0x0d]	7515	1			T1	1		T13	6		T17	21
valid_sources[0x0e]	7196	1			T1	3		T13	7		T17	6
valid_sources[0x0f]	7115	1			T1	5		T2	9		T13	5
valid_sources[0x10]	7443	1			T1	3		T2	5		T13	3
valid_sources[0x11]	7276	1			T1	5		T2	5		T13	8
valid_sources[0x12]	7746	1			T1	2		T2	5		T13	9
valid_sources[0x13]	7546	1			T1	1		T2	1		T13	7
valid_sources[0x14]	7220	1			T1	3		T2	5		T13	10
valid_sources[0x15]	7317	1			T1	2		T2	5		T13	5
valid_sources[0x16]	7468	1			T1	2		T13	6		T17	19
valid_sources[0x17]	7087	1			T1	4		T2	9		T15	8
valid_sources[0x18]	7009	1			T2	5		T13	10		T17	13
valid_sources[0x19]	6896	1			T1	4		T13	7		T17	18
valid_sources[0x1a]	8232	1			T1	3		T13	5		T17	17
valid_sources[0x1b]	7172	1			T1	10		T13	8		T17	6
valid_sources[0x1c]	7711	1			T1	7		T2	5		T13	8
valid_sources[0x1d]	7718	1			T1	1		T2	4		T15	7
valid_sources[0x1e]	7381	1			T1	2		T2	1		T15	19
valid_sources[0x1f]	8081	1			T1	3		T2	5		T13	9
valid_sources[0x20]	7976	1			T1	1		T2	1		T3	7
valid_sources[0x21]	7199	1			T1	1		T2	2		T3	3
valid_sources[0x22]	7386	1			T1	2		T3	96		T13	9
valid_sources[0x23]	7218	1			T1	5		T13	8		T17	6
valid_sources[0x24]	8804	1			T1	2		T13	6		T17	27
valid_sources[0x25]	6817	1			T1	4		T2	2		T13	5
valid_sources[0x26]	7490	1			T1	3		T2	1		T13	4
valid_sources[0x27]	7157	1			T1	4		T2	1		T3	9
valid_sources[0x28]	8190	1			T1	3		T2	7		T3	69
valid_sources[0x29]	6532	1			T13	10		T17	43		T18	5
valid_sources[0x2a]	7476	1			T1	1		T13	5		T17	21
valid_sources[0x2b]	8628	1			T1	3		T13	8		T17	33
valid_sources[0x2c]	7076	1			T1	3		T2	1		T13	9
valid_sources[0x2d]	8933	1			T13	10		T17	15		T14	62
valid_sources[0x2e]	7279	1			T1	5		T2	6		T13	3
valid_sources[0x2f]	7217	1			T1	3		T13	6		T17	13
valid_sources[0x30]	6279	1			T1	5		T13	6		T17	15
valid_sources[0x31]	7469	1			T1	6		T13	6		T17	6
valid_sources[0x32]	7659	1			T2	2		T13	3		T17	12
valid_sources[0x33]	7203	1			T1	3		T13	8		T17	13
valid_sources[0x34]	6934	1			T1	1		T13	5		T17	24
valid_sources[0x35]	7279	1			T1	4		T2	3		T13	7
valid_sources[0x36]	7109	1			T1	4		T2	1		T13	6
valid_sources[0x37]	7013	1			T1	3		T13	10		T17	10
valid_sources[0x38]	7033	1			T1	3		T3	18		T13	10
valid_sources[0x39]	7740	1			T13	18		T17	16		T18	12
valid_sources[0x3a]	7666	1			T1	3		T2	13		T3	5
valid_sources[0x3b]	7341	1			T1	4		T13	8		T17	31
valid_sources[0x3c]	7307	1			T1	2		T2	11		T3	38
valid_sources[0x3d]	7022	1			T1	1		T2	7		T13	11
valid_sources[0x3e]	7712	1			T1	2		T2	2		T3	85
valid_sources[0x3f]	7596	1			T1	1		T13	6		T17	20
valid_sources[0x40]	7847	1			T1	5		T2	8		T13	4
valid_sources[0x41]	8543	1			T1	7		T2	7		T13	9
valid_sources[0x42]	7411	1			T1	3		T2	6		T13	3
valid_sources[0x43]	8817	1			T1	5		T2	8		T13	10
valid_sources[0x44]	7853	1			T1	6		T2	1		T13	13
valid_sources[0x45]	6852	1			T1	2		T13	12		T17	12
valid_sources[0x46]	7559	1			T1	2		T13	5		T17	16
valid_sources[0x47]	7092	1			T1	3		T15	5		T13	4
valid_sources[0x48]	6975	1			T1	4		T13	14		T17	6
valid_sources[0x49]	8113	1			T1	5		T2	4		T13	10
valid_sources[0x4a]	7249	1			T1	5		T13	12		T17	18
valid_sources[0x4b]	7669	1			T1	6		T2	1		T13	5
valid_sources[0x4c]	8407	1			T1	1		T2	4		T13	6
valid_sources[0x4d]	7353	1			T1	3		T15	10		T13	5
valid_sources[0x4e]	7315	1			T1	3		T13	11		T17	13
valid_sources[0x4f]	7022	1			T1	3		T2	7		T13	7
valid_sources[0x50]	7034	1			T1	4		T3	7		T13	3
valid_sources[0x51]	6892	1			T1	4		T2	4		T13	3
valid_sources[0x52]	6661	1			T1	3		T13	6		T17	18
valid_sources[0x53]	7088	1			T1	2		T13	5		T17	6
valid_sources[0x54]	7323	1			T1	3		T13	5		T17	10
valid_sources[0x55]	7581	1			T1	4		T13	8		T17	10
valid_sources[0x56]	8062	1			T1	3		T2	8		T13	4
valid_sources[0x57]	8659	1			T1	11		T13	3		T17	13
valid_sources[0x58]	7721	1			T1	3		T2	3		T13	11
valid_sources[0x59]	9222	1			T1	3		T2	6		T13	11
valid_sources[0x5a]	8765	1			T1	4		T13	11		T17	18
valid_sources[0x5b]	7836	1			T1	3		T17	11		T14	54
valid_sources[0x5c]	6944	1			T1	1		T2	4		T15	12
valid_sources[0x5d]	7570	1			T1	3		T2	2		T13	6
valid_sources[0x5e]	7307	1			T1	4		T3	53		T13	2
valid_sources[0x5f]	7501	1			T1	3		T13	8		T17	17
valid_sources[0x60]	7161	1			T1	4		T2	5		T13	12
valid_sources[0x61]	7171	1			T1	3		T13	8		T17	18
valid_sources[0x62]	7511	1			T1	3		T15	11		T13	2
valid_sources[0x63]	7437	1			T1	2		T13	9		T17	19
valid_sources[0x64]	7966	1			T1	4		T13	3		T17	4
valid_sources[0x65]	7907	1			T1	8		T2	4		T13	10
valid_sources[0x66]	7360	1			T1	1		T2	1		T13	7
valid_sources[0x67]	7421	1			T1	2		T13	4		T17	10
valid_sources[0x68]	7352	1			T1	8		T2	6		T13	7
valid_sources[0x69]	7609	1			T1	2		T2	9		T13	8
valid_sources[0x6a]	8177	1			T1	2		T13	9		T17	18
valid_sources[0x6b]	7203	1			T1	4		T3	16		T13	10
valid_sources[0x6c]	7094	1			T1	9		T2	8		T13	13
valid_sources[0x6d]	6943	1			T1	2		T13	7		T17	15
valid_sources[0x6e]	7186	1			T1	7		T2	1		T13	12
valid_sources[0x6f]	7354	1			T1	7		T2	2		T13	5
valid_sources[0x70]	7299	1			T1	3		T13	7		T17	24
valid_sources[0x71]	8266	1			T1	4		T13	2		T17	25
valid_sources[0x72]	7737	1			T1	3		T13	6		T17	6
valid_sources[0x73]	7556	1			T1	4		T13	5		T17	13
valid_sources[0x74]	6854	1			T1	4		T13	8		T17	10
valid_sources[0x75]	7153	1			T1	2		T3	70		T15	7
valid_sources[0x76]	7279	1			T1	1		T13	9		T17	17
valid_sources[0x77]	6824	1			T1	1		T2	4		T3	9
valid_sources[0x78]	7218	1			T1	3		T13	9		T17	8
valid_sources[0x79]	7398	1			T1	7		T13	12		T17	16
valid_sources[0x7a]	7924	1			T1	5		T16	3		T13	13
valid_sources[0x7b]	7312	1			T1	5		T13	3		T17	16
valid_sources[0x7c]	7214	1			T1	4		T13	5		T17	12
valid_sources[0x7d]	6908	1			T1	5		T2	3		T13	3
valid_sources[0x7e]	6990	1			T2	3		T13	5		T17	13
valid_sources[0x7f]	7368	1			T1	6		T2	8		T13	4
valid_sources[0x80]	7213	1			T1	3		T13	12		T17	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27275

1

T1

29

T2

11

T3

15

values[0x0]

all_enables

biggest_size

204456

1

T1

31

T2

77

T3

87

values[0x1]

all_enables

biggest_size

27432

1

T1

18

T2

6

T3

11