Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	356401328	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	356401328	0	0
T1	21645064	394518	0	0
T2	30996560	859502	0	0
T3	1259888	23629	0	0
T13	3869768	167495	0	0
T14	20241200	507217	0	0
T15	30800	466	0	0
T16	47152	645	0	0
T17	3845016	78054	0	0
T18	1303736	19452	0	0
T19	552496	22660	0	0
T20	0	1180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21645064	21615048	0	0
T2	30996560	30992696	0	0
T3	1259888	1256640	0	0
T13	3869768	3785208	0	0
T14	20241200	20203792	0	0
T15	30800	28840	0	0
T16	47152	42056	0	0
T17	3845016	3843168	0	0
T18	1303736	1299592	0	0
T19	552496	539616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21645064	21615048	0	0
T2	30996560	30992696	0	0
T3	1259888	1256640	0	0
T13	3869768	3785208	0	0
T14	20241200	20203792	0	0
T15	30800	28840	0	0
T16	47152	42056	0	0
T17	3845016	3843168	0	0
T18	1303736	1299592	0	0
T19	552496	539616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21645064	21615048	0	0
T2	30996560	30992696	0	0
T3	1259888	1256640	0	0
T13	3869768	3785208	0	0
T14	20241200	20203792	0	0
T15	30800	28840	0	0
T16	47152	42056	0	0
T17	3845016	3843168	0	0
T18	1303736	1299592	0	0
T19	552496	539616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	137328234	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	137328234	0	0
T1	386519	164739	0	0
T2	553510	543554	0	0
T3	22498	10674	0	0
T13	69103	60450	0	0
T14	361450	212863	0	0
T15	550	117	0	0
T16	842	249	0	0
T17	68661	23994	0	0
T18	23281	4832	0	0
T19	9866	8972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	86817635	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	86817635	0	0
T1	386519	56654	0	0
T2	553510	156472	0	0
T3	22498	2898	0	0
T13	69103	38202	0	0
T14	361450	114081	0	0
T15	550	117	0	0
T16	842	132	0	0
T17	68661	15033	0	0
T18	23281	4897	0	0
T19	9866	4792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1676288	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1676288	0	0
T1	386519	2972	0	0
T2	553510	113	0	0
T3	22498	291	0	0
T13	69103	1489	0	0
T14	361450	2467	0	0
T15	550	4	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	298	0	0
T19	9866	108	0	0
T20	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3280471	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3280471	0	0
T1	386519	1151	0	0
T2	553510	6967	0	0
T3	22498	117	0	0
T13	69103	1488	0	0
T14	361450	2531	0	0
T15	550	4	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	260	0	0
T19	9866	108	0	0
T20	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1675398	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1675398	0	0
T1	386519	4026	0	0
T2	553510	100	0	0
T3	22498	252	0	0
T13	69103	1007	0	0
T14	361450	3219	0	0
T15	550	1	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	251	0	0
T19	9866	121	0	0
T20	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2811981	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2811981	0	0
T1	386519	2016	0	0
T2	553510	6708	0	0
T3	22498	81	0	0
T13	69103	1007	0	0
T14	361450	3401	0	0
T15	550	1	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	243	0	0
T19	9866	121	0	0
T20	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1676115	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1676115	0	0
T1	386519	3226	0	0
T2	553510	153	0	0
T3	22498	329	0	0
T13	69103	1017	0	0
T14	361450	5019	0	0
T15	550	3	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	205	0	0
T19	9866	356	0	0
T20	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3119431	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3119431	0	0
T1	386519	1321	0	0
T2	553510	8112	0	0
T3	22498	128	0	0
T13	69103	1017	0	0
T14	361450	5326	0	0
T15	550	3	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	167	0	0
T19	9866	356	0	0
T20	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1695315	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1695315	0	0
T1	386519	2799	0	0
T2	553510	166	0	0
T3	22498	275	0	0
T13	69103	1241	0	0
T14	361450	2577	0	0
T15	550	5	0	0
T16	842	5	0	0
T17	68661	0	0	0
T18	23281	213	0	0
T19	9866	110	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3138576	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3138576	0	0
T1	386519	1136	0	0
T2	553510	7582	0	0
T3	22498	112	0	0
T13	69103	1241	0	0
T14	361450	2634	0	0
T15	550	5	0	0
T16	842	5	0	0
T17	68661	0	0	0
T18	23281	252	0	0
T19	9866	109	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1719062	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1719062	0	0
T1	386519	4479	0	0
T2	553510	147	0	0
T3	22498	289	0	0
T13	69103	1008	0	0
T14	361450	4655	0	0
T15	550	2	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	125	0	0
T19	9866	91	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3856444	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3856444	0	0
T1	386519	1866	0	0
T2	553510	6385	0	0
T3	22498	105	0	0
T13	69103	1008	0	0
T14	361450	4889	0	0
T15	550	2	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	119	0	0
T19	9866	91	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1711636	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1711636	0	0
T1	386519	2627	0	0
T2	553510	121	0	0
T3	22498	271	0	0
T13	69103	1230	0	0
T14	361450	2346	0	0
T15	550	4	0	0
T16	842	9	0	0
T17	68661	0	0	0
T18	23281	164	0	0
T19	9866	127	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2708512	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2708512	0	0
T1	386519	1085	0	0
T2	553510	6783	0	0
T3	22498	119	0	0
T13	69103	1230	0	0
T14	361450	2315	0	0
T15	550	4	0	0
T16	842	9	0	0
T17	68661	0	0	0
T18	23281	147	0	0
T19	9866	127	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1694355	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1694355	0	0
T1	386519	2806	0	0
T2	553510	84	0	0
T3	22498	291	0	0
T13	69103	1497	0	0
T14	361450	2336	0	0
T15	550	5	0	0
T16	842	4	0	0
T17	68661	1287	0	0
T18	23281	213	0	0
T19	9866	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3660057	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3660057	0	0
T1	386519	1132	0	0
T2	553510	3740	0	0
T3	22498	146	0	0
T13	69103	1497	0	0
T14	361450	2581	0	0
T15	550	5	0	0
T16	842	4	0	0
T17	68661	807	0	0
T18	23281	251	0	0
T19	9866	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1713654	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1713654	0	0
T1	386519	4603	0	0
T2	553510	146	0	0
T3	22498	200	0	0
T13	69103	1202	0	0
T14	361450	2515	0	0
T15	550	7	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	227	0	0
T19	9866	116	0	0
T20	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3535276	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3535276	0	0
T1	386519	2063	0	0
T2	553510	6057	0	0
T3	22498	79	0	0
T13	69103	1202	0	0
T14	361450	2682	0	0
T15	550	7	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	222	0	0
T19	9866	116	0	0
T20	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1685795	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1685795	0	0
T1	386519	5702	0	0
T2	553510	99	0	0
T3	22498	270	0	0
T13	69103	1700	0	0
T14	361450	2718	0	0
T15	550	4	0	0
T16	842	3	0	0
T17	68661	1947	0	0
T18	23281	205	0	0
T19	9866	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3296301	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3296301	0	0
T1	386519	2862	0	0
T2	553510	4761	0	0
T3	22498	117	0	0
T13	69103	1699	0	0
T14	361450	2998	0	0
T15	550	4	0	0
T16	842	3	0	0
T17	68661	896	0	0
T18	23281	191	0	0
T19	9866	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1744583	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1744583	0	0
T1	386519	5140	0	0
T2	553510	121	0	0
T3	22498	166	0	0
T13	69103	733	0	0
T14	361450	2656	0	0
T15	550	2	0	0
T16	842	4	0	0
T17	68661	0	0	0
T18	23281	118	0	0
T19	9866	119	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3049104	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3049104	0	0
T1	386519	2993	0	0
T2	553510	5725	0	0
T3	22498	86	0	0
T13	69103	733	0	0
T14	361450	2724	0	0
T15	550	2	0	0
T16	842	4	0	0
T17	68661	0	0	0
T18	23281	168	0	0
T19	9866	119	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1780587	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1780587	0	0
T1	386519	6551	0	0
T2	553510	135	0	0
T3	22498	217	0	0
T13	69103	1899	0	0
T14	361450	2527	0	0
T15	550	3	0	0
T16	842	7	0	0
T17	68661	0	0	0
T18	23281	117	0	0
T19	9866	430	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3855906	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3855906	0	0
T1	386519	3207	0	0
T2	553510	6224	0	0
T3	22498	86	0	0
T13	69103	1899	0	0
T14	361450	2734	0	0
T15	550	3	0	0
T16	842	7	0	0
T17	68661	0	0	0
T18	23281	87	0	0
T19	9866	430	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1746356	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1746356	0	0
T1	386519	4770	0	0
T2	553510	52	0	0
T3	22498	262	0	0
T13	69103	1540	0	0
T14	361450	2396	0	0
T15	550	2	0	0
T16	842	5	0	0
T17	68661	1359	0	0
T18	23281	158	0	0
T19	9866	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3321587	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3321587	0	0
T1	386519	2410	0	0
T2	553510	3830	0	0
T3	22498	121	0	0
T13	69103	1539	0	0
T14	361450	2506	0	0
T15	550	2	0	0
T16	842	5	0	0
T17	68661	1155	0	0
T18	23281	184	0	0
T19	9866	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1723950	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1723950	0	0
T1	386519	2832	0	0
T2	553510	123	0	0
T3	22498	242	0	0
T13	69103	1775	0	0
T14	361450	4819	0	0
T15	550	2	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	177	0	0
T19	9866	118	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3862620	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3862620	0	0
T1	386519	1122	0	0
T2	553510	7091	0	0
T3	22498	91	0	0
T13	69103	1773	0	0
T14	361450	4534	0	0
T15	550	2	0	0
T16	842	6	0	0
T17	68661	0	0	0
T18	23281	94	0	0
T19	9866	118	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1701205	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1701205	0	0
T1	386519	2700	0	0
T2	553510	53	0	0
T3	22498	302	0	0
T13	69103	1049	0	0
T14	361450	2818	0	0
T15	550	5	0	0
T16	842	4	0	0
T17	68661	0	0	0
T18	23281	131	0	0
T19	9866	596	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3509431	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3509431	0	0
T1	386519	1032	0	0
T2	553510	4225	0	0
T3	22498	101	0	0
T13	69103	1049	0	0
T14	361450	2754	0	0
T15	550	5	0	0
T16	842	4	0	0
T17	68661	0	0	0
T18	23281	202	0	0
T19	9866	596	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1716612	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1716612	0	0
T1	386519	4785	0	0
T2	553510	110	0	0
T3	22498	252	0	0
T13	69103	1665	0	0
T14	361450	2671	0	0
T15	550	6	0	0
T16	842	4	0	0
T17	68661	7056	0	0
T18	23281	245	0	0
T19	9866	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3009019	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3009019	0	0
T1	386519	2061	0	0
T2	553510	8042	0	0
T3	22498	101	0	0
T13	69103	1665	0	0
T14	361450	2780	0	0
T15	550	6	0	0
T16	842	4	0	0
T17	68661	5262	0	0
T18	23281	200	0	0
T19	9866	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1723418	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1723418	0	0
T1	386519	7061	0	0
T2	553510	139	0	0
T3	22498	207	0	0
T13	69103	853	0	0
T14	361450	2550	0	0
T15	550	4	0	0
T16	842	6	0	0
T17	68661	4279	0	0
T18	23281	222	0	0
T19	9866	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2964348	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2964348	0	0
T1	386519	3616	0	0
T2	553510	6971	0	0
T3	22498	93	0	0
T13	69103	852	0	0
T14	361450	2760	0	0
T15	550	4	0	0
T16	842	6	0	0
T17	68661	2807	0	0
T18	23281	168	0	0
T19	9866	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1695224	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1695224	0	0
T1	386519	5161	0	0
T2	553510	62	0	0
T3	22498	267	0	0
T13	69103	1613	0	0
T14	361450	4898	0	0
T15	550	5	0	0
T16	842	2	0	0
T17	68661	1697	0	0
T18	23281	152	0	0
T19	9866	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3138941	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3138941	0	0
T1	386519	2068	0	0
T2	553510	2961	0	0
T3	22498	90	0	0
T13	69103	1613	0	0
T14	361450	5246	0	0
T15	550	5	0	0
T16	842	2	0	0
T17	68661	830	0	0
T18	23281	234	0	0
T19	9866	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1697804	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1697804	0	0
T1	386519	2574	0	0
T2	553510	81	0	0
T3	22498	202	0	0
T13	69103	722	0	0
T14	361450	2431	0	0
T15	550	5	0	0
T16	842	1	0	0
T17	68661	0	0	0
T18	23281	171	0	0
T19	9866	95	0	0
T20	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2760667	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2760667	0	0
T1	386519	915	0	0
T2	553510	2252	0	0
T3	22498	98	0	0
T13	69103	720	0	0
T14	361450	2651	0	0
T15	550	5	0	0
T16	842	1	0	0
T17	68661	0	0	0
T18	23281	201	0	0
T19	9866	95	0	0
T20	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1751893	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1751893	0	0
T1	386519	4492	0	0
T2	553510	101	0	0
T3	22498	291	0	0
T13	69103	1302	0	0
T14	361450	2599	0	0
T15	550	3	0	0
T16	842	8	0	0
T17	68661	2526	0	0
T18	23281	190	0	0
T19	9866	314	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2319642	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2319642	0	0
T1	386519	1771	0	0
T2	553510	6298	0	0
T3	22498	134	0	0
T13	69103	1301	0	0
T14	361450	2860	0	0
T15	550	3	0	0
T16	842	8	0	0
T17	68661	1090	0	0
T18	23281	230	0	0
T19	9866	314	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1774480	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1774480	0	0
T1	386519	6526	0	0
T2	553510	129	0	0
T3	22498	239	0	0
T13	69103	881	0	0
T14	361450	2689	0	0
T15	550	2	0	0
T16	842	10	0	0
T17	68661	1545	0	0
T18	23281	164	0	0
T19	9866	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3068199	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3068199	0	0
T1	386519	3375	0	0
T2	553510	5546	0	0
T3	22498	88	0	0
T13	69103	880	0	0
T14	361450	2819	0	0
T15	550	2	0	0
T16	842	10	0	0
T17	68661	1167	0	0
T18	23281	188	0	0
T19	9866	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1717102	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1717102	0	0
T1	386519	3858	0	0
T2	553510	87	0	0
T3	22498	162	0	0
T13	69103	1418	0	0
T14	361450	2857	0	0
T15	550	2	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	170	0	0
T19	9866	120	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3079156	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3079156	0	0
T1	386519	2146	0	0
T2	553510	5215	0	0
T3	22498	73	0	0
T13	69103	1418	0	0
T14	361450	2988	0	0
T15	550	2	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	182	0	0
T19	9866	120	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1740953	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1740953	0	0
T1	386519	10305	0	0
T2	553510	59	0	0
T3	22498	300	0	0
T13	69103	969	0	0
T14	361450	2726	0	0
T15	550	5	0	0
T16	842	6	0	0
T17	68661	2298	0	0
T18	23281	146	0	0
T19	9866	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3269246	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3269246	0	0
T1	386519	4370	0	0
T2	553510	2743	0	0
T3	22498	133	0	0
T13	69103	969	0	0
T14	361450	2701	0	0
T15	550	5	0	0
T16	842	6	0	0
T17	68661	1019	0	0
T18	23281	134	0	0
T19	9866	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1667436	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1667436	0	0
T1	386519	4796	0	0
T2	553510	170	0	0
T3	22498	346	0	0
T13	69103	1309	0	0
T14	361450	4272	0	0
T15	550	6	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	177	0	0
T19	9866	129	0	0
T20	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2853776	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2853776	0	0
T1	386519	2229	0	0
T2	553510	8769	0	0
T3	22498	88	0	0
T13	69103	1308	0	0
T14	361450	4694	0	0
T15	550	6	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	204	0	0
T19	9866	129	0	0
T20	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1714897	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1714897	0	0
T1	386519	6328	0	0
T2	553510	93	0	0
T3	22498	386	0	0
T13	69103	1284	0	0
T14	361450	5834	0	0
T15	550	7	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	176	0	0
T19	9866	102	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2723296	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2723296	0	0
T1	386519	2803	0	0
T2	553510	3982	0	0
T3	22498	129	0	0
T13	69103	1282	0	0
T14	361450	6053	0	0
T15	550	7	0	0
T16	842	2	0	0
T17	68661	0	0	0
T18	23281	132	0	0
T19	9866	102	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1757022	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1757022	0	0
T1	386519	2600	0	0
T2	553510	107	0	0
T3	22498	355	0	0
T13	69103	956	0	0
T14	361450	4614	0	0
T15	550	5	0	0
T16	842	3	0	0
T17	68661	0	0	0
T18	23281	180	0	0
T19	9866	235	0	0
T20	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3582973	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3582973	0	0
T1	386519	1130	0	0
T2	553510	5332	0	0
T3	22498	132	0	0
T13	69103	956	0	0
T14	361450	4521	0	0
T15	550	5	0	0
T16	842	3	0	0
T17	68661	0	0	0
T18	23281	157	0	0
T19	9866	235	0	0
T20	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1719586	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1719586	0	0
T1	386519	2613	0	0
T2	553510	147	0	0
T3	22498	215	0	0
T13	69103	2062	0	0
T14	361450	4521	0	0
T15	550	7	0	0
T16	842	10	0	0
T17	68661	0	0	0
T18	23281	104	0	0
T19	9866	126	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	3315565	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	3315565	0	0
T1	386519	1068	0	0
T2	553510	8560	0	0
T3	22498	106	0	0
T13	69103	2062	0	0
T14	361450	4657	0	0
T15	550	7	0	0
T16	842	10	0	0
T17	68661	0	0	0
T18	23281	98	0	0
T19	9866	126	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	1672055	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	1672055	0	0
T1	386519	2713	0	0
T2	553510	106	0	0
T3	22498	280	0	0
T13	69103	1007	0	0
T14	361450	2541	0	0
T15	550	10	0	0
T16	842	7	0	0
T17	68661	0	0	0
T18	23281	130	0	0
T19	9866	100	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322496522	2872153	0	0
DepthKnown_A	322496522	322377238	0	0
RvalidKnown_A	322496522	322377238	0	0
WreadyKnown_A	322496522	322377238	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	2872153	0	0
T1	386519	1132	0	0
T2	553510	5611	0	0
T3	22498	144	0	0
T13	69103	1007	0	0
T14	361450	2663	0	0
T15	550	10	0	0
T16	842	7	0	0
T17	68661	0	0	0
T18	23281	179	0	0
T19	9866	100	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322496522	322377238	0	0
T1	386519	385983	0	0
T2	553510	553441	0	0
T3	22498	22440	0	0
T13	69103	67593	0	0
T14	361450	360782	0	0
T15	550	515	0	0
T16	842	751	0	0
T17	68661	68628	0	0
T18	23281	23207	0	0
T19	9866	9636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0