Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1678527	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263828

1

T1

216

T2

929

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	657379	1			T1	592		T2	2298		T3	230
values[0x0]	627426	1			T1	526		T2	2229		T3	33
values[0x1]	657550	1			T1	545		T2	2144		T3	249

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1301283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

641072

1

T1

541

T2

2202

T3

169

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8075	1			T1	12		T2	27		T3	1
valid_sources[0x01]	7761	1			T2	39		T3	2		T4	3
valid_sources[0x02]	7886	1			T1	20		T2	6		T3	3
valid_sources[0x03]	8124	1			T2	43		T3	3		T4	9
valid_sources[0x04]	7639	1			T1	20		T2	50		T3	3
valid_sources[0x05]	7521	1			T1	13		T2	14		T4	3
valid_sources[0x06]	7994	1			T2	36		T3	2		T4	7
valid_sources[0x07]	7220	1			T2	37		T3	1		T4	7
valid_sources[0x08]	7919	1			T2	38		T4	8		T11	2
valid_sources[0x09]	7721	1			T1	5		T2	22		T3	6
valid_sources[0x0a]	7091	1			T2	14		T4	14		T11	2
valid_sources[0x0b]	7229	1			T2	12		T3	3		T11	1
valid_sources[0x0c]	7359	1			T2	16		T3	3		T4	4
valid_sources[0x0d]	7699	1			T2	19		T3	2		T4	6
valid_sources[0x0e]	7248	1			T1	15		T2	30		T3	1
valid_sources[0x0f]	7781	1			T2	32		T3	3		T4	10
valid_sources[0x10]	8057	1			T1	7		T2	69		T3	3
valid_sources[0x11]	6902	1			T2	15		T3	4		T4	8
valid_sources[0x12]	7096	1			T2	9		T3	2		T4	16
valid_sources[0x13]	7527	1			T2	20		T4	1		T11	1
valid_sources[0x14]	7380	1			T2	14		T3	2		T4	9
valid_sources[0x15]	6435	1			T2	30		T3	1		T4	24
valid_sources[0x16]	7884	1			T1	13		T2	32		T3	2
valid_sources[0x17]	7908	1			T2	25		T3	1		T4	7
valid_sources[0x18]	6908	1			T1	29		T2	21		T3	1
valid_sources[0x19]	7882	1			T1	26		T2	21		T3	2
valid_sources[0x1a]	8560	1			T1	27		T2	18		T3	4
valid_sources[0x1b]	7576	1			T1	15		T2	40		T3	2
valid_sources[0x1c]	7569	1			T2	31		T3	2		T4	15
valid_sources[0x1d]	7627	1			T1	11		T2	22		T4	3
valid_sources[0x1e]	7347	1			T2	38		T3	1		T4	1
valid_sources[0x1f]	7019	1			T2	22		T3	2		T4	3
valid_sources[0x20]	7788	1			T1	8		T2	22		T3	4
valid_sources[0x21]	7880	1			T1	19		T2	19		T3	1
valid_sources[0x22]	6962	1			T1	7		T2	23		T3	1
valid_sources[0x23]	7788	1			T1	10		T2	36		T4	1
valid_sources[0x24]	6965	1			T2	23		T3	1		T4	6
valid_sources[0x25]	7476	1			T1	27		T2	63		T3	2
valid_sources[0x26]	7277	1			T2	49		T3	1		T4	3
valid_sources[0x27]	7342	1			T1	8		T2	26		T3	1
valid_sources[0x28]	7555	1			T2	13		T3	1		T4	23
valid_sources[0x29]	7596	1			T2	18		T3	1		T4	11
valid_sources[0x2a]	8361	1			T1	19		T2	18		T3	1
valid_sources[0x2b]	6947	1			T2	12		T4	13		T14	4
valid_sources[0x2c]	7715	1			T2	45		T3	7		T4	12
valid_sources[0x2d]	7750	1			T1	18		T2	32		T3	1
valid_sources[0x2e]	7526	1			T2	38		T3	2		T4	11
valid_sources[0x2f]	8038	1			T2	51		T4	1		T14	3
valid_sources[0x30]	7216	1			T1	25		T2	26		T3	2
valid_sources[0x31]	7218	1			T1	6		T2	25		T4	3
valid_sources[0x32]	8057	1			T2	20		T3	3		T4	7
valid_sources[0x33]	7956	1			T1	17		T2	19		T3	2
valid_sources[0x34]	6466	1			T1	13		T2	17		T3	2
valid_sources[0x35]	7037	1			T2	36		T3	2		T4	13
valid_sources[0x36]	6750	1			T1	12		T2	74		T3	1
valid_sources[0x37]	7760	1			T2	31		T3	2		T4	17
valid_sources[0x38]	7748	1			T1	12		T2	23		T3	4
valid_sources[0x39]	7914	1			T1	19		T2	58		T3	6
valid_sources[0x3a]	7811	1			T2	21		T3	4		T4	12
valid_sources[0x3b]	7665	1			T2	26		T4	3		T14	2
valid_sources[0x3c]	8385	1			T1	13		T2	27		T4	13
valid_sources[0x3d]	7280	1			T1	18		T2	23		T3	5
valid_sources[0x3e]	7400	1			T2	31		T3	1		T4	9
valid_sources[0x3f]	7371	1			T2	15		T3	2		T4	4
valid_sources[0x40]	7386	1			T1	10		T2	22		T3	6
valid_sources[0x41]	6577	1			T1	8		T2	17		T3	2
valid_sources[0x42]	7787	1			T2	5		T3	2		T4	9
valid_sources[0x43]	7132	1			T1	17		T2	11		T3	3
valid_sources[0x44]	7356	1			T1	11		T2	41		T14	3
valid_sources[0x45]	7589	1			T2	6		T3	4		T4	7
valid_sources[0x46]	7834	1			T2	35		T3	2		T4	8
valid_sources[0x47]	7251	1			T1	14		T2	13		T3	7
valid_sources[0x48]	7579	1			T2	36		T4	12		T14	8
valid_sources[0x49]	7878	1			T2	13		T3	2		T4	5
valid_sources[0x4a]	7790	1			T2	52		T3	2		T4	6
valid_sources[0x4b]	6844	1			T2	18		T4	3		T14	2
valid_sources[0x4c]	7290	1			T1	28		T2	20		T3	1
valid_sources[0x4d]	7147	1			T1	23		T2	48		T3	4
valid_sources[0x4e]	6921	1			T1	13		T2	46		T3	1
valid_sources[0x4f]	7958	1			T2	33		T3	2		T4	7
valid_sources[0x50]	7130	1			T2	15		T3	1		T4	7
valid_sources[0x51]	7749	1			T2	25		T3	4		T4	15
valid_sources[0x52]	7451	1			T2	15		T3	2		T4	2
valid_sources[0x53]	7909	1			T2	22		T3	4		T4	9
valid_sources[0x54]	7529	1			T2	24		T3	1		T4	4
valid_sources[0x55]	7169	1			T2	20		T3	2		T4	2
valid_sources[0x56]	7278	1			T2	26		T3	1		T4	7
valid_sources[0x57]	8182	1			T2	48		T3	2		T4	5
valid_sources[0x58]	7617	1			T2	30		T3	1		T4	6
valid_sources[0x59]	6810	1			T1	13		T2	10		T3	4
valid_sources[0x5a]	8013	1			T2	21		T3	2		T4	5
valid_sources[0x5b]	7638	1			T2	20		T4	9		T14	4
valid_sources[0x5c]	7420	1			T2	17		T3	3		T4	18
valid_sources[0x5d]	7092	1			T1	14		T2	13		T3	2
valid_sources[0x5e]	7234	1			T1	40		T2	1		T3	1
valid_sources[0x5f]	7157	1			T2	8		T4	7		T11	2
valid_sources[0x60]	8367	1			T2	30		T3	2		T4	12
valid_sources[0x61]	7285	1			T1	9		T2	18		T3	3
valid_sources[0x62]	7192	1			T2	29		T3	1		T4	9
valid_sources[0x63]	8393	1			T2	42		T3	1		T4	11
valid_sources[0x64]	7329	1			T1	20		T2	51		T3	3
valid_sources[0x65]	7093	1			T1	15		T2	17		T3	3
valid_sources[0x66]	8316	1			T2	19		T4	1		T14	2
valid_sources[0x67]	8119	1			T1	18		T2	27		T3	6
valid_sources[0x68]	6938	1			T2	38		T4	1		T11	1
valid_sources[0x69]	8268	1			T1	23		T2	24		T3	4
valid_sources[0x6a]	8517	1			T1	26		T2	18		T3	1
valid_sources[0x6b]	7240	1			T2	13		T3	2		T4	6
valid_sources[0x6c]	7377	1			T2	16		T3	3		T4	1
valid_sources[0x6d]	7673	1			T1	15		T2	11		T3	4
valid_sources[0x6e]	7419	1			T2	30		T4	7		T14	3
valid_sources[0x6f]	7145	1			T2	25		T3	1		T4	6
valid_sources[0x70]	6795	1			T2	45		T3	1		T4	2
valid_sources[0x71]	8208	1			T2	47		T11	1		T14	2
valid_sources[0x72]	6910	1			T1	33		T2	18		T3	2
valid_sources[0x73]	7326	1			T2	23		T3	2		T4	16
valid_sources[0x74]	7125	1			T1	11		T2	33		T3	2
valid_sources[0x75]	7080	1			T2	16		T4	12		T14	4
valid_sources[0x76]	7014	1			T2	12		T3	2		T4	2
valid_sources[0x77]	6924	1			T2	19		T3	4		T4	6
valid_sources[0x78]	7296	1			T2	28		T3	3		T4	4
valid_sources[0x79]	7145	1			T1	10		T2	10		T3	1
valid_sources[0x7a]	8446	1			T2	32		T3	1		T4	5
valid_sources[0x7b]	7245	1			T1	16		T2	25		T3	2
valid_sources[0x7c]	7075	1			T2	24		T3	2		T4	12
valid_sources[0x7d]	8229	1			T2	79		T3	1		T4	10
valid_sources[0x7e]	7760	1			T2	18		T3	1		T4	9
valid_sources[0x7f]	7239	1			T1	16		T2	16		T3	3
valid_sources[0x80]	7514	1			T2	27		T3	3		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27980

1

T1

16

T2

89

T3

12

values[0x0]

all_enables

biggest_size

207825

1

T1

171

T2

755

T3

8

values[0x1]

all_enables

biggest_size

28023

1

T1

29

T2

85

T3

19