Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	371064451	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	371064451	0	0
T1	3604048	52050	0	0
T2	9257584	172236	0	0
T3	1092392	50535	0	0
T4	223160	9643	0	0
T11	8750392	166155	0	0
T12	1978816	29035	0	0
T13	129640	1610	0	0
T14	358176	12970	0	0
T15	17594528	387700	0	0
T16	4514160	77572	0	0
T17	0	342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3604048	3602032	0	0
T2	9257584	9181872	0	0
T3	1092392	1064616	0	0
T4	223160	221424	0	0
T11	8750392	8749216	0	0
T12	1978816	1974616	0	0
T13	129640	127400	0	0
T14	358176	323904	0	0
T15	17594528	17516856	0	0
T16	4514160	4511024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3604048	3602032	0	0
T2	9257584	9181872	0	0
T3	1092392	1064616	0	0
T4	223160	221424	0	0
T11	8750392	8749216	0	0
T12	1978816	1974616	0	0
T13	129640	127400	0	0
T14	358176	323904	0	0
T15	17594528	17516856	0	0
T16	4514160	4511024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3604048	3602032	0	0
T2	9257584	9181872	0	0
T3	1092392	1064616	0	0
T4	223160	221424	0	0
T11	8750392	8749216	0	0
T12	1978816	1974616	0	0
T13	129640	127400	0	0
T14	358176	323904	0	0
T15	17594528	17516856	0	0
T16	4514160	4511024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	137588338	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	137588338	0	0
T1	64358	12823	0	0
T2	165314	68257	0	0
T3	19507	17330	0	0
T4	3985	3762	0	0
T11	156257	78256	0	0
T12	35336	13268	0	0
T13	2315	698	0	0
T14	6396	4748	0	0
T15	314188	146192	0	0
T16	80610	36135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	95933951	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	95933951	0	0
T1	64358	13209	0	0
T2	165314	26883	0	0
T3	19507	12099	0	0
T4	3985	1961	0	0
T11	156257	16274	0	0
T12	35336	4404	0	0
T13	2315	266	0	0
T14	6396	2945	0	0
T15	314188	93474	0	0
T16	80610	10271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1559719	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1559719	0	0
T1	64358	407	0	0
T2	165314	1171	0	0
T3	19507	677	0	0
T4	3985	83	0	0
T11	156257	2222	0	0
T12	35336	326	0	0
T13	2315	0	0	0
T14	6396	45	0	0
T15	314188	3942	0	0
T16	80610	769	0	0
T17	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3258723	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3258723	0	0
T1	64358	565	0	0
T2	165314	730	0	0
T3	19507	677	0	0
T4	3985	83	0	0
T11	156257	267	0	0
T12	35336	125	0	0
T13	2315	0	0	0
T14	6396	45	0	0
T15	314188	3928	0	0
T16	80610	303	0	0
T17	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1627077	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1627077	0	0
T1	64358	535	0	0
T2	165314	1103	0	0
T3	19507	174	0	0
T4	3985	79	0	0
T11	156257	2186	0	0
T12	35336	235	0	0
T13	2315	25	0	0
T14	6396	306	0	0
T15	314188	3020	0	0
T16	80610	1018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3774998	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3774998	0	0
T1	64358	632	0	0
T2	165314	683	0	0
T3	19507	174	0	0
T4	3985	79	0	0
T11	156257	228	0	0
T12	35336	88	0	0
T13	2315	4	0	0
T14	6396	306	0	0
T15	314188	3046	0	0
T16	80610	418	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1607451	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1607451	0	0
T1	64358	356	0	0
T2	165314	3537	0	0
T3	19507	177	0	0
T4	3985	70	0	0
T11	156257	3347	0	0
T12	35336	212	0	0
T13	2315	49	0	0
T14	6396	39	0	0
T15	314188	1732	0	0
T16	80610	787	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3726163	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3726163	0	0
T1	64358	356	0	0
T2	165314	1735	0	0
T3	19507	177	0	0
T4	3985	70	0	0
T11	156257	44	0	0
T12	35336	75	0	0
T13	2315	18	0	0
T14	6396	39	0	0
T15	314188	1601	0	0
T16	80610	323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1576158	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1576158	0	0
T1	64358	477	0	0
T2	165314	1261	0	0
T3	19507	193	0	0
T4	3985	72	0	0
T11	156257	301	0	0
T12	35336	271	0	0
T13	2315	9	0	0
T14	6396	48	0	0
T15	314188	3448	0	0
T16	80610	1068	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3309497	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3309497	0	0
T1	64358	507	0	0
T2	165314	745	0	0
T3	19507	193	0	0
T4	3985	72	0	0
T11	156257	1	0	0
T12	35336	126	0	0
T13	2315	1	0	0
T14	6396	48	0	0
T15	314188	3349	0	0
T16	80610	432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1589179	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1589179	0	0
T1	64358	416	0	0
T2	165314	1184	0	0
T3	19507	190	0	0
T4	3985	63	0	0
T11	156257	3332	0	0
T12	35336	251	0	0
T13	2315	14	0	0
T14	6396	45	0	0
T15	314188	1740	0	0
T16	80610	1021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3494927	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3494927	0	0
T1	64358	418	0	0
T2	165314	614	0	0
T3	19507	190	0	0
T4	3985	63	0	0
T11	156257	1703	0	0
T12	35336	99	0	0
T13	2315	8	0	0
T14	6396	45	0	0
T15	314188	1644	0	0
T16	80610	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1607221	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1607221	0	0
T1	64358	455	0	0
T2	165314	1196	0	0
T3	19507	177	0	0
T4	3985	54	0	0
T11	156257	1810	0	0
T12	35336	336	0	0
T13	2315	0	0	0
T14	6396	42	0	0
T15	314188	1854	0	0
T16	80610	720	0	0
T17	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	4019843	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	4019843	0	0
T1	64358	549	0	0
T2	165314	654	0	0
T3	19507	177	0	0
T4	3985	54	0	0
T11	156257	282	0	0
T12	35336	142	0	0
T13	2315	0	0	0
T14	6396	42	0	0
T15	314188	1828	0	0
T16	80610	329	0	0
T17	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1543322	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1543322	0	0
T1	64358	471	0	0
T2	165314	1788	0	0
T3	19507	209	0	0
T4	3985	79	0	0
T11	156257	1422	0	0
T12	35336	328	0	0
T13	2315	0	0	0
T14	6396	56	0	0
T15	314188	1692	0	0
T16	80610	868	0	0
T17	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3560608	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3560608	0	0
T1	64358	538	0	0
T2	165314	936	0	0
T3	19507	209	0	0
T4	3985	79	0	0
T11	156257	302	0	0
T12	35336	146	0	0
T13	2315	0	0	0
T14	6396	56	0	0
T15	314188	1603	0	0
T16	80610	302	0	0
T17	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1590024	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1590024	0	0
T1	64358	465	0	0
T2	165314	1173	0	0
T3	19507	456	0	0
T4	3985	72	0	0
T11	156257	1251	0	0
T12	35336	393	0	0
T13	2315	42	0	0
T14	6396	306	0	0
T15	314188	3422	0	0
T16	80610	867	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3287204	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3287204	0	0
T1	64358	436	0	0
T2	165314	687	0	0
T3	19507	456	0	0
T4	3985	72	0	0
T11	156257	853	0	0
T12	35336	127	0	0
T13	2315	9	0	0
T14	6396	306	0	0
T15	314188	3571	0	0
T16	80610	306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1614336	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1614336	0	0
T1	64358	571	0	0
T2	165314	1267	0	0
T3	19507	178	0	0
T4	3985	60	0	0
T11	156257	1263	0	0
T12	35336	218	0	0
T13	2315	17	0	0
T14	6396	38	0	0
T15	314188	1831	0	0
T16	80610	827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3570702	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3570702	0	0
T1	64358	563	0	0
T2	165314	783	0	0
T3	19507	178	0	0
T4	3985	60	0	0
T11	156257	366	0	0
T12	35336	90	0	0
T13	2315	11	0	0
T14	6396	38	0	0
T15	314188	1792	0	0
T16	80610	394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1593207	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1593207	0	0
T1	64358	545	0	0
T2	165314	1290	0	0
T3	19507	163	0	0
T4	3985	65	0	0
T11	156257	2865	0	0
T12	35336	284	0	0
T13	2315	26	0	0
T14	6396	36	0	0
T15	314188	1726	0	0
T16	80610	888	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3560834	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3560834	0	0
T1	64358	537	0	0
T2	165314	784	0	0
T3	19507	163	0	0
T4	3985	65	0	0
T11	156257	263	0	0
T12	35336	112	0	0
T13	2315	25	0	0
T14	6396	36	0	0
T15	314188	1688	0	0
T16	80610	331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1630975	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1630975	0	0
T1	64358	550	0	0
T2	165314	1075	0	0
T3	19507	703	0	0
T4	3985	61	0	0
T11	156257	2753	0	0
T12	35336	282	0	0
T13	2315	0	0	0
T14	6396	46	0	0
T15	314188	3129	0	0
T16	80610	770	0	0
T17	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3194230	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3194230	0	0
T1	64358	459	0	0
T2	165314	631	0	0
T3	19507	703	0	0
T4	3985	61	0	0
T11	156257	1038	0	0
T12	35336	139	0	0
T13	2315	0	0	0
T14	6396	46	0	0
T15	314188	3062	0	0
T16	80610	277	0	0
T17	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1544089	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1544089	0	0
T1	64358	485	0	0
T2	165314	1381	0	0
T3	19507	881	0	0
T4	3985	76	0	0
T11	156257	3061	0	0
T12	35336	267	0	0
T13	2315	8	0	0
T14	6396	59	0	0
T15	314188	1755	0	0
T16	80610	750	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3905962	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3905962	0	0
T1	64358	428	0	0
T2	165314	681	0	0
T3	19507	881	0	0
T4	3985	76	0	0
T11	156257	1175	0	0
T12	35336	88	0	0
T13	2315	3	0	0
T14	6396	59	0	0
T15	314188	1795	0	0
T16	80610	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1608628	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1608628	0	0
T1	64358	560	0	0
T2	165314	1318	0	0
T3	19507	181	0	0
T4	3985	80	0	0
T11	156257	1264	0	0
T12	35336	374	0	0
T13	2315	14	0	0
T14	6396	52	0	0
T15	314188	4027	0	0
T16	80610	875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3446359	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3446359	0	0
T1	64358	567	0	0
T2	165314	901	0	0
T3	19507	181	0	0
T4	3985	80	0	0
T11	156257	1146	0	0
T12	35336	186	0	0
T13	2315	2	0	0
T14	6396	52	0	0
T15	314188	3863	0	0
T16	80610	432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1558473	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1558473	0	0
T1	64358	520	0	0
T2	165314	1428	0	0
T3	19507	190	0	0
T4	3985	72	0	0
T11	156257	533	0	0
T12	35336	314	0	0
T13	2315	30	0	0
T14	6396	45	0	0
T15	314188	6054	0	0
T16	80610	685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3443441	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3443441	0	0
T1	64358	440	0	0
T2	165314	856	0	0
T3	19507	190	0	0
T4	3985	72	0	0
T11	156257	221	0	0
T12	35336	114	0	0
T13	2315	11	0	0
T14	6396	45	0	0
T15	314188	5624	0	0
T16	80610	229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1611199	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1611199	0	0
T1	64358	473	0	0
T2	165314	3228	0	0
T3	19507	168	0	0
T4	3985	60	0	0
T11	156257	1794	0	0
T12	35336	221	0	0
T13	2315	1	0	0
T14	6396	303	0	0
T15	314188	1730	0	0
T16	80610	834	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3247052	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3247052	0	0
T1	64358	489	0	0
T2	165314	1433	0	0
T3	19507	168	0	0
T4	3985	60	0	0
T11	156257	796	0	0
T12	35336	105	0	0
T13	2315	10	0	0
T14	6396	303	0	0
T15	314188	1716	0	0
T16	80610	333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1548267	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1548267	0	0
T1	64358	525	0	0
T2	165314	3367	0	0
T3	19507	757	0	0
T4	3985	78	0	0
T11	156257	3866	0	0
T12	35336	316	0	0
T13	2315	16	0	0
T14	6396	44	0	0
T15	314188	3710	0	0
T16	80610	795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3124214	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3124214	0	0
T1	64358	586	0	0
T2	165314	1483	0	0
T3	19507	757	0	0
T4	3985	78	0	0
T11	156257	577	0	0
T12	35336	115	0	0
T13	2315	6	0	0
T14	6396	44	0	0
T15	314188	4059	0	0
T16	80610	314	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1541980	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1541980	0	0
T1	64358	373	0	0
T2	165314	1939	0	0
T3	19507	446	0	0
T4	3985	81	0	0
T11	156257	1901	0	0
T12	35336	312	0	0
T13	2315	27	0	0
T14	6396	54	0	0
T15	314188	1941	0	0
T16	80610	895	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3693073	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3693073	0	0
T1	64358	443	0	0
T2	165314	974	0	0
T3	19507	445	0	0
T4	3985	81	0	0
T11	156257	686	0	0
T12	35336	141	0	0
T13	2315	15	0	0
T14	6396	54	0	0
T15	314188	1815	0	0
T16	80610	412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1628542	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1628542	0	0
T1	64358	490	0	0
T2	165314	5281	0	0
T3	19507	183	0	0
T4	3985	71	0	0
T11	156257	2856	0	0
T12	35336	424	0	0
T13	2315	17	0	0
T14	6396	32	0	0
T15	314188	1689	0	0
T16	80610	650	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3751064	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3751064	0	0
T1	64358	552	0	0
T2	165314	2369	0	0
T3	19507	183	0	0
T4	3985	71	0	0
T11	156257	531	0	0
T12	35336	197	0	0
T13	2315	18	0	0
T14	6396	32	0	0
T15	314188	1683	0	0
T16	80610	267	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1595307	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1595307	0	0
T1	64358	533	0	0
T2	165314	1632	0	0
T3	19507	644	0	0
T4	3985	79	0	0
T11	156257	1627	0	0
T12	35336	302	0	0
T13	2315	24	0	0
T14	6396	259	0	0
T15	314188	1617	0	0
T16	80610	693	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3651353	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3651353	0	0
T1	64358	507	0	0
T2	165314	920	0	0
T3	19507	644	0	0
T4	3985	79	0	0
T11	156257	499	0	0
T12	35336	120	0	0
T13	2315	6	0	0
T14	6396	259	0	0
T15	314188	1632	0	0
T16	80610	242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1588295	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1588295	0	0
T1	64358	434	0	0
T2	165314	3383	0	0
T3	19507	761	0	0
T4	3985	73	0	0
T11	156257	2243	0	0
T12	35336	361	0	0
T13	2315	15	0	0
T14	6396	296	0	0
T15	314188	3785	0	0
T16	80610	765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3507855	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3507855	0	0
T1	64358	447	0	0
T2	165314	1618	0	0
T3	19507	761	0	0
T4	3985	73	0	0
T11	156257	1798	0	0
T12	35336	136	0	0
T13	2315	2	0	0
T14	6396	296	0	0
T15	314188	3802	0	0
T16	80610	359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1537947	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1537947	0	0
T1	64358	481	0	0
T2	165314	1354	0	0
T3	19507	493	0	0
T4	3985	83	0	0
T11	156257	1941	0	0
T12	35336	321	0	0
T13	2315	3	0	0
T14	6396	25	0	0
T15	314188	3603	0	0
T16	80610	880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3268908	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3268908	0	0
T1	64358	488	0	0
T2	165314	811	0	0
T3	19507	493	0	0
T4	3985	83	0	0
T11	156257	929	0	0
T12	35336	130	0	0
T13	2315	7	0	0
T14	6396	25	0	0
T15	314188	3437	0	0
T16	80610	284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1571582	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1571582	0	0
T1	64358	512	0	0
T2	165314	2507	0	0
T3	19507	238	0	0
T4	3985	74	0	0
T11	156257	1000	0	0
T12	35336	382	0	0
T13	2315	15	0	0
T14	6396	47	0	0
T15	314188	1935	0	0
T16	80610	861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3486067	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3486067	0	0
T1	64358	567	0	0
T2	165314	1187	0	0
T3	19507	237	0	0
T4	3985	74	0	0
T11	156257	69	0	0
T12	35336	129	0	0
T13	2315	15	0	0
T14	6396	46	0	0
T15	314188	2051	0	0
T16	80610	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1539854	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1539854	0	0
T1	64358	428	0	0
T2	165314	1220	0	0
T3	19507	701	0	0
T4	3985	76	0	0
T11	156257	588	0	0
T12	35336	254	0	0
T13	2315	6	0	0
T14	6396	256	0	0
T15	314188	2010	0	0
T16	80610	1000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3978270	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3978270	0	0
T1	64358	531	0	0
T2	165314	829	0	0
T3	19507	701	0	0
T4	3985	76	0	0
T11	156257	323	0	0
T12	35336	120	0	0
T13	2315	1	0	0
T14	6396	256	0	0
T15	314188	1782	0	0
T16	80610	394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1550542	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1550542	0	0
T1	64358	475	0	0
T2	165314	998	0	0
T3	19507	693	0	0
T4	3985	77	0	0
T11	156257	1026	0	0
T12	35336	262	0	0
T13	2315	15	0	0
T14	6396	32	0	0
T15	314188	4118	0	0
T16	80610	707	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3276717	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3276717	0	0
T1	64358	536	0	0
T2	165314	584	0	0
T3	19507	693	0	0
T4	3985	77	0	0
T11	156257	3	0	0
T12	35336	96	0	0
T13	2315	11	0	0
T14	6396	32	0	0
T15	314188	3910	0	0
T16	80610	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1569913	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1569913	0	0
T1	64358	423	0	0
T2	165314	2991	0	0
T3	19507	443	0	0
T4	3985	82	0	0
T11	156257	3347	0	0
T12	35336	363	0	0
T13	2315	15	0	0
T14	6396	29	0	0
T15	314188	1781	0	0
T16	80610	836	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3833812	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3833812	0	0
T1	64358	368	0	0
T2	165314	1524	0	0
T3	19507	443	0	0
T4	3985	82	0	0
T11	156257	918	0	0
T12	35336	173	0	0
T13	2315	1	0	0
T14	6396	29	0	0
T15	314188	1802	0	0
T16	80610	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1582817	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1582817	0	0
T1	64358	490	0	0
T2	165314	1199	0	0
T3	19507	314	0	0
T4	3985	70	0	0
T11	156257	2891	0	0
T12	35336	163	0	0
T13	2315	4	0	0
T14	6396	57	0	0
T15	314188	1912	0	0
T16	80610	778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3358921	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3358921	0	0
T1	64358	299	0	0
T2	165314	701	0	0
T3	19507	313	0	0
T4	3985	70	0	0
T11	156257	838	0	0
T12	35336	98	0	0
T13	2315	12	0	0
T14	6396	57	0	0
T15	314188	1792	0	0
T16	80610	281	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	1552071	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	1552071	0	0
T1	64358	366	0	0
T2	165314	1189	0	0
T3	19507	165	0	0
T4	3985	70	0	0
T11	156257	2661	0	0
T12	35336	261	0	0
T13	2315	49	0	0
T14	6396	42	0	0
T15	314188	5502	0	0
T16	80610	701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332236138	3143190	0	0
DepthKnown_A	332236138	332113235	0	0
RvalidKnown_A	332236138	332113235	0	0
WreadyKnown_A	332236138	332113235	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	3143190	0	0
T1	64358	394	0	0
T2	165314	783	0	0
T3	19507	164	0	0
T4	3985	70	0	0
T11	156257	418	0	0
T12	35336	113	0	0
T13	2315	9	0	0
T14	6396	42	0	0
T15	314188	5454	0	0
T16	80610	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332236138	332113235	0	0
T1	64358	64322	0	0
T2	165314	163962	0	0
T3	19507	19011	0	0
T4	3985	3954	0	0
T11	156257	156236	0	0
T12	35336	35261	0	0
T13	2315	2275	0	0
T14	6396	5784	0	0
T15	314188	312801	0	0
T16	80610	80554	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0