Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1793815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

281753

1

T1

89

T2

691

T3

396

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	702382	1			T1	251		T2	1697		T3	988
values[0x0]	668432	1			T1	216		T2	1651		T3	957
values[0x1]	704754	1			T1	231		T2	1631		T3	986

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1388646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

686922

1

T1

241

T2

1621

T3

948

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9895	1			T1	38		T2	21		T3	11
valid_sources[0x01]	8613	1			T2	19		T4	5		T17	30
valid_sources[0x02]	7615	1			T1	15		T2	20		T3	14
valid_sources[0x03]	8288	1			T2	18		T3	9		T4	4
valid_sources[0x04]	8869	1			T1	2		T2	20		T3	2
valid_sources[0x05]	8958	1			T1	16		T2	20		T3	10
valid_sources[0x06]	7745	1			T1	3		T2	18		T3	12
valid_sources[0x07]	8448	1			T1	2		T2	17		T3	16
valid_sources[0x08]	7386	1			T1	15		T2	17		T3	13
valid_sources[0x09]	7541	1			T2	19		T3	22		T17	54
valid_sources[0x0a]	8227	1			T2	23		T3	5		T4	1
valid_sources[0x0b]	7956	1			T1	1		T2	21		T3	12
valid_sources[0x0c]	7569	1			T2	19		T3	19		T4	2
valid_sources[0x0d]	9203	1			T2	22		T3	13		T4	2
valid_sources[0x0e]	7743	1			T2	22		T3	8		T4	3
valid_sources[0x0f]	8255	1			T1	1		T2	19		T3	17
valid_sources[0x10]	8489	1			T1	19		T2	17		T3	4
valid_sources[0x11]	7570	1			T2	19		T3	4		T4	1
valid_sources[0x12]	8019	1			T1	4		T2	21		T3	16
valid_sources[0x13]	7064	1			T2	20		T3	2		T17	20
valid_sources[0x14]	8064	1			T2	21		T3	23		T4	2
valid_sources[0x15]	7939	1			T2	19		T3	3		T17	39
valid_sources[0x16]	8003	1			T1	3		T2	20		T3	11
valid_sources[0x17]	7691	1			T1	8		T2	22		T3	25
valid_sources[0x18]	9257	1			T2	20		T3	7		T4	1
valid_sources[0x19]	7409	1			T2	19		T3	17		T17	11
valid_sources[0x1a]	7863	1			T2	20		T3	6		T17	37
valid_sources[0x1b]	8179	1			T2	21		T3	4		T4	1
valid_sources[0x1c]	8084	1			T2	18		T3	11		T4	2
valid_sources[0x1d]	8335	1			T1	1		T2	17		T3	27
valid_sources[0x1e]	8010	1			T2	19		T3	9		T17	53
valid_sources[0x1f]	7916	1			T2	19		T3	18		T4	1
valid_sources[0x20]	7594	1			T2	19		T3	11		T4	6
valid_sources[0x21]	9643	1			T1	4		T2	20		T3	8
valid_sources[0x22]	7115	1			T2	18		T3	16		T17	27
valid_sources[0x23]	7765	1			T2	18		T3	3		T4	4
valid_sources[0x24]	8389	1			T2	19		T4	2		T17	18
valid_sources[0x25]	7410	1			T2	19		T3	9		T17	23
valid_sources[0x26]	7719	1			T2	20		T3	14		T4	1
valid_sources[0x27]	7377	1			T2	22		T3	12		T4	1
valid_sources[0x28]	7436	1			T2	18		T3	7		T17	57
valid_sources[0x29]	8698	1			T2	20		T3	9		T4	4
valid_sources[0x2a]	8201	1			T1	2		T2	21		T3	4
valid_sources[0x2b]	7067	1			T2	17		T3	17		T4	3
valid_sources[0x2c]	8493	1			T2	21		T3	8		T4	1
valid_sources[0x2d]	8502	1			T2	17		T3	4		T4	3
valid_sources[0x2e]	10777	1			T1	27		T2	20		T3	8
valid_sources[0x2f]	9484	1			T2	18		T3	8		T17	13
valid_sources[0x30]	7858	1			T2	19		T3	4		T4	1
valid_sources[0x31]	7860	1			T2	21		T3	5		T4	3
valid_sources[0x32]	8460	1			T2	19		T4	1		T17	64
valid_sources[0x33]	7734	1			T2	20		T3	18		T4	1
valid_sources[0x34]	7289	1			T2	22		T3	13		T4	4
valid_sources[0x35]	8257	1			T1	5		T2	20		T3	14
valid_sources[0x36]	7234	1			T1	23		T2	20		T3	18
valid_sources[0x37]	7660	1			T2	18		T3	15		T4	3
valid_sources[0x38]	8847	1			T1	6		T2	20		T3	2
valid_sources[0x39]	8102	1			T2	18		T3	21		T4	3
valid_sources[0x3a]	8282	1			T2	18		T3	6		T4	3
valid_sources[0x3b]	8125	1			T1	6		T2	18		T3	17
valid_sources[0x3c]	7532	1			T2	19		T3	33		T4	2
valid_sources[0x3d]	7194	1			T2	18		T3	17		T4	4
valid_sources[0x3e]	8000	1			T2	19		T3	1		T17	16
valid_sources[0x3f]	7743	1			T2	17		T3	9		T4	3
valid_sources[0x40]	8202	1			T1	4		T2	17		T3	3
valid_sources[0x41]	8784	1			T1	3		T2	20		T4	2
valid_sources[0x42]	7655	1			T2	21		T3	14		T4	3
valid_sources[0x43]	7410	1			T2	21		T3	5		T4	1
valid_sources[0x44]	9737	1			T2	18		T3	4		T17	12
valid_sources[0x45]	8162	1			T2	21		T3	16		T4	3
valid_sources[0x46]	7616	1			T2	19		T3	18		T4	3
valid_sources[0x47]	7527	1			T2	20		T3	9		T17	10
valid_sources[0x48]	7759	1			T2	21		T3	3		T4	1
valid_sources[0x49]	7738	1			T2	18		T3	7		T4	1
valid_sources[0x4a]	7336	1			T2	22		T3	9		T4	2
valid_sources[0x4b]	7535	1			T2	20		T3	6		T4	2
valid_sources[0x4c]	7687	1			T2	18		T3	18		T4	3
valid_sources[0x4d]	8870	1			T2	19		T3	18		T4	3
valid_sources[0x4e]	6911	1			T2	19		T17	17		T15	5
valid_sources[0x4f]	7846	1			T1	29		T2	20		T3	1
valid_sources[0x50]	7143	1			T2	18		T3	14		T4	4
valid_sources[0x51]	8545	1			T2	18		T4	1		T17	35
valid_sources[0x52]	8060	1			T1	26		T2	19		T3	1
valid_sources[0x53]	9248	1			T1	2		T2	21		T3	27
valid_sources[0x54]	8235	1			T2	20		T3	15		T4	5
valid_sources[0x55]	7634	1			T1	4		T2	20		T3	4
valid_sources[0x56]	7525	1			T2	17		T3	21		T4	1
valid_sources[0x57]	7839	1			T2	22		T3	7		T4	3
valid_sources[0x58]	8734	1			T1	9		T2	19		T3	13
valid_sources[0x59]	7504	1			T1	1		T2	21		T3	9
valid_sources[0x5a]	8254	1			T2	20		T3	9		T4	5
valid_sources[0x5b]	7763	1			T2	20		T3	16		T17	24
valid_sources[0x5c]	8875	1			T2	20		T3	29		T17	22
valid_sources[0x5d]	8298	1			T2	21		T3	3		T17	21
valid_sources[0x5e]	8027	1			T2	19		T3	11		T4	1
valid_sources[0x5f]	8711	1			T2	18		T3	10		T4	1
valid_sources[0x60]	8380	1			T2	22		T3	15		T4	1
valid_sources[0x61]	9806	1			T2	19		T3	15		T4	3
valid_sources[0x62]	8916	1			T1	12		T2	17		T3	21
valid_sources[0x63]	7309	1			T2	18		T3	12		T4	1
valid_sources[0x64]	8262	1			T2	20		T3	2		T17	25
valid_sources[0x65]	8295	1			T1	6		T2	21		T3	20
valid_sources[0x66]	9328	1			T1	48		T2	18		T3	11
valid_sources[0x67]	7660	1			T2	22		T3	15		T4	3
valid_sources[0x68]	9724	1			T2	20		T3	21		T4	1
valid_sources[0x69]	7657	1			T1	7		T2	18		T3	6
valid_sources[0x6a]	9132	1			T2	19		T3	11		T4	2
valid_sources[0x6b]	8405	1			T2	19		T3	23		T4	1
valid_sources[0x6c]	7963	1			T2	20		T3	10		T17	43
valid_sources[0x6d]	7689	1			T1	1		T2	20		T3	7
valid_sources[0x6e]	8376	1			T2	22		T3	2		T4	7
valid_sources[0x6f]	8369	1			T1	15		T2	19		T3	6
valid_sources[0x70]	9065	1			T2	21		T3	16		T17	29
valid_sources[0x71]	8348	1			T2	21		T3	23		T17	70
valid_sources[0x72]	7320	1			T2	19		T3	2		T4	1
valid_sources[0x73]	11315	1			T1	3		T2	21		T3	1
valid_sources[0x74]	7943	1			T2	18		T3	16		T4	5
valid_sources[0x75]	8558	1			T2	23		T3	11		T4	1
valid_sources[0x76]	8807	1			T1	1		T2	21		T3	11
valid_sources[0x77]	8866	1			T2	20		T3	8		T4	7
valid_sources[0x78]	7438	1			T1	3		T2	18		T3	2
valid_sources[0x79]	7673	1			T2	17		T3	17		T17	29
valid_sources[0x7a]	7815	1			T2	20		T3	5		T4	1
valid_sources[0x7b]	8038	1			T2	19		T3	23		T4	2
valid_sources[0x7c]	7386	1			T2	17		T3	12		T4	2
valid_sources[0x7d]	7752	1			T2	21		T3	3		T4	1
valid_sources[0x7e]	7871	1			T2	22		T3	19		T17	17
valid_sources[0x7f]	8450	1			T1	2		T2	22		T3	11
valid_sources[0x80]	8344	1			T2	19		T3	35		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30062

1

T1

7

T2

64

T3

30

values[0x0]

all_enables

biggest_size

221727

1

T1

72

T2

562

T3

331

values[0x1]

all_enables

biggest_size

29964

1

T1

10

T2

65

T3

35