Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	345309188	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345309188	0	0
T1	849016	15567	0	0
T2	24071152	2013681	0	0
T3	2780120	41543	0	0
T4	13059424	244184	0	0
T15	9044896	1729614	0	0
T16	0	108	0	0
T17	765520	32771	0	0
T18	1331960	51636	0	0
T19	5648832	99689	0	0
T20	1158808	56936	0	0
T21	2049656	54080	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	849016	848456	0	0
T2	24071152	24070872	0	0
T3	2780120	2776592	0	0
T4	13059424	13001016	0	0
T15	9044896	9044728	0	0
T17	765520	759920	0	0
T18	1331960	1274224	0	0
T19	5648832	5644184	0	0
T20	1158808	1151024	0	0
T21	2049656	2047136	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	849016	848456	0	0
T2	24071152	24070872	0	0
T3	2780120	2776592	0	0
T4	13059424	13001016	0	0
T15	9044896	9044728	0	0
T17	765520	759920	0	0
T18	1331960	1274224	0	0
T19	5648832	5644184	0	0
T20	1158808	1151024	0	0
T21	2049656	2047136	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	849016	848456	0	0
T2	24071152	24070872	0	0
T3	2780120	2776592	0	0
T4	13059424	13001016	0	0
T15	9044896	9044728	0	0
T17	765520	759920	0	0
T18	1331960	1274224	0	0
T19	5648832	5644184	0	0
T20	1158808	1151024	0	0
T21	2049656	2047136	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T15	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	123380178	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	123380178	0	0
T1	15161	6289	0	0
T2	429842	23059	0	0
T3	49645	19340	0	0
T4	233204	109950	0	0
T15	161516	789434	0	0
T17	13670	13039	0	0
T18	23785	19443	0	0
T19	100872	97716	0	0
T20	20693	20122	0	0
T21	36601	22672	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	91547556	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	91547556	0	0
T1	15161	4071	0	0
T2	429842	178869	0	0
T3	49645	6013	0	0
T4	233204	30728	0	0
T15	161516	199174	0	0
T17	13670	7156	0	0
T18	23785	11721	0	0
T19	100872	552	0	0
T20	20693	12634	0	0
T21	36601	10523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1458115	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1458115	0	0
T1	15161	107	0	0
T2	429842	0	0	0
T3	49645	409	0	0
T4	233204	1625	0	0
T15	161516	16759	0	0
T16	0	2	0	0
T17	13670	93	0	0
T18	23785	306	0	0
T19	100872	23	0	0
T20	20693	661	0	0
T21	36601	347	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3004066	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3004066	0	0
T1	15161	124	0	0
T2	429842	0	0	0
T3	49645	131	0	0
T4	233204	596	0	0
T15	161516	5415	0	0
T16	0	2	0	0
T17	13670	93	0	0
T18	23785	306	0	0
T19	100872	7	0	0
T20	20693	661	0	0
T21	36601	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1441640	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1441640	0	0
T1	15161	153	0	0
T2	429842	1201	0	0
T3	49645	308	0	0
T4	233204	2120	0	0
T15	161516	23090	0	0
T17	13670	110	0	0
T18	23785	353	0	0
T19	100872	52	0	0
T20	20693	216	0	0
T21	36601	424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3156287	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3156287	0	0
T1	15161	128	0	0
T2	429842	91468	0	0
T3	49645	157	0	0
T4	233204	929	0	0
T15	161516	9272	0	0
T17	13670	110	0	0
T18	23785	352	0	0
T19	100872	13	0	0
T20	20693	216	0	0
T21	36601	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1522317	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1522317	0	0
T1	15161	136	0	0
T2	429842	1023	0	0
T3	49645	403	0	0
T4	233204	4230	0	0
T15	161516	15580	0	0
T17	13670	112	0	0
T18	23785	326	0	0
T19	100872	10	0	0
T20	20693	187	0	0
T21	36601	434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3686932	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3686932	0	0
T1	15161	159	0	0
T2	429842	79312	0	0
T3	49645	162	0	0
T4	233204	1664	0	0
T15	161516	7602	0	0
T17	13670	112	0	0
T18	23785	326	0	0
T19	100872	6	0	0
T20	20693	187	0	0
T21	36601	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1464300	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1464300	0	0
T1	15161	101	0	0
T2	429842	1203	0	0
T3	49645	401	0	0
T4	233204	6986	0	0
T15	161516	25342	0	0
T17	13670	114	0	0
T18	23785	330	0	0
T19	100872	24	0	0
T20	20693	212	0	0
T21	36601	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3876569	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3876569	0	0
T1	15161	73	0	0
T2	429842	88105	0	0
T3	49645	157	0	0
T4	233204	2814	0	0
T15	161516	9613	0	0
T17	13670	114	0	0
T18	23785	330	0	0
T19	100872	3	0	0
T20	20693	212	0	0
T21	36601	309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1520364	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1520364	0	0
T1	15161	125	0	0
T2	429842	934	0	0
T3	49645	360	0	0
T4	233204	2054	0	0
T15	161516	16791	0	0
T17	13670	363	0	0
T18	23785	354	0	0
T19	100872	23	0	0
T20	20693	439	0	0
T21	36601	293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3387377	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3387377	0	0
T1	15161	170	0	0
T2	429842	75705	0	0
T3	49645	158	0	0
T4	233204	873	0	0
T15	161516	6653	0	0
T17	13670	363	0	0
T18	23785	353	0	0
T19	100872	5	0	0
T20	20693	439	0	0
T21	36601	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1496379	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1496379	0	0
T1	15161	86	0	0
T2	429842	0	0	0
T3	49645	366	0	0
T4	233204	1408	0	0
T15	161516	22934	0	0
T16	0	5	0	0
T17	13670	323	0	0
T18	23785	307	0	0
T19	100872	56	0	0
T20	20693	202	0	0
T21	36601	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3165409	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3165409	0	0
T1	15161	72	0	0
T2	429842	0	0	0
T3	49645	185	0	0
T4	233204	633	0	0
T15	161516	6592	0	0
T16	0	5	0	0
T17	13670	323	0	0
T18	23785	307	0	0
T19	100872	10	0	0
T20	20693	202	0	0
T21	36601	397	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1495962	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1495962	0	0
T1	15161	63	0	0
T2	429842	0	0	0
T3	49645	408	0	0
T4	233204	3240	0	0
T15	161516	22125	0	0
T16	0	2	0	0
T17	13670	117	0	0
T18	23785	332	0	0
T19	100872	47	0	0
T20	20693	463	0	0
T21	36601	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	2512737	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	2512737	0	0
T1	15161	64	0	0
T2	429842	0	0	0
T3	49645	116	0	0
T4	233204	1445	0	0
T15	161516	11359	0	0
T16	0	2	0	0
T17	13670	117	0	0
T18	23785	332	0	0
T19	100872	10	0	0
T20	20693	463	0	0
T21	36601	365	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1462331	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1462331	0	0
T1	15161	64	0	0
T2	429842	927	0	0
T3	49645	444	0	0
T4	233204	1568	0	0
T15	161516	20769	0	0
T17	13670	115	0	0
T18	23785	339	0	0
T19	100872	42	0	0
T20	20693	408	0	0
T21	36601	492	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3860409	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3860409	0	0
T1	15161	78	0	0
T2	429842	71769	0	0
T3	49645	208	0	0
T4	233204	660	0	0
T15	161516	6966	0	0
T17	13670	115	0	0
T18	23785	339	0	0
T19	100872	8	0	0
T20	20693	408	0	0
T21	36601	425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1468644	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1468644	0	0
T1	15161	125	0	0
T2	429842	2614	0	0
T3	49645	396	0	0
T4	233204	1580	0	0
T15	161516	17540	0	0
T17	13670	119	0	0
T18	23785	475	0	0
T19	100872	17	0	0
T20	20693	463	0	0
T21	36601	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3614561	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3614561	0	0
T1	15161	93	0	0
T2	429842	203352	0	0
T3	49645	158	0	0
T4	233204	589	0	0
T15	161516	8301	0	0
T17	13670	119	0	0
T18	23785	475	0	0
T19	100872	6	0	0
T20	20693	463	0	0
T21	36601	338	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1435165	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1435165	0	0
T1	15161	56	0	0
T2	429842	0	0	0
T3	49645	553	0	0
T4	233204	2504	0	0
T15	161516	17878	0	0
T16	0	6	0	0
T17	13670	574	0	0
T18	23785	349	0	0
T19	100872	53	0	0
T20	20693	435	0	0
T21	36601	294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	2906915	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	2906915	0	0
T1	15161	49	0	0
T2	429842	0	0	0
T3	49645	196	0	0
T4	233204	1075	0	0
T15	161516	7246	0	0
T16	0	6	0	0
T17	13670	574	0	0
T18	23785	349	0	0
T19	100872	8	0	0
T20	20693	435	0	0
T21	36601	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1475504	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1475504	0	0
T1	15161	146	0	0
T2	429842	877	0	0
T3	49645	535	0	0
T4	233204	1644	0	0
T15	161516	15319	0	0
T17	13670	344	0	0
T18	23785	417	0	0
T19	100872	32	0	0
T20	20693	500	0	0
T21	36601	415	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3876109	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3876109	0	0
T1	15161	123	0	0
T2	429842	80922	0	0
T3	49645	213	0	0
T4	233204	776	0	0
T15	161516	6553	0	0
T17	13670	344	0	0
T18	23785	417	0	0
T19	100872	7	0	0
T20	20693	500	0	0
T21	36601	382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1527414	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1527414	0	0
T1	15161	70	0	0
T2	429842	0	0	0
T3	49645	393	0	0
T4	233204	1998	0	0
T15	161516	20564	0	0
T16	0	6	0	0
T17	13670	411	0	0
T18	23785	458	0	0
T19	100872	35	0	0
T20	20693	483	0	0
T21	36601	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	4010035	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	4010035	0	0
T1	15161	48	0	0
T2	429842	0	0	0
T3	49645	133	0	0
T4	233204	758	0	0
T15	161516	8092	0	0
T16	0	6	0	0
T17	13670	411	0	0
T18	23785	457	0	0
T19	100872	14	0	0
T20	20693	483	0	0
T21	36601	352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1476394	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1476394	0	0
T1	15161	107	0	0
T2	429842	1307	0	0
T3	49645	478	0	0
T4	233204	1711	0	0
T15	161516	24365	0	0
T17	13670	379	0	0
T18	23785	551	0	0
T19	100872	13	0	0
T20	20693	712	0	0
T21	36601	346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3871858	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3871858	0	0
T1	15161	100	0	0
T2	429842	93390	0	0
T3	49645	182	0	0
T4	233204	637	0	0
T15	161516	9611	0	0
T17	13670	379	0	0
T18	23785	551	0	0
T19	100872	3	0	0
T20	20693	712	0	0
T21	36601	333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1512281	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1512281	0	0
T1	15161	89	0	0
T2	429842	0	0	0
T3	49645	435	0	0
T4	233204	1637	0	0
T15	161516	20067	0	0
T16	0	3	0	0
T17	13670	112	0	0
T18	23785	299	0	0
T19	100872	18	0	0
T20	20693	415	0	0
T21	36601	394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	2867507	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	2867507	0	0
T1	15161	90	0	0
T2	429842	0	0	0
T3	49645	174	0	0
T4	233204	662	0	0
T15	161516	5933	0	0
T16	0	3	0	0
T17	13670	112	0	0
T18	23785	299	0	0
T19	100872	7	0	0
T20	20693	415	0	0
T21	36601	465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1499640	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1499640	0	0
T1	15161	119	0	0
T2	429842	0	0	0
T3	49645	353	0	0
T4	233204	1544	0	0
T15	161516	24052	0	0
T16	0	9	0	0
T17	13670	332	0	0
T18	23785	349	0	0
T19	100872	33	0	0
T20	20693	174	0	0
T21	36601	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3204574	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3204574	0	0
T1	15161	119	0	0
T2	429842	0	0	0
T3	49645	131	0	0
T4	233204	672	0	0
T15	161516	7508	0	0
T16	0	9	0	0
T17	13670	332	0	0
T18	23785	348	0	0
T19	100872	8	0	0
T20	20693	174	0	0
T21	36601	420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1467435	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1467435	0	0
T1	15161	79	0	0
T2	429842	1324	0	0
T3	49645	502	0	0
T4	233204	3711	0	0
T15	161516	22384	0	0
T17	13670	112	0	0
T18	23785	338	0	0
T19	100872	26	0	0
T20	20693	1202	0	0
T21	36601	401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3566115	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3566115	0	0
T1	15161	63	0	0
T2	429842	98087	0	0
T3	49645	164	0	0
T4	233204	1784	0	0
T15	161516	10894	0	0
T17	13670	112	0	0
T18	23785	338	0	0
T19	100872	5	0	0
T20	20693	1202	0	0
T21	36601	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1463601	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1463601	0	0
T1	15161	102	0	0
T2	429842	2309	0	0
T3	49645	574	0	0
T4	233204	3475	0	0
T15	161516	21322	0	0
T17	13670	407	0	0
T18	23785	542	0	0
T19	100872	39	0	0
T20	20693	711	0	0
T21	36601	507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	2989983	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	2989983	0	0
T1	15161	39	0	0
T2	429842	183585	0	0
T3	49645	210	0	0
T4	233204	1391	0	0
T15	161516	6280	0	0
T17	13670	407	0	0
T18	23785	542	0	0
T19	100872	8	0	0
T20	20693	711	0	0
T21	36601	468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1455766	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1455766	0	0
T1	15161	42	0	0
T2	429842	1405	0	0
T3	49645	457	0	0
T4	233204	5334	0	0
T15	161516	20556	0	0
T17	13670	345	0	0
T18	23785	387	0	0
T19	100872	24	0	0
T20	20693	196	0	0
T21	36601	325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3330375	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3330375	0	0
T1	15161	60	0	0
T2	429842	108512	0	0
T3	49645	191	0	0
T4	233204	2278	0	0
T15	161516	6292	0	0
T17	13670	345	0	0
T18	23785	387	0	0
T19	100872	6	0	0
T20	20693	196	0	0
T21	36601	340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1471670	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1471670	0	0
T1	15161	88	0	0
T2	429842	0	0	0
T3	49645	466	0	0
T4	233204	1468	0	0
T15	161516	22980	0	0
T16	0	10	0	0
T17	13670	113	0	0
T18	23785	304	0	0
T19	100872	35	0	0
T20	20693	217	0	0
T21	36601	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3146443	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3146443	0	0
T1	15161	56	0	0
T2	429842	0	0	0
T3	49645	162	0	0
T4	233204	673	0	0
T15	161516	7512	0	0
T16	0	10	0	0
T17	13670	113	0	0
T18	23785	304	0	0
T19	100872	9	0	0
T20	20693	217	0	0
T21	36601	398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1467393	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1467393	0	0
T1	15161	78	0	0
T2	429842	1221	0	0
T3	49645	397	0	0
T4	233204	1615	0	0
T15	161516	20085	0	0
T17	13670	115	0	0
T18	23785	303	0	0
T19	100872	52	0	0
T20	20693	183	0	0
T21	36601	362	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3082939	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3082939	0	0
T1	15161	76	0	0
T2	429842	104121	0	0
T3	49645	153	0	0
T4	233204	732	0	0
T15	161516	7384	0	0
T17	13670	115	0	0
T18	23785	303	0	0
T19	100872	10	0	0
T20	20693	183	0	0
T21	36601	398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1479160	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1479160	0	0
T1	15161	166	0	0
T2	429842	1390	0	0
T3	49645	433	0	0
T4	233204	1741	0	0
T15	161516	20159	0	0
T17	13670	375	0	0
T18	23785	329	0	0
T19	100872	53	0	0
T20	20693	195	0	0
T21	36601	455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	4124093	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	4124093	0	0
T1	15161	120	0	0
T2	429842	102247	0	0
T3	49645	170	0	0
T4	233204	737	0	0
T15	161516	7150	0	0
T17	13670	375	0	0
T18	23785	328	0	0
T19	100872	12	0	0
T20	20693	195	0	0
T21	36601	508	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1456327	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1456327	0	0
T1	15161	75	0	0
T2	429842	1005	0	0
T3	49645	586	0	0
T4	233204	1681	0	0
T15	161516	13857	0	0
T17	13670	120	0	0
T18	23785	571	0	0
T19	100872	33	0	0
T20	20693	692	0	0
T21	36601	442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	2958294	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	2958294	0	0
T1	15161	39	0	0
T2	429842	71855	0	0
T3	49645	211	0	0
T4	233204	632	0	0
T15	161516	4729	0	0
T17	13670	120	0	0
T18	23785	571	0	0
T19	100872	7	0	0
T20	20693	692	0	0
T21	36601	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1465625	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1465625	0	0
T1	15161	64	0	0
T2	429842	0	0	0
T3	49645	417	0	0
T4	233204	3673	0	0
T15	161516	19662	0	0
T16	0	4	0	0
T17	13670	313	0	0
T18	23785	322	0	0
T19	100872	8	0	0
T20	20693	200	0	0
T21	36601	384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3114696	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3114696	0	0
T1	15161	60	0	0
T2	429842	0	0	0
T3	49645	148	0	0
T4	233204	1609	0	0
T15	161516	6229	0	0
T16	0	4	0	0
T17	13670	313	0	0
T18	23785	322	0	0
T19	100872	4	0	0
T20	20693	200	0	0
T21	36601	393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1460738	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1460738	0	0
T1	15161	169	0	0
T2	429842	3294	0	0
T3	49645	390	0	0
T4	233204	3717	0	0
T15	161516	17164	0	0
T17	13670	113	0	0
T18	23785	316	0	0
T19	100872	19	0	0
T20	20693	951	0	0
T21	36601	414	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3420559	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3420559	0	0
T1	15161	112	0	0
T2	429842	258784	0	0
T3	49645	180	0	0
T4	233204	1370	0	0
T15	161516	5680	0	0
T17	13670	113	0	0
T18	23785	315	0	0
T19	100872	354	0	0
T20	20693	951	0	0
T21	36601	415	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1486957	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1486957	0	0
T1	15161	102	0	0
T2	429842	0	0	0
T3	49645	472	0	0
T4	233204	1640	0	0
T15	161516	20528	0	0
T16	0	5	0	0
T17	13670	110	0	0
T18	23785	320	0	0
T19	100872	45	0	0
T20	20693	703	0	0
T21	36601	502	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3287434	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3287434	0	0
T1	15161	84	0	0
T2	429842	0	0	0
T3	49645	213	0	0
T4	233204	807	0	0
T15	161516	7521	0	0
T16	0	5	0	0
T17	13670	110	0	0
T18	23785	320	0	0
T19	100872	7	0	0
T20	20693	703	0	0
T21	36601	486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1433266	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1433266	0	0
T1	15161	150	0	0
T2	429842	0	0	0
T3	49645	271	0	0
T4	233204	7217	0	0
T15	161516	22518	0	0
T16	0	2	0	0
T17	13670	132	0	0
T18	23785	630	0	0
T19	100872	25	0	0
T20	20693	211	0	0
T21	36601	304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	2744176	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	2744176	0	0
T1	15161	171	0	0
T2	429842	0	0	0
T3	49645	122	0	0
T4	233204	3205	0	0
T15	161516	8023	0	0
T16	0	2	0	0
T17	13670	132	0	0
T18	23785	630	0	0
T19	100872	6	0	0
T20	20693	211	0	0
T21	36601	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	1479924	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	1479924	0	0
T1	15161	96	0	0
T2	429842	1025	0	0
T3	49645	436	0	0
T4	233204	1705	0	0
T15	161516	17442	0	0
T17	13670	415	0	0
T18	23785	332	0	0
T19	100872	32	0	0
T20	20693	659	0	0
T21	36601	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317840784	3770690	0	0
DepthKnown_A	317840784	317717227	0	0
RvalidKnown_A	317840784	317717227	0	0
WreadyKnown_A	317840784	317717227	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	3770690	0	0
T1	15161	79	0	0
T2	429842	77480	0	0
T3	49645	162	0	0
T4	233204	679	0	0
T15	161516	4764	0	0
T17	13670	415	0	0
T18	23785	332	0	0
T19	100872	9	0	0
T20	20693	659	0	0
T21	36601	327	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317840784	317717227	0	0
T1	15161	15151	0	0
T2	429842	429837	0	0
T3	49645	49582	0	0
T4	233204	232161	0	0
T15	161516	161513	0	0
T17	13670	13570	0	0
T18	23785	22754	0	0
T19	100872	100789	0	0
T20	20693	20554	0	0
T21	36601	36556	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0