Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1611694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252534

1

T1

326

T2

10

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	631673	1			T1	752		T2	33		T3	3
values[0x0]	600630	1			T1	782		T2	44		T4	7
values[0x1]	631925	1			T1	781		T2	29		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1249133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615095

1

T1

748

T2

32

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7058	1			T1	16		T14	2		T11	19
valid_sources[0x01]	7873	1			T1	11		T4	2		T14	12
valid_sources[0x02]	6706	1			T1	11		T14	15		T13	4
valid_sources[0x03]	7398	1			T1	8		T14	11		T13	5
valid_sources[0x04]	6546	1			T1	10		T4	1		T14	5
valid_sources[0x05]	7103	1			T1	8		T14	4		T11	21
valid_sources[0x06]	7055	1			T1	11		T2	8		T14	2
valid_sources[0x07]	6987	1			T1	13		T2	6		T14	10
valid_sources[0x08]	6571	1			T1	8		T14	9		T13	1
valid_sources[0x09]	8002	1			T1	11		T14	10		T13	1
valid_sources[0x0a]	7646	1			T1	12		T14	9		T11	19
valid_sources[0x0b]	6657	1			T1	4		T14	2		T13	8
valid_sources[0x0c]	7104	1			T1	8		T14	18		T13	6
valid_sources[0x0d]	6524	1			T1	8		T14	4		T11	17
valid_sources[0x0e]	7768	1			T1	9		T4	1		T14	9
valid_sources[0x0f]	7537	1			T1	8		T14	7		T13	6
valid_sources[0x10]	7299	1			T1	15		T14	11		T11	21
valid_sources[0x11]	6706	1			T1	10		T14	12		T13	1
valid_sources[0x12]	7379	1			T1	11		T4	1		T14	3
valid_sources[0x13]	7147	1			T1	6		T14	15		T13	5
valid_sources[0x14]	7160	1			T1	6		T14	8		T13	4
valid_sources[0x15]	7560	1			T1	9		T14	4		T13	2
valid_sources[0x16]	7529	1			T1	8		T14	4		T13	8
valid_sources[0x17]	7170	1			T1	5		T14	9		T13	2
valid_sources[0x18]	8133	1			T1	12		T14	6		T13	4
valid_sources[0x19]	7611	1			T1	12		T4	1		T14	5
valid_sources[0x1a]	6893	1			T1	6		T14	9		T13	10
valid_sources[0x1b]	6564	1			T1	7		T14	7		T13	3
valid_sources[0x1c]	8543	1			T1	5		T14	3		T13	1
valid_sources[0x1d]	7977	1			T1	9		T14	1		T13	8
valid_sources[0x1e]	7720	1			T1	4		T14	4		T13	6
valid_sources[0x1f]	6798	1			T1	8		T2	5		T4	2
valid_sources[0x20]	6714	1			T1	8		T4	2		T14	2
valid_sources[0x21]	6881	1			T1	8		T2	14		T14	17
valid_sources[0x22]	7655	1			T1	7		T4	2		T14	6
valid_sources[0x23]	6326	1			T1	9		T2	12		T14	5
valid_sources[0x24]	8253	1			T1	8		T14	8		T13	7
valid_sources[0x25]	6095	1			T1	11		T14	12		T13	9
valid_sources[0x26]	7326	1			T1	7		T14	4		T13	1
valid_sources[0x27]	6841	1			T1	5		T14	5		T13	4
valid_sources[0x28]	7932	1			T1	9		T14	1		T13	1
valid_sources[0x29]	7405	1			T1	9		T4	1		T14	8
valid_sources[0x2a]	6598	1			T1	14		T14	16		T13	1
valid_sources[0x2b]	6836	1			T1	11		T4	2		T14	14
valid_sources[0x2c]	7152	1			T1	7		T14	7		T11	21
valid_sources[0x2d]	7400	1			T1	13		T2	11		T14	5
valid_sources[0x2e]	7146	1			T1	7		T4	2		T14	5
valid_sources[0x2f]	7278	1			T1	11		T4	1		T14	7
valid_sources[0x30]	6972	1			T1	7		T14	1		T13	4
valid_sources[0x31]	9009	1			T1	14		T14	2		T13	1
valid_sources[0x32]	7378	1			T1	6		T14	2		T13	4
valid_sources[0x33]	8042	1			T1	14		T13	1		T11	18
valid_sources[0x34]	7473	1			T1	5		T14	6		T13	4
valid_sources[0x35]	7142	1			T1	5		T14	10		T11	22
valid_sources[0x36]	7172	1			T1	14		T14	27		T13	6
valid_sources[0x37]	8634	1			T1	9		T4	1		T14	2
valid_sources[0x38]	7605	1			T1	8		T14	3		T13	4
valid_sources[0x39]	6407	1			T1	2		T14	11		T13	3
valid_sources[0x3a]	7112	1			T1	11		T14	29		T13	1
valid_sources[0x3b]	7813	1			T1	9		T14	10		T13	5
valid_sources[0x3c]	7619	1			T1	12		T14	11		T13	1
valid_sources[0x3d]	7390	1			T1	17		T14	17		T13	7
valid_sources[0x3e]	6536	1			T1	4		T14	4		T13	7
valid_sources[0x3f]	7415	1			T1	5		T14	5		T13	3
valid_sources[0x40]	7292	1			T1	13		T4	1		T14	10
valid_sources[0x41]	7138	1			T1	6		T14	6		T13	1
valid_sources[0x42]	6588	1			T1	11		T13	4		T11	20
valid_sources[0x43]	7795	1			T1	8		T14	8		T13	5
valid_sources[0x44]	7574	1			T1	9		T2	6		T14	2
valid_sources[0x45]	6941	1			T1	11		T14	13		T13	5
valid_sources[0x46]	7633	1			T1	10		T14	11		T13	2
valid_sources[0x47]	7938	1			T1	8		T14	1		T13	1
valid_sources[0x48]	7097	1			T1	13		T14	2		T13	3
valid_sources[0x49]	7564	1			T1	15		T4	1		T14	6
valid_sources[0x4a]	7335	1			T1	9		T4	1		T14	6
valid_sources[0x4b]	7521	1			T1	9		T14	11		T13	4
valid_sources[0x4c]	6662	1			T1	12		T14	4		T13	6
valid_sources[0x4d]	7439	1			T1	9		T14	5		T13	2
valid_sources[0x4e]	7795	1			T1	10		T4	1		T14	2
valid_sources[0x4f]	6989	1			T1	14		T14	3		T13	3
valid_sources[0x50]	7682	1			T1	8		T14	14		T11	21
valid_sources[0x51]	6518	1			T1	7		T14	6		T13	2
valid_sources[0x52]	7117	1			T1	18		T14	5		T13	15
valid_sources[0x53]	7004	1			T1	17		T3	3		T4	1
valid_sources[0x54]	7903	1			T1	4		T4	2		T14	2
valid_sources[0x55]	7688	1			T1	9		T4	1		T14	20
valid_sources[0x56]	7319	1			T1	6		T14	7		T15	6
valid_sources[0x57]	6716	1			T1	9		T3	1		T14	19
valid_sources[0x58]	6799	1			T1	2		T4	1		T14	26
valid_sources[0x59]	7381	1			T1	18		T4	3		T14	1
valid_sources[0x5a]	6813	1			T1	6		T14	4		T13	4
valid_sources[0x5b]	6793	1			T1	11		T4	1		T14	10
valid_sources[0x5c]	7796	1			T1	4		T14	11		T13	1
valid_sources[0x5d]	6832	1			T1	4		T2	17		T14	5
valid_sources[0x5e]	8232	1			T1	11		T4	1		T14	11
valid_sources[0x5f]	7258	1			T1	6		T14	17		T13	1
valid_sources[0x60]	7229	1			T1	11		T4	1		T14	4
valid_sources[0x61]	6378	1			T1	9		T14	10		T13	5
valid_sources[0x62]	6676	1			T1	11		T14	14		T13	7
valid_sources[0x63]	8111	1			T1	6		T14	8		T13	5
valid_sources[0x64]	7089	1			T1	4		T14	3		T13	4
valid_sources[0x65]	7740	1			T1	7		T4	1		T14	7
valid_sources[0x66]	7270	1			T1	4		T14	27		T13	3
valid_sources[0x67]	7042	1			T1	9		T14	19		T13	1
valid_sources[0x68]	6465	1			T1	8		T14	8		T13	7
valid_sources[0x69]	7534	1			T1	14		T14	7		T13	2
valid_sources[0x6a]	7499	1			T1	8		T14	22		T13	2
valid_sources[0x6b]	8259	1			T1	10		T14	4		T13	2
valid_sources[0x6c]	8156	1			T1	14		T14	9		T13	2
valid_sources[0x6d]	7098	1			T1	8		T14	10		T13	3
valid_sources[0x6e]	6553	1			T1	4		T14	15		T13	6
valid_sources[0x6f]	6993	1			T1	4		T14	6		T13	2
valid_sources[0x70]	7029	1			T1	4		T4	1		T14	13
valid_sources[0x71]	7057	1			T1	12		T14	8		T13	3
valid_sources[0x72]	6799	1			T1	6		T14	12		T13	2
valid_sources[0x73]	6749	1			T1	8		T2	6		T14	1
valid_sources[0x74]	7094	1			T1	6		T4	1		T14	30
valid_sources[0x75]	6764	1			T1	6		T14	17		T11	18
valid_sources[0x76]	6171	1			T1	6		T14	6		T13	7
valid_sources[0x77]	6712	1			T1	3		T14	12		T13	1
valid_sources[0x78]	6978	1			T1	7		T14	7		T13	2
valid_sources[0x79]	7308	1			T1	9		T14	10		T13	4
valid_sources[0x7a]	7610	1			T1	10		T14	6		T13	2
valid_sources[0x7b]	6812	1			T1	7		T4	1		T14	25
valid_sources[0x7c]	7472	1			T1	7		T14	8		T13	4
valid_sources[0x7d]	7689	1			T1	15		T14	13		T13	6
valid_sources[0x7e]	7509	1			T1	7		T14	10		T13	5
valid_sources[0x7f]	6580	1			T1	9		T14	2		T13	6
valid_sources[0x80]	6512	1			T1	17		T4	1		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26677

1

T1

29

T4

2

T14

26

values[0x0]

all_enables

biggest_size

199279

1

T1

271

T2

10

T4

3

values[0x1]

all_enables

biggest_size

26578

1

T1

26

T4

3

T14

34