Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	353978424	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353978424	0	0
T1	16140488	2512963	0	0
T2	3115000	55371	0	0
T3	211960	4004	0	0
T4	205240	6956	0	0
T10	10044944	197609	0	0
T11	24007984	2020511	0	0
T13	26441688	474029	0	0
T14	6325816	133253	0	0
T15	10754016	256119	0	0
T16	1178408	17676	0	0
T17	0	23238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16140488	16140096	0	0
T2	3115000	3112480	0	0
T3	211960	204512	0	0
T4	205240	201488	0	0
T10	10044944	10042816	0	0
T11	24007984	24007872	0	0
T13	26441688	26437656	0	0
T14	6325816	6325536	0	0
T15	10754016	10752672	0	0
T16	1178408	1176504	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16140488	16140096	0	0
T2	3115000	3112480	0	0
T3	211960	204512	0	0
T4	205240	201488	0	0
T10	10044944	10042816	0	0
T11	24007984	24007872	0	0
T13	26441688	26437656	0	0
T14	6325816	6325536	0	0
T15	10754016	10752672	0	0
T16	1178408	1176504	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16140488	16140096	0	0
T2	3115000	3112480	0	0
T3	211960	204512	0	0
T4	205240	201488	0	0
T10	10044944	10042816	0	0
T11	24007984	24007872	0	0
T13	26441688	26437656	0	0
T14	6325816	6325536	0	0
T15	10754016	10752672	0	0
T16	1178408	1176504	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T10	56	56	0	0
T11	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	123929755	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	123929755	0	0
T1	288223	163571	0	0
T2	55625	53716	0	0
T3	3785	1822	0	0
T4	3665	3184	0	0
T10	179374	84800	0	0
T11	428714	22989	0	0
T13	472173	461158	0	0
T14	112961	110618	0	0
T15	192036	102727	0	0
T16	21043	4370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	96093361	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	96093361	0	0
T1	288223	784115	0	0
T2	55625	606	0	0
T3	3785	512	0	0
T4	3665	1878	0	0
T10	179374	33276	0	0
T11	428714	179503	0	0
T13	472173	4371	0	0
T14	112961	6532	0	0
T15	192036	54034	0	0
T16	21043	4471	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1474416	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1474416	0	0
T1	288223	31393	0	0
T2	55625	3	0	0
T3	3785	54	0	0
T4	3665	37	0	0
T10	179374	1237	0	0
T11	428714	2386	0	0
T13	472173	134	0	0
T14	112961	377	0	0
T15	192036	2181	0	0
T16	21043	126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	4016560	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	4016560	0	0
T1	288223	31818	0	0
T2	55625	2	0	0
T3	3785	12	0	0
T4	3665	37	0	0
T10	179374	1534	0	0
T11	428714	183511	0	0
T13	472173	35	0	0
T14	112961	834	0	0
T15	192036	692	0	0
T16	21043	143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1500123	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1500123	0	0
T1	288223	28086	0	0
T2	55625	8	0	0
T3	3785	44	0	0
T4	3665	46	0	0
T10	179374	3348	0	0
T11	428714	0	0	0
T13	472173	167	0	0
T14	112961	374	0	0
T15	192036	1066	0	0
T16	21043	106	0	0
T17	0	846	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	4188949	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	4188949	0	0
T1	288223	28463	0	0
T2	55625	1	0	0
T3	3785	17	0	0
T4	3665	46	0	0
T10	179374	1182	0	0
T11	428714	0	0	0
T13	472173	38	0	0
T14	112961	89	0	0
T15	192036	2785	0	0
T16	21043	136	0	0
T17	0	808	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1461315	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1461315	0	0
T1	288223	26170	0	0
T2	55625	30	0	0
T3	3785	56	0	0
T4	3665	33	0	0
T10	179374	829	0	0
T11	428714	0	0	0
T13	472173	185	0	0
T14	112961	346	0	0
T15	192036	1219	0	0
T16	21043	98	0	0
T17	0	869	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3401365	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3401365	0	0
T1	288223	32428	0	0
T2	55625	5	0	0
T3	3785	17	0	0
T4	3665	33	0	0
T10	179374	735	0	0
T11	428714	0	0	0
T13	472173	48	0	0
T14	112961	82	0	0
T15	192036	1321	0	0
T16	21043	104	0	0
T17	0	864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1421347	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1421347	0	0
T1	288223	27408	0	0
T2	55625	20	0	0
T3	3785	21	0	0
T4	3665	33	0	0
T10	179374	1451	0	0
T11	428714	0	0	0
T13	472173	115	0	0
T14	112961	337	0	0
T15	192036	425	0	0
T16	21043	142	0	0
T17	0	816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3730680	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3730680	0	0
T1	288223	30608	0	0
T2	55625	7	0	0
T3	3785	7	0	0
T4	3665	33	0	0
T10	179374	1477	0	0
T11	428714	0	0	0
T13	472173	31	0	0
T14	112961	77	0	0
T15	192036	1576	0	0
T16	21043	142	0	0
T17	0	700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1458988	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1458988	0	0
T1	288223	27394	0	0
T2	55625	8	0	0
T3	3785	5	0	0
T4	3665	27	0	0
T10	179374	2030	0	0
T11	428714	1059	0	0
T13	472173	84	0	0
T14	112961	322	0	0
T15	192036	3792	0	0
T16	21043	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	2878107	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	2878107	0	0
T1	288223	27515	0	0
T2	55625	4	0	0
T3	3785	14	0	0
T4	3665	27	0	0
T10	179374	861	0	0
T11	428714	92606	0	0
T13	472173	24	0	0
T14	112961	75	0	0
T15	192036	2828	0	0
T16	21043	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1461715	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1461715	0	0
T1	288223	27820	0	0
T2	55625	23	0	0
T3	3785	63	0	0
T4	3665	35	0	0
T10	179374	92	0	0
T11	428714	0	0	0
T13	472173	131	0	0
T14	112961	328	0	0
T15	192036	1347	0	0
T16	21043	216	0	0
T17	0	768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3398141	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3398141	0	0
T1	288223	27924	0	0
T2	55625	5	0	0
T3	3785	34	0	0
T4	3665	35	0	0
T10	179374	134	0	0
T11	428714	0	0	0
T13	472173	34	0	0
T14	112961	270	0	0
T15	192036	297	0	0
T16	21043	218	0	0
T17	0	861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1426778	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1426778	0	0
T1	288223	29767	0	0
T2	55625	1	0	0
T3	3785	45	0	0
T4	3665	49	0	0
T10	179374	2986	0	0
T11	428714	1437	0	0
T13	472173	139	0	0
T14	112961	334	0	0
T15	192036	565	0	0
T16	21043	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3227632	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3227632	0	0
T1	288223	27270	0	0
T2	55625	1	0	0
T3	3785	37	0	0
T4	3665	49	0	0
T10	179374	1365	0	0
T11	428714	111737	0	0
T13	472173	39	0	0
T14	112961	73	0	0
T15	192036	2021	0	0
T16	21043	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1431441	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1431441	0	0
T1	288223	22819	0	0
T2	55625	27	0	0
T3	3785	52	0	0
T4	3665	37	0	0
T10	179374	2550	0	0
T11	428714	0	0	0
T13	472173	134	0	0
T14	112961	461	0	0
T15	192036	4862	0	0
T16	21043	129	0	0
T17	0	764	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	4035687	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	4035687	0	0
T1	288223	24661	0	0
T2	55625	8	0	0
T3	3785	26	0	0
T4	3665	37	0	0
T10	179374	2191	0	0
T11	428714	0	0	0
T13	472173	34	0	0
T14	112961	610	0	0
T15	192036	5460	0	0
T16	21043	166	0	0
T17	0	824	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1451531	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1451531	0	0
T1	288223	27409	0	0
T2	55625	36	0	0
T3	3785	69	0	0
T4	3665	31	0	0
T10	179374	890	0	0
T11	428714	0	0	0
T13	472173	195	0	0
T14	112961	369	0	0
T15	192036	1493	0	0
T16	21043	155	0	0
T17	0	854	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	2736922	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	2736922	0	0
T1	288223	26095	0	0
T2	55625	7	0	0
T3	3785	31	0	0
T4	3665	31	0	0
T10	179374	1058	0	0
T11	428714	0	0	0
T13	472173	39	0	0
T14	112961	310	0	0
T15	192036	1704	0	0
T16	21043	135	0	0
T17	0	765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1450767	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1450767	0	0
T1	288223	30762	0	0
T2	55625	17	0	0
T3	3785	14	0	0
T4	3665	24	0	0
T10	179374	1579	0	0
T11	428714	0	0	0
T13	472173	116	0	0
T14	112961	317	0	0
T15	192036	862	0	0
T16	21043	239	0	0
T17	0	708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	2936193	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	2936193	0	0
T1	288223	27057	0	0
T2	55625	4	0	0
T3	3785	3	0	0
T4	3665	24	0	0
T10	179374	1652	0	0
T11	428714	0	0	0
T13	472173	28	0	0
T14	112961	873	0	0
T15	192036	1403	0	0
T16	21043	228	0	0
T17	0	757	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1400104	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1400104	0	0
T1	288223	29056	0	0
T2	55625	11	0	0
T3	3785	38	0	0
T4	3665	32	0	0
T10	179374	519	0	0
T11	428714	2435	0	0
T13	472173	178	0	0
T14	112961	259	0	0
T15	192036	157	0	0
T16	21043	140	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3661965	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3661965	0	0
T1	288223	24975	0	0
T2	55625	5	0	0
T3	3785	25	0	0
T4	3665	32	0	0
T10	179374	927	0	0
T11	428714	181400	0	0
T13	472173	38	0	0
T14	112961	59	0	0
T15	192036	1974	0	0
T16	21043	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1440270	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1440270	0	0
T1	288223	25377	0	0
T2	55625	8	0	0
T3	3785	69	0	0
T4	3665	46	0	0
T10	179374	1947	0	0
T11	428714	2285	0	0
T13	472173	146	0	0
T14	112961	384	0	0
T15	192036	1804	0	0
T16	21043	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3722766	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3722766	0	0
T1	288223	31362	0	0
T2	55625	2	0	0
T3	3785	24	0	0
T4	3665	46	0	0
T10	179374	1859	0	0
T11	428714	182600	0	0
T13	472173	28	0	0
T14	112961	92	0	0
T15	192036	2706	0	0
T16	21043	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1451508	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1451508	0	0
T1	288223	26258	0	0
T2	55625	10	0	0
T3	3785	29	0	0
T4	3665	37	0	0
T10	179374	909	0	0
T11	428714	0	0	0
T13	472173	154	0	0
T14	112961	409	0	0
T15	192036	1000	0	0
T16	21043	158	0	0
T17	0	878	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3695101	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3695101	0	0
T1	288223	26751	0	0
T2	55625	3	0	0
T3	3785	12	0	0
T4	3665	37	0	0
T10	179374	1606	0	0
T11	428714	0	0	0
T13	472173	38	0	0
T14	112961	83	0	0
T15	192036	1909	0	0
T16	21043	171	0	0
T17	0	756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1442603	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1442603	0	0
T1	288223	26951	0	0
T2	55625	37	0	0
T3	3785	31	0	0
T4	3665	29	0	0
T10	179374	2449	0	0
T11	428714	0	0	0
T13	472173	137	0	0
T14	112961	254	0	0
T15	192036	2470	0	0
T16	21043	246	0	0
T17	0	961	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3383434	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3383434	0	0
T1	288223	29113	0	0
T2	55625	6	0	0
T3	3785	9	0	0
T4	3665	29	0	0
T10	179374	2341	0	0
T11	428714	0	0	0
T13	472173	41	0	0
T14	112961	122	0	0
T15	192036	2309	0	0
T16	21043	209	0	0
T17	0	891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1449452	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1449452	0	0
T1	288223	21578	0	0
T2	55625	36	0	0
T3	3785	33	0	0
T4	3665	28	0	0
T10	179374	3521	0	0
T11	428714	1173	0	0
T13	472173	155	0	0
T14	112961	278	0	0
T15	192036	3105	0	0
T16	21043	214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3641856	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3641856	0	0
T1	288223	23627	0	0
T2	55625	6	0	0
T3	3785	17	0	0
T4	3665	28	0	0
T10	179374	1250	0	0
T11	428714	91836	0	0
T13	472173	36	0	0
T14	112961	70	0	0
T15	192036	3945	0	0
T16	21043	190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1416630	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1416630	0	0
T1	288223	31588	0	0
T2	55625	22	0	0
T3	3785	64	0	0
T4	3665	34	0	0
T10	179374	1529	0	0
T11	428714	944	0	0
T13	472173	130	0	0
T14	112961	392	0	0
T15	192036	415	0	0
T16	21043	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3187095	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3187095	0	0
T1	288223	35926	0	0
T2	55625	4	0	0
T3	3785	11	0	0
T4	3665	34	0	0
T10	179374	1492	0	0
T11	428714	85418	0	0
T13	472173	28	0	0
T14	112961	85	0	0
T15	192036	1619	0	0
T16	21043	143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1445480	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1445480	0	0
T1	288223	28802	0	0
T2	55625	27	0	0
T3	3785	63	0	0
T4	3665	51	0	0
T10	179374	1519	0	0
T11	428714	3916	0	0
T13	472173	122	0	0
T14	112961	328	0	0
T15	192036	1381	0	0
T16	21043	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3373580	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3373580	0	0
T1	288223	29034	0	0
T2	55625	4	0	0
T3	3785	28	0	0
T4	3665	51	0	0
T10	179374	1061	0	0
T11	428714	305570	0	0
T13	472173	425	0	0
T14	112961	218	0	0
T15	192036	1049	0	0
T16	21043	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1449373	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1449373	0	0
T1	288223	38984	0	0
T2	55625	7	0	0
T3	3785	63	0	0
T4	3665	28	0	0
T10	179374	474	0	0
T11	428714	0	0	0
T13	472173	193	0	0
T14	112961	304	0	0
T15	192036	1257	0	0
T16	21043	170	0	0
T17	0	865	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3367011	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3367011	0	0
T1	288223	32914	0	0
T2	55625	501	0	0
T3	3785	28	0	0
T4	3665	28	0	0
T10	179374	1	0	0
T11	428714	0	0	0
T13	472173	47	0	0
T14	112961	72	0	0
T15	192036	1603	0	0
T16	21043	179	0	0
T17	0	852	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1433909	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1433909	0	0
T1	288223	25613	0	0
T2	55625	8	0	0
T3	3785	52	0	0
T4	3665	39	0	0
T10	179374	1473	0	0
T11	428714	997	0	0
T13	472173	159	0	0
T14	112961	322	0	0
T15	192036	3243	0	0
T16	21043	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	4388340	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	4388340	0	0
T1	288223	24885	0	0
T2	55625	3	0	0
T3	3785	22	0	0
T4	3665	39	0	0
T10	179374	2377	0	0
T11	428714	78743	0	0
T13	472173	34	0	0
T14	112961	337	0	0
T15	192036	2117	0	0
T16	21043	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1428588	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1428588	0	0
T1	288223	34956	0	0
T2	55625	7	0	0
T3	3785	40	0	0
T4	3665	34	0	0
T10	179374	2073	0	0
T11	428714	0	0	0
T13	472173	153	0	0
T14	112961	365	0	0
T15	192036	2218	0	0
T16	21043	235	0	0
T17	0	1099	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3048491	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3048491	0	0
T1	288223	35056	0	0
T2	55625	2	0	0
T3	3785	27	0	0
T4	3665	34	0	0
T10	179374	686	0	0
T11	428714	0	0	0
T13	472173	32	0	0
T14	112961	86	0	0
T15	192036	2297	0	0
T16	21043	155	0	0
T17	0	947	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1442278	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1442278	0	0
T1	288223	30163	0	0
T2	55625	21	0	0
T3	3785	35	0	0
T4	3665	33	0	0
T10	179374	935	0	0
T11	428714	1072	0	0
T13	472173	230	0	0
T14	112961	373	0	0
T15	192036	2677	0	0
T16	21043	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3298299	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3298299	0	0
T1	288223	28203	0	0
T2	55625	5	0	0
T3	3785	15	0	0
T4	3665	33	0	0
T10	179374	340	0	0
T11	428714	80128	0	0
T13	472173	1917	0	0
T14	112961	1054	0	0
T15	192036	2648	0	0
T16	21043	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1419157	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1419157	0	0
T1	288223	30543	0	0
T2	55625	23	0	0
T3	3785	50	0	0
T4	3665	30	0	0
T10	179374	2483	0	0
T11	428714	0	0	0
T13	472173	99	0	0
T14	112961	376	0	0
T15	192036	1126	0	0
T16	21043	203	0	0
T17	0	813	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3164026	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3164026	0	0
T1	288223	29464	0	0
T2	55625	4	0	0
T3	3785	18	0	0
T4	3665	30	0	0
T10	179374	1538	0	0
T11	428714	0	0	0
T13	472173	21	0	0
T14	112961	136	0	0
T15	192036	2074	0	0
T16	21043	170	0	0
T17	0	766	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1445930	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1445930	0	0
T1	288223	29793	0	0
T2	55625	19	0	0
T3	3785	46	0	0
T4	3665	45	0	0
T10	179374	2795	0	0
T11	428714	0	0	0
T13	472173	196	0	0
T14	112961	403	0	0
T15	192036	110	0	0
T16	21043	126	0	0
T17	0	772	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3343366	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3343366	0	0
T1	288223	28257	0	0
T2	55625	4	0	0
T3	3785	14	0	0
T4	3665	45	0	0
T10	179374	856	0	0
T11	428714	0	0	0
T13	472173	1164	0	0
T14	112961	251	0	0
T15	192036	949	0	0
T16	21043	174	0	0
T17	0	650	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1410080	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1410080	0	0
T1	288223	34851	0	0
T2	55625	8	0	0
T3	3785	8	0	0
T4	3665	24	0	0
T10	179374	920	0	0
T11	428714	1265	0	0
T13	472173	160	0	0
T14	112961	369	0	0
T15	192036	600	0	0
T16	21043	255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3046525	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3046525	0	0
T1	288223	35247	0	0
T2	55625	3	0	0
T3	3785	3	0	0
T4	3665	24	0	0
T10	179374	277	0	0
T11	428714	100159	0	0
T13	472173	59	0	0
T14	112961	315	0	0
T15	192036	1266	0	0
T16	21043	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1449574	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1449574	0	0
T1	288223	24430	0	0
T2	55625	5	0	0
T3	3785	46	0	0
T4	3665	26	0	0
T10	179374	2005	0	0
T11	428714	1298	0	0
T13	472173	102	0	0
T14	112961	394	0	0
T15	192036	2039	0	0
T16	21043	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	3770470	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	3770470	0	0
T1	288223	22153	0	0
T2	55625	3	0	0
T3	3785	22	0	0
T4	3665	26	0	0
T10	179374	1279	0	0
T11	428714	97131	0	0
T13	472173	23	0	0
T14	112961	86	0	0
T15	192036	2092	0	0
T16	21043	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1425145	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1425145	0	0
T1	288223	32431	0	0
T2	55625	12	0	0
T3	3785	56	0	0
T4	3665	42	0	0
T10	179374	1514	0	0
T11	428714	0	0	0
T13	472173	173	0	0
T14	112961	391	0	0
T15	192036	1663	0	0
T16	21043	155	0	0
T17	0	907	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	4184917	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	4184917	0	0
T1	288223	32275	0	0
T2	55625	3	0	0
T3	3785	33	0	0
T4	3665	42	0	0
T10	179374	1589	0	0
T11	428714	0	0	0
T13	472173	33	0	0
T14	112961	79	0	0
T15	192036	847	0	0
T16	21043	154	0	0
T17	0	877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	1470127	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	1470127	0	0
T1	288223	31064	0	0
T2	55625	9	0	0
T3	3785	16	0	0
T4	3665	37	0	0
T10	179374	2200	0	0
T11	428714	2721	0	0
T13	472173	242	0	0
T14	112961	405	0	0
T15	192036	2247	0	0
T16	21043	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	323459694	4169201	0	0
DepthKnown_A	323459694	323339165	0	0
RvalidKnown_A	323459694	323339165	0	0
WreadyKnown_A	323459694	323339165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	4169201	0	0
T1	288223	30730	0	0
T2	55625	4	0	0
T3	3785	2	0	0
T4	3665	37	0	0
T10	179374	1608	0	0
T11	428714	204192	0	0
T13	472173	57	0	0
T14	112961	94	0	0
T15	192036	2543	0	0
T16	21043	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323459694	323339165	0	0
T1	288223	288216	0	0
T2	55625	55580	0	0
T3	3785	3652	0	0
T4	3665	3598	0	0
T10	179374	179336	0	0
T11	428714	428712	0	0
T13	472173	472101	0	0
T14	112961	112956	0	0
T15	192036	192012	0	0
T16	21043	21009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0