Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1766378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

277846

1

T1

9

T2

342

T3

502

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	690742	1			T1	29		T2	869		T3	1274
values[0x0]	662309	1			T1	4		T2	809		T3	1202
values[0x1]	691173	1			T1	56		T2	780		T3	1328

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1368305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

675919

1

T1

34

T2

836

T3

1243

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7741	1			T2	10		T3	11		T4	5
valid_sources[0x01]	7122	1			T2	10		T3	2		T14	11
valid_sources[0x02]	9514	1			T2	8		T3	33		T14	4
valid_sources[0x03]	7773	1			T2	7		T3	9		T4	8
valid_sources[0x04]	9239	1			T2	9		T3	11		T4	30
valid_sources[0x05]	7964	1			T2	7		T3	13		T14	16
valid_sources[0x06]	7291	1			T2	8		T3	17		T4	16
valid_sources[0x07]	8558	1			T2	13		T3	10		T14	23
valid_sources[0x08]	7811	1			T2	10		T3	12		T13	1
valid_sources[0x09]	8965	1			T2	16		T3	11		T14	11
valid_sources[0x0a]	7692	1			T2	15		T3	16		T13	1
valid_sources[0x0b]	7174	1			T2	9		T3	21		T4	18
valid_sources[0x0c]	7364	1			T2	8		T4	6		T16	2
valid_sources[0x0d]	7462	1			T2	8		T3	17		T14	9
valid_sources[0x0e]	8756	1			T2	8		T3	4		T13	1
valid_sources[0x0f]	8335	1			T2	6		T3	50		T13	2
valid_sources[0x10]	7987	1			T2	13		T3	20		T4	6
valid_sources[0x11]	7725	1			T2	10		T3	9		T16	1
valid_sources[0x12]	7919	1			T2	10		T3	7		T13	1
valid_sources[0x13]	8464	1			T2	5		T3	24		T4	53
valid_sources[0x14]	7890	1			T2	11		T3	11		T16	1
valid_sources[0x15]	8249	1			T2	6		T3	37		T16	2
valid_sources[0x16]	7446	1			T2	14		T3	13		T13	1
valid_sources[0x17]	8815	1			T2	8		T3	53		T4	7
valid_sources[0x18]	7615	1			T2	15		T3	6		T4	3
valid_sources[0x19]	7917	1			T2	6		T3	5		T14	14
valid_sources[0x1a]	7955	1			T2	13		T3	3		T13	1
valid_sources[0x1b]	7091	1			T2	9		T3	6		T4	4
valid_sources[0x1c]	7875	1			T2	6		T3	48		T14	13
valid_sources[0x1d]	9411	1			T2	14		T16	1		T14	21
valid_sources[0x1e]	8290	1			T2	4		T3	18		T13	1
valid_sources[0x1f]	8173	1			T2	11		T3	16		T4	2
valid_sources[0x20]	8256	1			T2	14		T3	1		T13	2
valid_sources[0x21]	7335	1			T2	8		T4	9		T16	1
valid_sources[0x22]	7842	1			T2	12		T3	4		T4	10
valid_sources[0x23]	7565	1			T2	6		T3	19		T4	3
valid_sources[0x24]	9155	1			T1	3		T2	9		T3	6
valid_sources[0x25]	8568	1			T2	7		T3	9		T4	11
valid_sources[0x26]	8378	1			T2	6		T3	33		T14	20
valid_sources[0x27]	8123	1			T2	15		T3	3		T4	1
valid_sources[0x28]	8644	1			T2	3		T3	12		T14	10
valid_sources[0x29]	8231	1			T2	10		T3	8		T4	6
valid_sources[0x2a]	7901	1			T2	11		T3	16		T16	2
valid_sources[0x2b]	8972	1			T2	9		T3	18		T4	16
valid_sources[0x2c]	7922	1			T2	6		T3	9		T16	1
valid_sources[0x2d]	8191	1			T2	10		T3	12		T14	15
valid_sources[0x2e]	7473	1			T2	7		T3	4		T13	1
valid_sources[0x2f]	8156	1			T2	8		T3	29		T14	8
valid_sources[0x30]	9338	1			T2	9		T3	10		T13	1
valid_sources[0x31]	7149	1			T2	12		T3	8		T14	15
valid_sources[0x32]	7711	1			T2	11		T3	15		T14	12
valid_sources[0x33]	9724	1			T1	2		T2	9		T3	18
valid_sources[0x34]	7952	1			T2	16		T3	41		T14	16
valid_sources[0x35]	7202	1			T2	7		T3	11		T14	19
valid_sources[0x36]	7571	1			T2	12		T3	40		T14	20
valid_sources[0x37]	7670	1			T2	9		T3	27		T16	1
valid_sources[0x38]	8183	1			T2	9		T3	7		T13	2
valid_sources[0x39]	7994	1			T1	3		T2	9		T3	31
valid_sources[0x3a]	7687	1			T1	5		T2	9		T3	13
valid_sources[0x3b]	7348	1			T2	7		T3	1		T16	1
valid_sources[0x3c]	7602	1			T2	11		T3	33		T14	6
valid_sources[0x3d]	8815	1			T2	11		T3	25		T4	10
valid_sources[0x3e]	8504	1			T2	16		T3	29		T4	28
valid_sources[0x3f]	7472	1			T2	10		T3	33		T14	12
valid_sources[0x40]	7630	1			T2	9		T3	6		T4	2
valid_sources[0x41]	7793	1			T2	12		T3	28		T13	2
valid_sources[0x42]	8070	1			T2	9		T3	34		T4	12
valid_sources[0x43]	7282	1			T2	11		T3	17		T14	13
valid_sources[0x44]	8467	1			T2	11		T3	4		T14	5
valid_sources[0x45]	7725	1			T2	8		T3	13		T16	1
valid_sources[0x46]	7475	1			T2	11		T3	4		T14	7
valid_sources[0x47]	7909	1			T1	1		T2	11		T3	11
valid_sources[0x48]	7530	1			T2	11		T3	1		T13	1
valid_sources[0x49]	7474	1			T2	8		T3	21		T13	1
valid_sources[0x4a]	8301	1			T2	9		T3	10		T13	1
valid_sources[0x4b]	9667	1			T2	9		T3	20		T13	2
valid_sources[0x4c]	7700	1			T1	4		T2	9		T3	12
valid_sources[0x4d]	7839	1			T2	7		T3	13		T16	1
valid_sources[0x4e]	8151	1			T2	14		T3	5		T14	15
valid_sources[0x4f]	8218	1			T2	11		T3	25		T13	1
valid_sources[0x50]	7539	1			T2	5		T3	1		T14	9
valid_sources[0x51]	7738	1			T2	10		T3	8		T4	2
valid_sources[0x52]	7884	1			T2	13		T3	25		T16	1
valid_sources[0x53]	7748	1			T2	11		T3	57		T4	1
valid_sources[0x54]	7874	1			T2	6		T3	3		T4	2
valid_sources[0x55]	7314	1			T1	3		T2	6		T3	22
valid_sources[0x56]	7529	1			T2	12		T3	10		T4	2
valid_sources[0x57]	7906	1			T2	13		T3	29		T4	7
valid_sources[0x58]	8129	1			T2	7		T3	5		T4	7
valid_sources[0x59]	7653	1			T1	1		T2	12		T3	39
valid_sources[0x5a]	9680	1			T2	12		T3	44		T14	17
valid_sources[0x5b]	7512	1			T1	2		T2	15		T3	30
valid_sources[0x5c]	9047	1			T2	13		T3	15		T16	1
valid_sources[0x5d]	7381	1			T2	9		T3	10		T16	1
valid_sources[0x5e]	7834	1			T2	6		T3	20		T4	4
valid_sources[0x5f]	8137	1			T2	6		T3	10		T16	1
valid_sources[0x60]	7452	1			T2	12		T3	4		T13	1
valid_sources[0x61]	8312	1			T2	9		T4	4		T16	1
valid_sources[0x62]	7897	1			T2	14		T13	4		T14	23
valid_sources[0x63]	8631	1			T2	12		T3	18		T14	6
valid_sources[0x64]	7880	1			T2	8		T3	2		T14	22
valid_sources[0x65]	7722	1			T2	5		T3	15		T16	1
valid_sources[0x66]	7960	1			T2	7		T3	14		T4	6
valid_sources[0x67]	7185	1			T1	3		T2	9		T3	20
valid_sources[0x68]	8095	1			T2	10		T3	7		T4	4
valid_sources[0x69]	8018	1			T1	1		T2	13		T3	6
valid_sources[0x6a]	8192	1			T2	8		T3	18		T16	3
valid_sources[0x6b]	7574	1			T2	9		T3	13		T14	19
valid_sources[0x6c]	7892	1			T2	10		T3	28		T4	7
valid_sources[0x6d]	8318	1			T2	11		T3	3		T4	3
valid_sources[0x6e]	7750	1			T1	3		T2	8		T3	35
valid_sources[0x6f]	10330	1			T2	12		T3	4		T4	19
valid_sources[0x70]	7167	1			T2	7		T3	17		T14	10
valid_sources[0x71]	8107	1			T2	11		T16	2		T14	16
valid_sources[0x72]	7542	1			T2	6		T3	9		T16	2
valid_sources[0x73]	8254	1			T2	8		T3	3		T14	11
valid_sources[0x74]	7878	1			T2	12		T3	3		T4	3
valid_sources[0x75]	7306	1			T2	12		T3	14		T4	8
valid_sources[0x76]	8646	1			T1	9		T2	11		T3	25
valid_sources[0x77]	7980	1			T2	2		T3	17		T16	2
valid_sources[0x78]	8860	1			T2	11		T3	12		T4	8
valid_sources[0x79]	7933	1			T2	5		T3	12		T4	17
valid_sources[0x7a]	8089	1			T2	10		T14	16		T17	35
valid_sources[0x7b]	8294	1			T2	3		T3	13		T16	2
valid_sources[0x7c]	9259	1			T2	12		T3	20		T14	20
valid_sources[0x7d]	7232	1			T2	8		T3	16		T14	5
valid_sources[0x7e]	7595	1			T2	8		T3	19		T4	22
valid_sources[0x7f]	7904	1			T2	15		T3	28		T16	1
valid_sources[0x80]	8238	1			T2	14		T3	23		T14	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29203

1

T1

1

T2

32

T3

44

values[0x0]

all_enables

biggest_size

219508

1

T1

2

T2

282

T3

408

values[0x1]

all_enables

biggest_size

29135

1

T1

6

T2

28

T3

50