Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328352640	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328352640	0	0
T1	2292752	48276	0	0
T2	278096	9325	0	0
T3	3715376	82158	0	0
T4	7281008	1564046	0	0
T13	6046376	105418	0	0
T14	16894528	1860076	0	0
T15	0	14031	0	0
T16	40320	942	0	0
T17	11935000	282101	0	0
T18	9732408	1463200	0	0
T19	81088	3472	0	0
T20	0	4044	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2292752	2290960	0	0
T2	278096	268520	0	0
T3	3715376	3714704	0	0
T4	7281008	7280672	0	0
T13	6046376	6043240	0	0
T14	16894528	16894416	0	0
T16	40320	37856	0	0
T17	11935000	11933432	0	0
T18	9732408	9732184	0	0
T19	81088	80416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2292752	2290960	0	0
T2	278096	268520	0	0
T3	3715376	3714704	0	0
T4	7281008	7280672	0	0
T13	6046376	6043240	0	0
T14	16894528	16894416	0	0
T16	40320	37856	0	0
T17	11935000	11933432	0	0
T18	9732408	9732184	0	0
T19	81088	80416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2292752	2290960	0	0
T2	278096	268520	0	0
T3	3715376	3714704	0	0
T4	7281008	7280672	0	0
T13	6046376	6043240	0	0
T14	16894528	16894416	0	0
T16	40320	37856	0	0
T17	11935000	11933432	0	0
T18	9732408	9732184	0	0
T19	81088	80416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	119363260	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	119363260	0	0
T1	40942	18460	0	0
T2	4966	4279	0	0
T3	66346	27247	0	0
T4	130018	665774	0	0
T13	107971	49482	0	0
T14	301688	147550	0	0
T16	720	366	0	0
T17	213125	127544	0	0
T18	173793	9282	0	0
T19	1448	1357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	86273800	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	86273800	0	0
T1	40942	15505	0	0
T2	4966	2458	0	0
T3	66346	13832	0	0
T4	130018	302093	0	0
T13	107971	12139	0	0
T14	301688	354353	0	0
T16	720	192	0	0
T17	213125	48266	0	0
T18	173793	722318	0	0
T19	1448	705	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1355841	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1355841	0	0
T1	40942	237	0	0
T2	4966	44	0	0
T3	66346	2428	0	0
T4	130018	13388	0	0
T13	107971	1418	0	0
T14	301688	40463	0	0
T16	720	5	0	0
T17	213125	1703	0	0
T18	173793	0	0	0
T19	1448	19	0	0
T20	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3130901	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3130901	0	0
T1	40942	264	0	0
T2	4966	44	0	0
T3	66346	966	0	0
T4	130018	10254	0	0
T13	107971	185	0	0
T14	301688	14361	0	0
T16	720	5	0	0
T17	213125	1821	0	0
T18	173793	0	0	0
T19	1448	19	0	0
T20	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1435043	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1435043	0	0
T1	40942	216	0	0
T2	4966	47	0	0
T3	66346	1184	0	0
T4	130018	11525	0	0
T13	107971	919	0	0
T14	301688	32865	0	0
T16	720	8	0	0
T17	213125	5452	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3419307	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3419307	0	0
T1	40942	174	0	0
T2	4966	47	0	0
T3	66346	789	0	0
T4	130018	10298	0	0
T13	107971	77	0	0
T14	301688	13210	0	0
T16	720	8	0	0
T17	213125	4021	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1382085	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1382085	0	0
T1	40942	234	0	0
T2	4966	43	0	0
T3	66346	1962	0	0
T4	130018	9759	0	0
T13	107971	1450	0	0
T14	301688	41227	0	0
T16	720	9	0	0
T17	213125	3205	0	0
T18	173793	0	0	0
T19	1448	23	0	0
T20	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2766921	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2766921	0	0
T1	40942	219	0	0
T2	4966	43	0	0
T3	66346	772	0	0
T4	130018	10185	0	0
T13	107971	710	0	0
T14	301688	15449	0	0
T16	720	9	0	0
T17	213125	687	0	0
T18	173793	0	0	0
T19	1448	23	0	0
T20	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1400299	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1400299	0	0
T1	40942	246	0	0
T2	4966	56	0	0
T3	66346	2207	0	0
T4	130018	9784	0	0
T13	107971	676	0	0
T14	301688	31370	0	0
T16	720	3	0	0
T17	213125	2881	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3692896	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3692896	0	0
T1	40942	246	0	0
T2	4966	56	0	0
T3	66346	876	0	0
T4	130018	8188	0	0
T13	107971	395	0	0
T14	301688	11465	0	0
T16	720	3	0	0
T17	213125	2521	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1378038	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1378038	0	0
T1	40942	225	0	0
T2	4966	59	0	0
T3	66346	1601	0	0
T4	130018	8009	0	0
T13	107971	404	0	0
T14	301688	36198	0	0
T16	720	9	0	0
T17	213125	1176	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3156178	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3156178	0	0
T1	40942	222	0	0
T2	4966	59	0	0
T3	66346	1121	0	0
T4	130018	8945	0	0
T13	107971	2	0	0
T14	301688	13359	0	0
T16	720	9	0	0
T17	213125	1889	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1416191	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1416191	0	0
T1	40942	288	0	0
T2	4966	48	0	0
T3	66346	0	0	0
T4	130018	10686	0	0
T13	107971	590	0	0
T14	301688	30840	0	0
T15	0	788	0	0
T16	720	8	0	0
T17	213125	1908	0	0
T18	173793	0	0	0
T19	1448	22	0	0
T20	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3639028	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3639028	0	0
T1	40942	341	0	0
T2	4966	48	0	0
T3	66346	0	0	0
T4	130018	10880	0	0
T13	107971	3	0	0
T14	301688	13050	0	0
T15	0	752	0	0
T16	720	8	0	0
T17	213125	1688	0	0
T18	173793	0	0	0
T19	1448	22	0	0
T20	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1382474	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1382474	0	0
T1	40942	286	0	0
T2	4966	41	0	0
T3	66346	0	0	0
T4	130018	11168	0	0
T13	107971	3419	0	0
T14	301688	38490	0	0
T15	0	706	0	0
T16	720	6	0	0
T17	213125	1604	0	0
T18	173793	0	0	0
T19	1448	23	0	0
T20	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3385229	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3385229	0	0
T1	40942	321	0	0
T2	4966	41	0	0
T3	66346	0	0	0
T4	130018	9701	0	0
T13	107971	403	0	0
T14	301688	11681	0	0
T15	0	699	0	0
T16	720	6	0	0
T17	213125	1510	0	0
T18	173793	0	0	0
T19	1448	23	0	0
T20	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1421922	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1421922	0	0
T1	40942	220	0	0
T2	4966	60	0	0
T3	66346	1753	0	0
T4	130018	10279	0	0
T13	107971	1068	0	0
T14	301688	45172	0	0
T16	720	6	0	0
T17	213125	1736	0	0
T18	173793	0	0	0
T19	1448	17	0	0
T20	0	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3288304	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3288304	0	0
T1	40942	242	0	0
T2	4966	60	0	0
T3	66346	761	0	0
T4	130018	13393	0	0
T13	107971	399	0	0
T14	301688	13110	0	0
T16	720	6	0	0
T17	213125	1456	0	0
T18	173793	0	0	0
T19	1448	17	0	0
T20	0	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1409365	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1409365	0	0
T1	40942	395	0	0
T2	4966	61	0	0
T3	66346	2819	0	0
T4	130018	12519	0	0
T13	107971	1223	0	0
T14	301688	39400	0	0
T16	720	3	0	0
T17	213125	2842	0	0
T18	173793	1047	0	0
T19	1448	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3309688	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3309688	0	0
T1	40942	330	0	0
T2	4966	61	0	0
T3	66346	1928	0	0
T4	130018	12001	0	0
T13	107971	669	0	0
T14	301688	13087	0	0
T16	720	3	0	0
T17	213125	4259	0	0
T18	173793	82020	0	0
T19	1448	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1457708	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1457708	0	0
T1	40942	268	0	0
T2	4966	48	0	0
T3	66346	1993	0	0
T4	130018	10605	0	0
T13	107971	1306	0	0
T14	301688	30413	0	0
T16	720	7	0	0
T17	213125	1907	0	0
T18	173793	1085	0	0
T19	1448	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3637357	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3637357	0	0
T1	40942	264	0	0
T2	4966	48	0	0
T3	66346	927	0	0
T4	130018	9278	0	0
T13	107971	572	0	0
T14	301688	10366	0	0
T16	720	7	0	0
T17	213125	838	0	0
T18	173793	84384	0	0
T19	1448	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1395316	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1395316	0	0
T1	40942	231	0	0
T2	4966	42	0	0
T3	66346	2128	0	0
T4	130018	11603	0	0
T13	107971	356	0	0
T14	301688	44682	0	0
T16	720	10	0	0
T17	213125	2123	0	0
T18	173793	0	0	0
T19	1448	31	0	0
T20	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3149479	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3149479	0	0
T1	40942	314	0	0
T2	4966	42	0	0
T3	66346	1043	0	0
T4	130018	13381	0	0
T13	107971	624	0	0
T14	301688	17643	0	0
T16	720	10	0	0
T17	213125	1319	0	0
T18	173793	0	0	0
T19	1448	31	0	0
T20	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1407118	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1407118	0	0
T1	40942	364	0	0
T2	4966	53	0	0
T3	66346	1349	0	0
T4	130018	8991	0	0
T13	107971	726	0	0
T14	301688	38912	0	0
T16	720	6	0	0
T17	213125	1603	0	0
T18	173793	0	0	0
T19	1448	29	0	0
T20	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3455757	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3455757	0	0
T1	40942	283	0	0
T2	4966	53	0	0
T3	66346	845	0	0
T4	130018	9886	0	0
T13	107971	884	0	0
T14	301688	12632	0	0
T16	720	6	0	0
T17	213125	1175	0	0
T18	173793	0	0	0
T19	1448	29	0	0
T20	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1353043	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1353043	0	0
T1	40942	210	0	0
T2	4966	44	0	0
T3	66346	0	0	0
T4	130018	11063	0	0
T13	107971	1594	0	0
T14	301688	33926	0	0
T15	0	671	0	0
T16	720	6	0	0
T17	213125	1326	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2602800	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2602800	0	0
T1	40942	215	0	0
T2	4966	44	0	0
T3	66346	0	0	0
T4	130018	16384	0	0
T13	107971	1212	0	0
T14	301688	11532	0	0
T15	0	674	0	0
T16	720	6	0	0
T17	213125	386	0	0
T18	173793	0	0	0
T19	1448	27	0	0
T20	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1396093	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1396093	0	0
T1	40942	212	0	0
T2	4966	39	0	0
T3	66346	0	0	0
T4	130018	8419	0	0
T13	107971	2357	0	0
T14	301688	40065	0	0
T15	0	776	0	0
T16	720	3	0	0
T17	213125	1630	0	0
T18	173793	0	0	0
T19	1448	28	0	0
T20	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2763568	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2763568	0	0
T1	40942	205	0	0
T2	4966	39	0	0
T3	66346	0	0	0
T4	130018	6704	0	0
T13	107971	1298	0	0
T14	301688	14514	0	0
T15	0	732	0	0
T16	720	3	0	0
T17	213125	3049	0	0
T18	173793	0	0	0
T19	1448	28	0	0
T20	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1345077	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1345077	0	0
T1	40942	245	0	0
T2	4966	43	0	0
T3	66346	1673	0	0
T4	130018	7702	0	0
T13	107971	1240	0	0
T14	301688	42968	0	0
T16	720	6	0	0
T17	213125	2923	0	0
T18	173793	0	0	0
T19	1448	40	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3000133	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3000133	0	0
T1	40942	265	0	0
T2	4966	43	0	0
T3	66346	988	0	0
T4	130018	7549	0	0
T13	107971	350	0	0
T14	301688	12806	0	0
T16	720	6	0	0
T17	213125	2456	0	0
T18	173793	0	0	0
T19	1448	40	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1350738	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1350738	0	0
T1	40942	201	0	0
T2	4966	46	0	0
T3	66346	0	0	0
T4	130018	8852	0	0
T13	107971	1639	0	0
T14	301688	39318	0	0
T15	0	588	0	0
T16	720	6	0	0
T17	213125	1991	0	0
T18	173793	0	0	0
T19	1448	26	0	0
T20	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3718596	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3718596	0	0
T1	40942	240	0	0
T2	4966	46	0	0
T3	66346	0	0	0
T4	130018	11495	0	0
T13	107971	241	0	0
T14	301688	8995	0	0
T15	0	616	0	0
T16	720	6	0	0
T17	213125	1288	0	0
T18	173793	0	0	0
T19	1448	26	0	0
T20	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1391939	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1391939	0	0
T1	40942	202	0	0
T2	4966	44	0	0
T3	66346	0	0	0
T4	130018	9474	0	0
T13	107971	1740	0	0
T14	301688	40626	0	0
T15	0	714	0	0
T16	720	7	0	0
T17	213125	840	0	0
T18	173793	0	0	0
T19	1448	32	0	0
T20	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3321058	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3321058	0	0
T1	40942	180	0	0
T2	4966	44	0	0
T3	66346	0	0	0
T4	130018	10692	0	0
T13	107971	184	0	0
T14	301688	12838	0	0
T15	0	769	0	0
T16	720	7	0	0
T17	213125	446	0	0
T18	173793	0	0	0
T19	1448	32	0	0
T20	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1410408	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1410408	0	0
T1	40942	232	0	0
T2	4966	47	0	0
T3	66346	2287	0	0
T4	130018	13539	0	0
T13	107971	1825	0	0
T14	301688	37902	0	0
T16	720	12	0	0
T17	213125	1000	0	0
T18	173793	1374	0	0
T19	1448	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3167740	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3167740	0	0
T1	40942	262	0	0
T2	4966	47	0	0
T3	66346	1000	0	0
T4	130018	14038	0	0
T13	107971	839	0	0
T14	301688	11907	0	0
T16	720	12	0	0
T17	213125	277	0	0
T18	173793	102453	0	0
T19	1448	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1367441	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1367441	0	0
T1	40942	281	0	0
T2	4966	61	0	0
T3	66346	1949	0	0
T4	130018	10541	0	0
T13	107971	1869	0	0
T14	301688	32191	0	0
T16	720	7	0	0
T17	213125	2142	0	0
T18	173793	0	0	0
T19	1448	36	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3323161	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3323161	0	0
T1	40942	227	0	0
T2	4966	61	0	0
T3	66346	862	0	0
T4	130018	11690	0	0
T13	107971	1460	0	0
T14	301688	14314	0	0
T16	720	7	0	0
T17	213125	2932	0	0
T18	173793	0	0	0
T19	1448	36	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1408605	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1408605	0	0
T1	40942	294	0	0
T2	4966	43	0	0
T3	66346	0	0	0
T4	130018	11518	0	0
T13	107971	467	0	0
T14	301688	35498	0	0
T15	0	684	0	0
T16	720	13	0	0
T17	213125	3750	0	0
T18	173793	0	0	0
T19	1448	33	0	0
T20	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3205699	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3205699	0	0
T1	40942	284	0	0
T2	4966	43	0	0
T3	66346	0	0	0
T4	130018	13643	0	0
T13	107971	117	0	0
T14	301688	13816	0	0
T15	0	676	0	0
T16	720	13	0	0
T17	213125	1699	0	0
T18	173793	0	0	0
T19	1448	33	0	0
T20	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1384458	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1384458	0	0
T1	40942	292	0	0
T2	4966	50	0	0
T3	66346	1914	0	0
T4	130018	7424	0	0
T13	107971	417	0	0
T14	301688	39840	0	0
T16	720	5	0	0
T17	213125	1413	0	0
T18	173793	0	0	0
T19	1448	20	0	0
T20	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2688108	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2688108	0	0
T1	40942	284	0	0
T2	4966	50	0	0
T3	66346	954	0	0
T4	130018	8313	0	0
T13	107971	17	0	0
T14	301688	12637	0	0
T16	720	5	0	0
T17	213125	1460	0	0
T18	173793	0	0	0
T19	1448	20	0	0
T20	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1376667	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1376667	0	0
T1	40942	226	0	0
T2	4966	37	0	0
T3	66346	0	0	0
T4	130018	12885	0	0
T13	107971	1449	0	0
T14	301688	40767	0	0
T15	0	694	0	0
T16	720	12	0	0
T17	213125	737	0	0
T18	173793	0	0	0
T19	1448	28	0	0
T20	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2984739	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2984739	0	0
T1	40942	248	0	0
T2	4966	37	0	0
T3	66346	0	0	0
T4	130018	11981	0	0
T13	107971	533	0	0
T14	301688	14840	0	0
T15	0	734	0	0
T16	720	12	0	0
T17	213125	699	0	0
T18	173793	0	0	0
T19	1448	28	0	0
T20	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1386446	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1386446	0	0
T1	40942	288	0	0
T2	4966	51	0	0
T3	66346	0	0	0
T4	130018	10015	0	0
T13	107971	1072	0	0
T14	301688	32792	0	0
T16	720	6	0	0
T17	213125	1538	0	0
T18	173793	1240	0	0
T19	1448	30	0	0
T20	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2825474	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2825474	0	0
T1	40942	346	0	0
T2	4966	51	0	0
T3	66346	0	0	0
T4	130018	9166	0	0
T13	107971	331	0	0
T14	301688	13588	0	0
T16	720	6	0	0
T17	213125	1898	0	0
T18	173793	95909	0	0
T19	1448	30	0	0
T20	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1387848	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1387848	0	0
T1	40942	313	0	0
T2	4966	44	0	0
T3	66346	0	0	0
T4	130018	18691	0	0
T13	107971	474	0	0
T14	301688	38347	0	0
T15	0	733	0	0
T16	720	4	0	0
T17	213125	2556	0	0
T18	173793	0	0	0
T19	1448	21	0	0
T20	0	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3237922	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3237922	0	0
T1	40942	288	0	0
T2	4966	44	0	0
T3	66346	0	0	0
T4	130018	16196	0	0
T13	107971	1	0	0
T14	301688	14707	0	0
T15	0	686	0	0
T16	720	4	0	0
T17	213125	357	0	0
T18	173793	0	0	0
T19	1448	21	0	0
T20	0	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1391636	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1391636	0	0
T1	40942	232	0	0
T2	4966	49	0	0
T3	66346	0	0	0
T4	130018	14326	0	0
T13	107971	669	0	0
T14	301688	31335	0	0
T15	0	644	0	0
T16	720	10	0	0
T17	213125	2039	0	0
T18	173793	0	0	0
T19	1448	24	0	0
T20	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2415383	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2415383	0	0
T1	40942	187	0	0
T2	4966	49	0	0
T3	66346	0	0	0
T4	130018	15150	0	0
T13	107971	1	0	0
T14	301688	10577	0	0
T15	0	695	0	0
T16	720	10	0	0
T17	213125	2395	0	0
T18	173793	0	0	0
T19	1448	24	0	0
T20	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1402270	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1402270	0	0
T1	40942	280	0	0
T2	4966	48	0	0
T3	66346	0	0	0
T4	130018	11344	0	0
T13	107971	586	0	0
T14	301688	36743	0	0
T16	720	10	0	0
T17	213125	3073	0	0
T18	173793	3192	0	0
T19	1448	23	0	0
T20	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	3132471	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	3132471	0	0
T1	40942	270	0	0
T2	4966	48	0	0
T3	66346	0	0	0
T4	130018	13088	0	0
T13	107971	629	0	0
T14	301688	14579	0	0
T16	720	10	0	0
T17	213125	2591	0	0
T18	173793	253355	0	0
T19	1448	23	0	0
T20	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	1320523	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	1320523	0	0
T1	40942	466	0	0
T2	4966	46	0	0
T3	66346	0	0	0
T4	130018	10261	0	0
T13	107971	705	0	0
T14	301688	31471	0	0
T16	720	5	0	0
T17	213125	2927	0	0
T18	173793	1344	0	0
T19	1448	25	0	0
T20	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298070543	2783091	0	0
DepthKnown_A	298070543	297943364	0	0
RvalidKnown_A	298070543	297943364	0	0
WreadyKnown_A	298070543	297943364	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	2783091	0	0
T1	40942	406	0	0
T2	4966	46	0	0
T3	66346	0	0	0
T4	130018	9330	0	0
T13	107971	3	0	0
T14	301688	13289	0	0
T16	720	5	0	0
T17	213125	3149	0	0
T18	173793	104197	0	0
T19	1448	25	0	0
T20	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298070543	297943364	0	0
T1	40942	40910	0	0
T2	4966	4795	0	0
T3	66346	66334	0	0
T4	130018	130012	0	0
T13	107971	107915	0	0
T14	301688	301686	0	0
T16	720	676	0	0
T17	213125	213097	0	0
T18	173793	173789	0	0
T19	1448	1436	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0