Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1754402	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

275862

1

T1

228

T2

193

T3

123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	685314	1			T1	531		T2	477		T3	287
values[0x0]	660138	1			T1	509		T2	477		T3	305
values[0x1]	684812	1			T1	533		T2	482		T3	336

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1360676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

669588

1

T1

514

T2

433

T3

300

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8630	1			T1	2		T2	4		T3	1
valid_sources[0x01]	7563	1			T1	7		T2	7		T3	1
valid_sources[0x02]	8296	1			T2	2		T12	6		T15	4
valid_sources[0x03]	8387	1			T1	6		T2	7		T3	2
valid_sources[0x04]	7225	1			T1	8		T2	6		T12	14
valid_sources[0x05]	7249	1			T1	7		T2	7		T3	1
valid_sources[0x06]	7878	1			T2	7		T12	26		T15	5
valid_sources[0x07]	7939	1			T1	8		T2	4		T12	7
valid_sources[0x08]	7747	1			T1	11		T2	7		T12	3
valid_sources[0x09]	7713	1			T1	6		T2	3		T3	2
valid_sources[0x0a]	8266	1			T1	5		T2	6		T12	4
valid_sources[0x0b]	7986	1			T1	1		T2	6		T3	4
valid_sources[0x0c]	8724	1			T1	4		T2	2		T3	2
valid_sources[0x0d]	8018	1			T1	16		T2	3		T3	6
valid_sources[0x0e]	7703	1			T2	2		T3	5		T12	13
valid_sources[0x0f]	8948	1			T2	6		T3	2		T12	14
valid_sources[0x10]	7772	1			T1	5		T2	10		T3	1
valid_sources[0x11]	7617	1			T1	9		T2	5		T12	9
valid_sources[0x12]	9253	1			T2	4		T3	1		T12	2
valid_sources[0x13]	7679	1			T1	3		T2	9		T3	7
valid_sources[0x14]	7401	1			T1	4		T2	7		T12	6
valid_sources[0x15]	8241	1			T2	8		T3	15		T12	23
valid_sources[0x16]	8778	1			T1	16		T2	5		T15	3
valid_sources[0x17]	8047	1			T1	4		T2	3		T3	5
valid_sources[0x18]	7340	1			T1	4		T2	10		T3	3
valid_sources[0x19]	8214	1			T2	6		T3	2		T12	17
valid_sources[0x1a]	7696	1			T1	13		T2	4		T3	5
valid_sources[0x1b]	7653	1			T2	6		T3	1		T12	6
valid_sources[0x1c]	7375	1			T2	2		T12	3		T15	17
valid_sources[0x1d]	7756	1			T2	6		T3	1		T15	7
valid_sources[0x1e]	8514	1			T2	7		T3	4		T12	12
valid_sources[0x1f]	7822	1			T1	2		T2	9		T3	9
valid_sources[0x20]	7649	1			T2	6		T3	4		T12	4
valid_sources[0x21]	7712	1			T1	19		T2	3		T3	1
valid_sources[0x22]	7667	1			T1	4		T2	6		T3	4
valid_sources[0x23]	8412	1			T2	6		T3	4		T12	9
valid_sources[0x24]	8451	1			T1	6		T2	4		T3	4
valid_sources[0x25]	7823	1			T1	1		T2	7		T3	3
valid_sources[0x26]	7372	1			T1	8		T2	10		T3	1
valid_sources[0x27]	7790	1			T1	3		T2	6		T3	1
valid_sources[0x28]	8102	1			T1	31		T2	6		T12	13
valid_sources[0x29]	7965	1			T1	6		T2	4		T12	9
valid_sources[0x2a]	8061	1			T1	2		T2	5		T3	4
valid_sources[0x2b]	7678	1			T1	3		T2	5		T12	6
valid_sources[0x2c]	8264	1			T1	6		T2	5		T3	5
valid_sources[0x2d]	8342	1			T1	4		T2	8		T3	2
valid_sources[0x2e]	8979	1			T2	2		T3	1		T12	19
valid_sources[0x2f]	7771	1			T1	33		T2	9		T12	37
valid_sources[0x30]	7803	1			T2	4		T3	3		T12	7
valid_sources[0x31]	7766	1			T1	18		T2	10		T3	4
valid_sources[0x32]	7845	1			T1	10		T2	1		T3	6
valid_sources[0x33]	7444	1			T1	11		T2	2		T3	14
valid_sources[0x34]	7579	1			T1	7		T2	7		T3	16
valid_sources[0x35]	8155	1			T1	27		T2	6		T3	1
valid_sources[0x36]	7106	1			T2	6		T3	5		T12	28
valid_sources[0x37]	8606	1			T1	1		T2	7		T3	2
valid_sources[0x38]	8362	1			T1	5		T2	5		T3	1
valid_sources[0x39]	7252	1			T2	6		T3	8		T12	6
valid_sources[0x3a]	7069	1			T1	5		T2	6		T3	12
valid_sources[0x3b]	7679	1			T1	22		T2	7		T3	3
valid_sources[0x3c]	7963	1			T1	18		T2	4		T3	1
valid_sources[0x3d]	7739	1			T1	5		T2	4		T3	3
valid_sources[0x3e]	8481	1			T1	14		T2	8		T12	12
valid_sources[0x3f]	8885	1			T1	3		T2	4		T3	8
valid_sources[0x40]	7690	1			T2	3		T3	4		T12	3
valid_sources[0x41]	8107	1			T1	9		T2	6		T3	7
valid_sources[0x42]	7115	1			T1	3		T2	6		T3	7
valid_sources[0x43]	7722	1			T1	8		T2	6		T3	1
valid_sources[0x44]	7655	1			T2	8		T3	3		T12	5
valid_sources[0x45]	7880	1			T2	5		T12	16		T15	6
valid_sources[0x46]	8366	1			T1	13		T2	5		T3	1
valid_sources[0x47]	7275	1			T1	8		T2	7		T3	5
valid_sources[0x48]	7505	1			T2	7		T3	9		T12	24
valid_sources[0x49]	8112	1			T1	1		T2	8		T3	2
valid_sources[0x4a]	8080	1			T1	1		T2	4		T12	5
valid_sources[0x4b]	8343	1			T1	18		T2	9		T12	8
valid_sources[0x4c]	7494	1			T1	7		T2	4		T3	11
valid_sources[0x4d]	7557	1			T1	20		T2	6		T12	4
valid_sources[0x4e]	6983	1			T1	14		T2	3		T12	3
valid_sources[0x4f]	7553	1			T1	30		T2	1		T3	8
valid_sources[0x50]	8214	1			T2	8		T3	1		T12	5
valid_sources[0x51]	7764	1			T1	7		T2	11		T3	2
valid_sources[0x52]	8072	1			T2	5		T3	2		T12	28
valid_sources[0x53]	8900	1			T1	8		T2	10		T3	8
valid_sources[0x54]	7881	1			T1	4		T2	5		T3	6
valid_sources[0x55]	8010	1			T1	10		T2	3		T3	1
valid_sources[0x56]	7723	1			T1	1		T2	7		T12	17
valid_sources[0x57]	8028	1			T1	6		T2	3		T3	9
valid_sources[0x58]	7874	1			T1	16		T2	6		T15	5
valid_sources[0x59]	7609	1			T2	6		T3	2		T12	7
valid_sources[0x5a]	8563	1			T2	12		T12	16		T15	8
valid_sources[0x5b]	7373	1			T1	38		T2	9		T12	7
valid_sources[0x5c]	9087	1			T1	3		T2	4		T3	3
valid_sources[0x5d]	7765	1			T1	6		T2	5		T3	4
valid_sources[0x5e]	8766	1			T2	6		T3	15		T15	6
valid_sources[0x5f]	8226	1			T2	7		T12	4		T15	11
valid_sources[0x60]	8142	1			T2	2		T12	19		T15	9
valid_sources[0x61]	8196	1			T1	13		T2	9		T3	6
valid_sources[0x62]	7809	1			T2	2		T3	5		T12	5
valid_sources[0x63]	7878	1			T1	4		T2	5		T3	9
valid_sources[0x64]	7578	1			T1	18		T2	7		T12	6
valid_sources[0x65]	9034	1			T2	2		T3	6		T12	1
valid_sources[0x66]	7907	1			T2	5		T3	11		T12	3
valid_sources[0x67]	7545	1			T2	1		T3	11		T12	13
valid_sources[0x68]	8589	1			T1	6		T2	6		T3	9
valid_sources[0x69]	7872	1			T1	13		T2	1		T3	4
valid_sources[0x6a]	7915	1			T2	3		T12	11		T15	6
valid_sources[0x6b]	7717	1			T1	3		T2	4		T12	14
valid_sources[0x6c]	9537	1			T2	4		T3	2		T12	15
valid_sources[0x6d]	9655	1			T1	22		T2	7		T3	6
valid_sources[0x6e]	9117	1			T1	3		T2	10		T3	8
valid_sources[0x6f]	8086	1			T2	6		T3	9		T12	24
valid_sources[0x70]	7584	1			T1	11		T2	8		T3	5
valid_sources[0x71]	8661	1			T2	5		T3	9		T15	5
valid_sources[0x72]	7598	1			T1	16		T2	4		T3	2
valid_sources[0x73]	7677	1			T1	52		T2	5		T3	8
valid_sources[0x74]	7404	1			T1	8		T2	4		T3	3
valid_sources[0x75]	8819	1			T2	6		T3	7		T12	14
valid_sources[0x76]	7239	1			T1	8		T2	6		T3	7
valid_sources[0x77]	8377	1			T1	3		T2	2		T12	7
valid_sources[0x78]	8607	1			T1	13		T2	8		T3	1
valid_sources[0x79]	8105	1			T1	10		T2	2		T3	2
valid_sources[0x7a]	9273	1			T2	2		T12	7		T15	5
valid_sources[0x7b]	7681	1			T2	2		T12	1		T15	1
valid_sources[0x7c]	8024	1			T2	2		T3	13		T12	1
valid_sources[0x7d]	7775	1			T2	5		T3	1		T12	1
valid_sources[0x7e]	8078	1			T1	11		T2	7		T3	2
valid_sources[0x7f]	7663	1			T1	5		T2	4		T3	5
valid_sources[0x80]	8995	1			T1	3		T2	6		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28596

1

T1

17

T2

28

T3

9

values[0x0]

all_enables

biggest_size

218587

1

T1

187

T2

142

T3

103

values[0x1]

all_enables

biggest_size

28679

1

T1

24

T2

23

T3

11