Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	334680015	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334680015	0	0
T1	1499344	22421	0	0
T2	181664	7072	0	0
T3	48867616	1561956	0	0
T12	2710456	50917	0	0
T13	35112	1145	0	0
T14	1059128	21874	0	0
T15	52391360	938657	0	0
T16	2658768	39156	0	0
T17	241696	8147	0	0
T18	24136	886	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1499344	1497552	0	0
T2	181664	177632	0	0
T3	48867616	48865992	0	0
T12	2710456	2708776	0	0
T13	35112	33712	0	0
T14	1059128	1058288	0	0
T15	52391360	52390464	0	0
T16	2658768	2655296	0	0
T17	241696	236656	0	0
T18	24136	23464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1499344	1497552	0	0
T2	181664	177632	0	0
T3	48867616	48865992	0	0
T12	2710456	2708776	0	0
T13	35112	33712	0	0
T14	1059128	1058288	0	0
T15	52391360	52390464	0	0
T16	2658768	2655296	0	0
T17	241696	236656	0	0
T18	24136	23464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1499344	1497552	0	0
T2	181664	177632	0	0
T3	48867616	48865992	0	0
T12	2710456	2708776	0	0
T13	35112	33712	0	0
T14	1059128	1058288	0	0
T15	52391360	52390464	0	0
T16	2658768	2655296	0	0
T17	241696	236656	0	0
T18	24136	23464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	129549017	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	129549017	0	0
T1	26774	10256	0	0
T2	3244	2766	0	0
T3	872636	861166	0	0
T12	48401	20885	0	0
T13	627	440	0	0
T14	18913	8273	0	0
T15	935560	913430	0	0
T16	47478	9913	0	0
T17	4316	3749	0	0
T18	431	343	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	83247436	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	83247436	0	0
T1	26774	3296	0	0
T2	3244	1436	0	0
T3	872636	348378	0	0
T12	48401	13444	0	0
T13	627	235	0	0
T14	18913	7120	0	0
T15	935560	8539	0	0
T16	47478	9672	0	0
T17	4316	2238	0	0
T18	431	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1478100	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1478100	0	0
T1	26774	179	0	0
T2	3244	56	0	0
T3	872636	131	0	0
T12	48401	386	0	0
T13	627	12	0	0
T14	18913	118	0	0
T15	935560	255	0	0
T16	47478	277	0	0
T17	4316	44	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2898584	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2898584	0	0
T1	26774	96	0	0
T2	3244	56	0	0
T3	872636	13031	0	0
T12	48401	350	0	0
T13	627	12	0	0
T14	18913	92	0	0
T15	935560	67	0	0
T16	47478	263	0	0
T17	4316	44	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1523788	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1523788	0	0
T1	26774	262	0	0
T2	3244	52	0	0
T3	872636	210	0	0
T12	48401	346	0	0
T13	627	9	0	0
T14	18913	77	0	0
T15	935560	358	0	0
T16	47478	327	0	0
T17	4316	33	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3475544	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3475544	0	0
T1	26774	97	0	0
T2	3244	52	0	0
T3	872636	16830	0	0
T12	48401	298	0	0
T13	627	9	0	0
T14	18913	98	0	0
T15	935560	379	0	0
T16	47478	380	0	0
T17	4316	33	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1441132	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1441132	0	0
T1	26774	142	0	0
T2	3244	61	0	0
T3	872636	170	0	0
T12	48401	347	0	0
T13	627	11	0	0
T14	18913	119	0	0
T15	935560	228	0	0
T16	47478	283	0	0
T17	4316	23	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2537411	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2537411	0	0
T1	26774	60	0	0
T2	3244	61	0	0
T3	872636	11165	0	0
T12	48401	322	0	0
T13	627	11	0	0
T14	18913	138	0	0
T15	935560	443	0	0
T16	47478	351	0	0
T17	4316	23	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1457530	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1457530	0	0
T1	26774	166	0	0
T2	3244	51	0	0
T3	872636	126	0	0
T12	48401	406	0	0
T13	627	9	0	0
T14	18913	209	0	0
T15	935560	342	0	0
T16	47478	346	0	0
T17	4316	59	0	0
T18	431	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2815382	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2815382	0	0
T1	26774	80	0	0
T2	3244	51	0	0
T3	872636	10117	0	0
T12	48401	328	0	0
T13	627	9	0	0
T14	18913	232	0	0
T15	935560	66	0	0
T16	47478	318	0	0
T17	4316	59	0	0
T18	431	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1449434	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1449434	0	0
T1	26774	220	0	0
T2	3244	41	0	0
T3	872636	155	0	0
T12	48401	481	0	0
T13	627	6	0	0
T14	18913	77	0	0
T15	935560	248	0	0
T16	47478	413	0	0
T17	4316	47	0	0
T18	431	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2771342	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2771342	0	0
T1	26774	57	0	0
T2	3244	41	0	0
T3	872636	15159	0	0
T12	48401	332	0	0
T13	627	6	0	0
T14	18913	74	0	0
T15	935560	59	0	0
T16	47478	383	0	0
T17	4316	47	0	0
T18	431	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1458703	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1458703	0	0
T1	26774	183	0	0
T2	3244	73	0	0
T3	872636	135	0	0
T12	48401	431	0	0
T13	627	7	0	0
T14	18913	99	0	0
T15	935560	245	0	0
T16	47478	268	0	0
T17	4316	45	0	0
T18	431	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3265888	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3265888	0	0
T1	26774	77	0	0
T2	3244	73	0	0
T3	872636	9758	0	0
T12	48401	405	0	0
T13	627	7	0	0
T14	18913	163	0	0
T15	935560	662	0	0
T16	47478	262	0	0
T17	4316	45	0	0
T18	431	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1452543	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1452543	0	0
T1	26774	270	0	0
T2	3244	45	0	0
T3	872636	140	0	0
T12	48401	292	0	0
T13	627	6	0	0
T14	18913	181	0	0
T15	935560	261	0	0
T16	47478	433	0	0
T17	4316	39	0	0
T18	431	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3013159	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3013159	0	0
T1	26774	112	0	0
T2	3244	45	0	0
T3	872636	12617	0	0
T12	48401	259	0	0
T13	627	6	0	0
T14	18913	130	0	0
T15	935560	56	0	0
T16	47478	301	0	0
T17	4316	39	0	0
T18	431	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1459854	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1459854	0	0
T1	26774	284	0	0
T2	3244	54	0	0
T3	872636	199	0	0
T12	48401	355	0	0
T13	627	11	0	0
T14	18913	171	0	0
T15	935560	359	0	0
T16	47478	388	0	0
T17	4316	43	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2874364	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2874364	0	0
T1	26774	121	0	0
T2	3244	54	0	0
T3	872636	15433	0	0
T12	48401	344	0	0
T13	627	11	0	0
T14	18913	149	0	0
T15	935560	87	0	0
T16	47478	358	0	0
T17	4316	43	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1445571	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1445571	0	0
T1	26774	175	0	0
T2	3244	64	0	0
T3	872636	126	0	0
T12	48401	307	0	0
T13	627	8	0	0
T14	18913	149	0	0
T15	935560	282	0	0
T16	47478	432	0	0
T17	4316	34	0	0
T18	431	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3072136	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3072136	0	0
T1	26774	74	0	0
T2	3244	64	0	0
T3	872636	6683	0	0
T12	48401	236	0	0
T13	627	8	0	0
T14	18913	141	0	0
T15	935560	69	0	0
T16	47478	427	0	0
T17	4316	34	0	0
T18	431	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1511740	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1511740	0	0
T1	26774	250	0	0
T2	3244	46	0	0
T3	872636	197	0	0
T12	48401	358	0	0
T13	627	9	0	0
T14	18913	152	0	0
T15	935560	325	0	0
T16	47478	310	0	0
T17	4316	57	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3377652	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3377652	0	0
T1	26774	111	0	0
T2	3244	46	0	0
T3	872636	16857	0	0
T12	48401	372	0	0
T13	627	9	0	0
T14	18913	121	0	0
T15	935560	1385	0	0
T16	47478	330	0	0
T17	4316	57	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1478990	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1478990	0	0
T1	26774	111	0	0
T2	3244	58	0	0
T3	872636	208	0	0
T12	48401	280	0	0
T13	627	8	0	0
T14	18913	53	0	0
T15	935560	300	0	0
T16	47478	354	0	0
T17	4316	31	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3082387	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3082387	0	0
T1	26774	50	0	0
T2	3244	58	0	0
T3	872636	17751	0	0
T12	48401	237	0	0
T13	627	8	0	0
T14	18913	75	0	0
T15	935560	64	0	0
T16	47478	397	0	0
T17	4316	31	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1469543	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1469543	0	0
T1	26774	293	0	0
T2	3244	51	0	0
T3	872636	91	0	0
T12	48401	229	0	0
T13	627	12	0	0
T14	18913	113	0	0
T15	935560	310	0	0
T16	47478	478	0	0
T17	4316	42	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2812007	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2812007	0	0
T1	26774	107	0	0
T2	3244	51	0	0
T3	872636	10733	0	0
T12	48401	235	0	0
T13	627	12	0	0
T14	18913	152	0	0
T15	935560	70	0	0
T16	47478	406	0	0
T17	4316	42	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1461819	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1461819	0	0
T1	26774	252	0	0
T2	3244	48	0	0
T3	872636	147	0	0
T12	48401	271	0	0
T13	627	13	0	0
T14	18913	103	0	0
T15	935560	285	0	0
T16	47478	221	0	0
T17	4316	39	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2714014	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2714014	0	0
T1	26774	122	0	0
T2	3244	48	0	0
T3	872636	13690	0	0
T12	48401	173	0	0
T13	627	13	0	0
T14	18913	152	0	0
T15	935560	63	0	0
T16	47478	177	0	0
T17	4316	39	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1492667	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1492667	0	0
T1	26774	238	0	0
T2	3244	61	0	0
T3	872636	181	0	0
T12	48401	391	0	0
T13	627	11	0	0
T14	18913	191	0	0
T15	935560	287	0	0
T16	47478	362	0	0
T17	4316	45	0	0
T18	431	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3688540	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3688540	0	0
T1	26774	95	0	0
T2	3244	61	0	0
T3	872636	11833	0	0
T12	48401	360	0	0
T13	627	11	0	0
T14	18913	176	0	0
T15	935560	412	0	0
T16	47478	398	0	0
T17	4316	45	0	0
T18	431	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1462124	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1462124	0	0
T1	26774	276	0	0
T2	3244	51	0	0
T3	872636	163	0	0
T12	48401	279	0	0
T13	627	6	0	0
T14	18913	160	0	0
T15	935560	297	0	0
T16	47478	543	0	0
T17	4316	53	0	0
T18	431	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3295431	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3295431	0	0
T1	26774	85	0	0
T2	3244	51	0	0
T3	872636	15250	0	0
T12	48401	209	0	0
T13	627	6	0	0
T14	18913	109	0	0
T15	935560	67	0	0
T16	47478	577	0	0
T17	4316	53	0	0
T18	431	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1432849	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1432849	0	0
T1	26774	208	0	0
T2	3244	59	0	0
T3	872636	111	0	0
T12	48401	245	0	0
T13	627	9	0	0
T14	18913	80	0	0
T15	935560	341	0	0
T16	47478	302	0	0
T17	4316	38	0	0
T18	431	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2766368	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2766368	0	0
T1	26774	117	0	0
T2	3244	59	0	0
T3	872636	12048	0	0
T12	48401	247	0	0
T13	627	9	0	0
T14	18913	111	0	0
T15	935560	911	0	0
T16	47478	379	0	0
T17	4316	38	0	0
T18	431	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1482246	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1482246	0	0
T1	26774	267	0	0
T2	3244	41	0	0
T3	872636	171	0	0
T12	48401	336	0	0
T13	627	5	0	0
T14	18913	111	0	0
T15	935560	275	0	0
T16	47478	344	0	0
T17	4316	34	0	0
T18	431	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3342847	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3342847	0	0
T1	26774	83	0	0
T2	3244	41	0	0
T3	872636	13215	0	0
T12	48401	278	0	0
T13	627	5	0	0
T14	18913	115	0	0
T15	935560	1043	0	0
T16	47478	367	0	0
T17	4316	34	0	0
T18	431	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1470540	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1470540	0	0
T1	26774	283	0	0
T2	3244	59	0	0
T3	872636	132	0	0
T12	48401	309	0	0
T13	627	4	0	0
T14	18913	68	0	0
T15	935560	263	0	0
T16	47478	392	0	0
T17	4316	34	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3333654	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3333654	0	0
T1	26774	84	0	0
T2	3244	59	0	0
T3	872636	9120	0	0
T12	48401	245	0	0
T13	627	4	0	0
T14	18913	73	0	0
T15	935560	71	0	0
T16	47478	373	0	0
T17	4316	34	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1495010	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1495010	0	0
T1	26774	242	0	0
T2	3244	44	0	0
T3	872636	182	0	0
T12	48401	238	0	0
T13	627	11	0	0
T14	18913	134	0	0
T15	935560	364	0	0
T16	47478	387	0	0
T17	4316	42	0	0
T18	431	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	4005686	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	4005686	0	0
T1	26774	78	0	0
T2	3244	44	0	0
T3	872636	18882	0	0
T12	48401	300	0	0
T13	627	11	0	0
T14	18913	141	0	0
T15	935560	157	0	0
T16	47478	373	0	0
T17	4316	42	0	0
T18	431	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1465569	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1465569	0	0
T1	26774	182	0	0
T2	3244	50	0	0
T3	872636	163	0	0
T12	48401	281	0	0
T13	627	9	0	0
T14	18913	85	0	0
T15	935560	309	0	0
T16	47478	430	0	0
T17	4316	42	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3422693	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3422693	0	0
T1	26774	103	0	0
T2	3244	50	0	0
T3	872636	14867	0	0
T12	48401	206	0	0
T13	627	9	0	0
T14	18913	68	0	0
T15	935560	68	0	0
T16	47478	439	0	0
T17	4316	42	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1475601	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1475601	0	0
T1	26774	316	0	0
T2	3244	54	0	0
T3	872636	173	0	0
T12	48401	344	0	0
T13	627	5	0	0
T14	18913	121	0	0
T15	935560	271	0	0
T16	47478	340	0	0
T17	4316	34	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2315365	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2315365	0	0
T1	26774	126	0	0
T2	3244	54	0	0
T3	872636	13897	0	0
T12	48401	303	0	0
T13	627	5	0	0
T14	18913	84	0	0
T15	935560	59	0	0
T16	47478	419	0	0
T17	4316	34	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1426617	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1426617	0	0
T1	26774	275	0	0
T2	3244	59	0	0
T3	872636	97	0	0
T12	48401	408	0	0
T13	627	17	0	0
T14	18913	87	0	0
T15	935560	318	0	0
T16	47478	263	0	0
T17	4316	38	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2830216	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2830216	0	0
T1	26774	107	0	0
T2	3244	59	0	0
T3	872636	10136	0	0
T12	48401	343	0	0
T13	627	17	0	0
T14	18913	89	0	0
T15	935560	78	0	0
T16	47478	335	0	0
T17	4316	38	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1502653	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1502653	0	0
T1	26774	236	0	0
T2	3244	62	0	0
T3	872636	152	0	0
T12	48401	419	0	0
T13	627	4	0	0
T14	18913	95	0	0
T15	935560	376	0	0
T16	47478	380	0	0
T17	4316	37	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3150752	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3150752	0	0
T1	26774	74	0	0
T2	3244	62	0	0
T3	872636	14166	0	0
T12	48401	317	0	0
T13	627	4	0	0
T14	18913	93	0	0
T15	935560	873	0	0
T16	47478	283	0	0
T17	4316	37	0	0
T18	431	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1437040	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1437040	0	0
T1	26774	297	0	0
T2	3244	41	0	0
T3	872636	123	0	0
T12	48401	227	0	0
T13	627	13	0	0
T14	18913	163	0	0
T15	935560	293	0	0
T16	47478	360	0	0
T17	4316	32	0	0
T18	431	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2782493	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2782493	0	0
T1	26774	118	0	0
T2	3244	41	0	0
T3	872636	13770	0	0
T12	48401	143	0	0
T13	627	13	0	0
T14	18913	139	0	0
T15	935560	353	0	0
T16	47478	261	0	0
T17	4316	32	0	0
T18	431	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1448346	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1448346	0	0
T1	26774	208	0	0
T2	3244	54	0	0
T3	872636	120	0	0
T12	48401	304	0	0
T13	627	7	0	0
T14	18913	134	0	0
T15	935560	332	0	0
T16	47478	453	0	0
T17	4316	40	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	2440108	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	2440108	0	0
T1	26774	108	0	0
T2	3244	54	0	0
T3	872636	8838	0	0
T12	48401	213	0	0
T13	627	7	0	0
T14	18913	135	0	0
T15	935560	69	0	0
T16	47478	419	0	0
T17	4316	40	0	0
T18	431	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1500276	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1500276	0	0
T1	26774	241	0	0
T2	3244	51	0	0
T3	872636	138	0	0
T12	48401	345	0	0
T13	627	9	0	0
T14	18913	59	0	0
T15	935560	300	0	0
T16	47478	382	0	0
T17	4316	34	0	0
T18	431	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3001586	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3001586	0	0
T1	26774	105	0	0
T2	3244	51	0	0
T3	872636	12884	0	0
T12	48401	250	0	0
T13	627	9	0	0
T14	18913	101	0	0
T15	935560	829	0	0
T16	47478	368	0	0
T17	4316	34	0	0
T18	431	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	1439419	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	1439419	0	0
T1	26774	277	0	0
T2	3244	49	0	0
T3	872636	93	0	0
T12	48401	343	0	0
T13	627	4	0	0
T14	18913	130	0	0
T15	935560	326	0	0
T16	47478	438	0	0
T17	4316	41	0	0
T18	431	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301921544	3178249	0	0
DepthKnown_A	301921544	301801543	0	0
RvalidKnown_A	301921544	301801543	0	0
WreadyKnown_A	301921544	301801543	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	3178249	0	0
T1	26774	89	0	0
T2	3244	49	0	0
T3	872636	9648	0	0
T12	48401	325	0	0
T13	627	4	0	0
T14	18913	91	0	0
T15	935560	78	0	0
T16	47478	321	0	0
T17	4316	41	0	0
T18	431	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301921544	301801543	0	0
T1	26774	26742	0	0
T2	3244	3172	0	0
T3	872636	872607	0	0
T12	48401	48371	0	0
T13	627	602	0	0
T14	18913	18898	0	0
T15	935560	935544	0	0
T16	47478	47416	0	0
T17	4316	4226	0	0
T18	431	419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0