Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1834298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

288359

1

T2

17

T3

15

T4

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	717821	1			T1	1		T2	43		T3	37
values[0x0]	686984	1			T1	1		T2	40		T3	40
values[0x1]	717852	1			T1	4		T2	30		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1422478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

700179

1

T1

3

T2

40

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7915	1			T13	9		T9	1		T20	8
valid_sources[0x01]	8341	1			T13	11		T20	2		T12	6
valid_sources[0x02]	7784	1			T4	1		T13	18		T20	3
valid_sources[0x03]	8495	1			T4	1		T13	13		T20	4
valid_sources[0x04]	7491	1			T13	27		T20	4		T12	8
valid_sources[0x05]	8082	1			T16	3		T13	12		T9	1
valid_sources[0x06]	7632	1			T2	1		T15	2		T13	17
valid_sources[0x07]	9314	1			T15	5		T13	22		T20	6
valid_sources[0x08]	7250	1			T16	2		T13	15		T9	1
valid_sources[0x09]	8181	1			T2	1		T13	18		T9	4
valid_sources[0x0a]	8111	1			T4	1		T16	1		T13	21
valid_sources[0x0b]	7574	1			T3	1		T16	1		T13	22
valid_sources[0x0c]	9026	1			T13	11		T20	6		T12	5
valid_sources[0x0d]	8365	1			T3	1		T16	1		T13	12
valid_sources[0x0e]	7807	1			T4	1		T13	23		T9	1
valid_sources[0x0f]	8099	1			T4	2		T13	17		T20	7
valid_sources[0x10]	8252	1			T5	1		T13	16		T20	1
valid_sources[0x11]	7948	1			T2	1		T13	30		T9	2
valid_sources[0x12]	7902	1			T4	1		T13	17		T20	2
valid_sources[0x13]	9714	1			T16	1		T13	19		T20	11
valid_sources[0x14]	8986	1			T13	11		T20	5		T12	8
valid_sources[0x15]	9128	1			T3	1		T13	13		T9	3
valid_sources[0x16]	8591	1			T13	17		T9	1		T20	1
valid_sources[0x17]	8100	1			T13	13		T9	1		T20	2
valid_sources[0x18]	7719	1			T3	2		T13	12		T20	4
valid_sources[0x19]	9058	1			T4	1		T15	9		T13	12
valid_sources[0x1a]	7892	1			T13	18		T9	26		T20	2
valid_sources[0x1b]	7946	1			T2	1		T15	6		T13	26
valid_sources[0x1c]	7643	1			T3	1		T16	2		T13	12
valid_sources[0x1d]	8402	1			T2	1		T16	1		T13	11
valid_sources[0x1e]	8717	1			T13	19		T9	2		T20	3
valid_sources[0x1f]	7876	1			T4	1		T16	1		T13	17
valid_sources[0x20]	7771	1			T4	1		T13	20		T9	2
valid_sources[0x21]	7643	1			T2	3		T4	1		T13	18
valid_sources[0x22]	7727	1			T13	9		T9	26		T20	7
valid_sources[0x23]	7837	1			T4	1		T15	4		T13	10
valid_sources[0x24]	9135	1			T4	1		T13	15		T12	13
valid_sources[0x25]	8950	1			T13	17		T9	7		T20	8
valid_sources[0x26]	8369	1			T2	3		T3	2		T4	1
valid_sources[0x27]	7986	1			T3	1		T16	1		T13	11
valid_sources[0x28]	7338	1			T4	2		T13	17		T9	2
valid_sources[0x29]	7632	1			T16	2		T13	23		T9	4
valid_sources[0x2a]	7791	1			T4	1		T15	2		T13	18
valid_sources[0x2b]	7747	1			T16	1		T13	19		T20	5
valid_sources[0x2c]	8214	1			T2	2		T3	2		T4	1
valid_sources[0x2d]	8828	1			T2	8		T16	4		T13	22
valid_sources[0x2e]	9388	1			T4	1		T13	14		T9	3
valid_sources[0x2f]	8200	1			T2	1		T16	2		T13	10
valid_sources[0x30]	7501	1			T4	1		T16	4		T13	12
valid_sources[0x31]	7875	1			T4	1		T13	13		T20	5
valid_sources[0x32]	7164	1			T13	18		T20	1		T12	6
valid_sources[0x33]	7374	1			T4	1		T13	18		T20	6
valid_sources[0x34]	8298	1			T3	1		T13	13		T20	6
valid_sources[0x35]	7824	1			T3	3		T13	23		T20	1
valid_sources[0x36]	8603	1			T4	1		T13	24		T20	2
valid_sources[0x37]	8723	1			T15	4		T13	23		T9	2
valid_sources[0x38]	8662	1			T2	3		T13	14		T9	1
valid_sources[0x39]	8612	1			T2	1		T3	1		T4	1
valid_sources[0x3a]	8066	1			T13	19		T9	2		T20	4
valid_sources[0x3b]	8456	1			T2	3		T16	2		T13	29
valid_sources[0x3c]	8206	1			T15	4		T13	11		T20	1
valid_sources[0x3d]	10091	1			T3	2		T13	19		T20	3
valid_sources[0x3e]	7195	1			T4	2		T13	10		T9	1
valid_sources[0x3f]	7905	1			T13	11		T20	1		T12	10
valid_sources[0x40]	8718	1			T16	1		T13	19		T9	3
valid_sources[0x41]	7694	1			T4	1		T13	5		T20	6
valid_sources[0x42]	7725	1			T2	9		T13	13		T9	1
valid_sources[0x43]	9110	1			T3	3		T13	13		T9	9
valid_sources[0x44]	7550	1			T1	1		T16	1		T13	10
valid_sources[0x45]	8489	1			T13	15		T9	1		T20	5
valid_sources[0x46]	8503	1			T3	1		T16	4		T13	12
valid_sources[0x47]	8270	1			T5	34		T15	14		T13	13
valid_sources[0x48]	8764	1			T2	1		T4	2		T16	1
valid_sources[0x49]	7819	1			T4	1		T16	4		T13	9
valid_sources[0x4a]	9115	1			T13	29		T14	3		T20	3
valid_sources[0x4b]	7908	1			T4	1		T13	27		T20	2
valid_sources[0x4c]	8207	1			T2	1		T13	12		T9	3
valid_sources[0x4d]	7495	1			T4	1		T13	12		T9	2
valid_sources[0x4e]	8188	1			T3	2		T4	1		T16	1
valid_sources[0x4f]	8785	1			T13	15		T9	11		T20	3
valid_sources[0x50]	7999	1			T2	2		T4	2		T13	8
valid_sources[0x51]	7844	1			T2	2		T3	1		T13	14
valid_sources[0x52]	7500	1			T4	1		T16	2		T13	19
valid_sources[0x53]	8900	1			T16	2		T13	20		T14	4
valid_sources[0x54]	9385	1			T16	2		T13	13		T9	1
valid_sources[0x55]	7496	1			T4	2		T13	13		T20	3
valid_sources[0x56]	8250	1			T13	11		T20	6		T12	8
valid_sources[0x57]	7372	1			T13	25		T20	2		T12	4
valid_sources[0x58]	7722	1			T2	1		T4	1		T16	2
valid_sources[0x59]	8019	1			T2	1		T16	1		T13	23
valid_sources[0x5a]	8698	1			T13	11		T20	2		T12	6
valid_sources[0x5b]	7824	1			T4	1		T13	9		T20	5
valid_sources[0x5c]	8296	1			T2	2		T3	2		T13	12
valid_sources[0x5d]	8474	1			T13	14		T9	2		T20	3
valid_sources[0x5e]	7636	1			T3	1		T4	1		T13	18
valid_sources[0x5f]	8469	1			T13	10		T9	12		T20	2
valid_sources[0x60]	7997	1			T4	1		T13	14		T14	17
valid_sources[0x61]	8089	1			T3	1		T15	6		T13	16
valid_sources[0x62]	7858	1			T15	1		T13	23		T9	1
valid_sources[0x63]	7476	1			T13	16		T20	5		T12	9
valid_sources[0x64]	9363	1			T13	20		T9	1		T20	4
valid_sources[0x65]	8507	1			T2	1		T3	1		T13	16
valid_sources[0x66]	8628	1			T13	10		T9	1		T20	4
valid_sources[0x67]	8064	1			T4	1		T16	1		T13	15
valid_sources[0x68]	8371	1			T13	17		T9	4		T20	2
valid_sources[0x69]	8362	1			T13	25		T9	1		T20	1
valid_sources[0x6a]	8964	1			T13	15		T20	3		T12	10
valid_sources[0x6b]	8432	1			T13	18		T9	32		T20	1
valid_sources[0x6c]	8557	1			T2	2		T4	1		T15	1
valid_sources[0x6d]	7969	1			T2	3		T13	16		T20	2
valid_sources[0x6e]	7645	1			T13	21		T9	20		T20	5
valid_sources[0x6f]	8115	1			T16	2		T13	22		T20	3
valid_sources[0x70]	7940	1			T3	4		T4	1		T13	13
valid_sources[0x71]	7423	1			T13	19		T9	2		T20	2
valid_sources[0x72]	9241	1			T3	1		T13	15		T20	6
valid_sources[0x73]	11166	1			T3	2		T13	11		T9	1
valid_sources[0x74]	7369	1			T15	2		T13	23		T20	3
valid_sources[0x75]	9487	1			T1	2		T3	2		T13	19
valid_sources[0x76]	8023	1			T2	3		T3	5		T13	11
valid_sources[0x77]	8934	1			T13	7		T20	5		T12	6
valid_sources[0x78]	8144	1			T4	1		T13	10		T9	3
valid_sources[0x79]	7902	1			T3	1		T13	19		T20	5
valid_sources[0x7a]	9059	1			T13	10		T12	11		T19	3
valid_sources[0x7b]	9281	1			T4	2		T13	13		T20	4
valid_sources[0x7c]	7764	1			T2	1		T13	9		T9	6
valid_sources[0x7d]	8443	1			T4	1		T16	1		T13	21
valid_sources[0x7e]	8039	1			T13	17		T20	5		T12	3
valid_sources[0x7f]	9012	1			T13	9		T9	1		T20	5
valid_sources[0x80]	8393	1			T4	1		T13	11		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30295

1

T2

1

T4

4

T5

5

values[0x0]

all_enables

biggest_size

227680

1

T2

14

T3

13

T4

4

values[0x1]

all_enables

biggest_size

30384

1

T2

2

T3

2

T4

4