Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	327035487	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	327035487	0	0
T1	161896	2873	0	0
T2	25200	560	0	0
T3	33432	567	0	0
T4	2528344	36712	0	0
T5	210728	3655	0	0
T9	1845760	74507	0	0
T13	6179376	136850	0	0
T14	148624	4577	0	0
T15	6067376	114317	0	0
T16	19712	503	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161896	160664	0	0
T2	25200	23072	0	0
T3	33432	31360	0	0
T4	2528344	2526608	0	0
T5	210728	209328	0	0
T9	1845760	1791608	0	0
T13	6179376	6177920	0	0
T14	148624	144816	0	0
T15	6067376	6066088	0	0
T16	19712	18536	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161896	160664	0	0
T2	25200	23072	0	0
T3	33432	31360	0	0
T4	2528344	2526608	0	0
T5	210728	209328	0	0
T9	1845760	1791608	0	0
T13	6179376	6177920	0	0
T14	148624	144816	0	0
T15	6067376	6066088	0	0
T16	19712	18536	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161896	160664	0	0
T2	25200	23072	0	0
T3	33432	31360	0	0
T4	2528344	2526608	0	0
T5	210728	209328	0	0
T9	1845760	1791608	0	0
T13	6179376	6177920	0	0
T14	148624	144816	0	0
T15	6067376	6066088	0	0
T16	19712	18536	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T9	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	119100325	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	119100325	0	0
T1	2891	1239	0	0
T2	450	221	0	0
T3	597	219	0	0
T4	45149	16962	0	0
T5	3763	1649	0	0
T9	32960	29891	0	0
T13	110346	54235	0	0
T14	2654	2087	0	0
T15	108346	51742	0	0
T16	352	194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	85054499	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	85054499	0	0
T1	2891	372	0	0
T2	450	113	0	0
T3	597	116	0	0
T4	45149	5509	0	0
T5	3763	448	0	0
T9	32960	16117	0	0
T13	110346	35879	0	0
T14	2654	1222	0	0
T15	108346	13530	0	0
T16	352	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1441718	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1441718	0	0
T1	2891	37	0	0
T2	450	8	0	0
T3	597	1	0	0
T4	45149	392	0	0
T5	3763	52	0	0
T9	32960	866	0	0
T13	110346	899	0	0
T14	2654	25	0	0
T15	108346	2822	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2557946	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2557946	0	0
T1	2891	8	0	0
T2	450	8	0	0
T3	597	1	0	0
T4	45149	164	0	0
T5	3763	33	0	0
T9	32960	866	0	0
T13	110346	940	0	0
T14	2654	25	0	0
T15	108346	704	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1449319	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1449319	0	0
T1	2891	39	0	0
T2	450	3	0	0
T3	597	2	0	0
T4	45149	397	0	0
T5	3763	54	0	0
T9	32960	652	0	0
T13	110346	857	0	0
T14	2654	32	0	0
T15	108346	820	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2831239	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2831239	0	0
T1	2891	23	0	0
T2	450	3	0	0
T3	597	2	0	0
T4	45149	147	0	0
T5	3763	22	0	0
T9	32960	652	0	0
T13	110346	905	0	0
T14	2654	32	0	0
T15	108346	263	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1442834	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1442834	0	0
T1	2891	26	0	0
T2	450	3	0	0
T3	597	4	0	0
T4	45149	423	0	0
T5	3763	11	0	0
T9	32960	420	0	0
T13	110346	852	0	0
T14	2654	13	0	0
T15	108346	44	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3313109	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3313109	0	0
T1	2891	19	0	0
T2	450	3	0	0
T3	597	4	0	0
T4	45149	165	0	0
T5	3763	10	0	0
T9	32960	419	0	0
T13	110346	974	0	0
T14	2654	13	0	0
T15	108346	1	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1409265	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1409265	0	0
T1	2891	48	0	0
T2	450	7	0	0
T3	597	6	0	0
T4	45149	381	0	0
T5	3763	25	0	0
T9	32960	406	0	0
T13	110346	866	0	0
T14	2654	22	0	0
T15	108346	1492	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3343805	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3343805	0	0
T1	2891	11	0	0
T2	450	7	0	0
T3	597	6	0	0
T4	45149	172	0	0
T5	3763	15	0	0
T9	32960	406	0	0
T13	110346	810	0	0
T14	2654	22	0	0
T15	108346	280	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1442101	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1442101	0	0
T1	2891	9	0	0
T2	450	3	0	0
T3	597	1	0	0
T4	45149	514	0	0
T5	3763	11	0	0
T9	32960	395	0	0
T13	110346	716	0	0
T14	2654	28	0	0
T15	108346	996	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3218997	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3218997	0	0
T1	2891	9	0	0
T2	450	3	0	0
T3	597	1	0	0
T4	45149	182	0	0
T5	3763	6	0	0
T9	32960	395	0	0
T13	110346	895	0	0
T14	2654	28	0	0
T15	108346	338	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1506739	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1506739	0	0
T1	2891	37	0	0
T2	450	3	0	0
T3	597	3	0	0
T4	45149	359	0	0
T5	3763	19	0	0
T9	32960	470	0	0
T13	110346	1044	0	0
T14	2654	33	0	0
T15	108346	3693	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2958655	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2958655	0	0
T1	2891	10	0	0
T2	450	3	0	0
T3	597	3	0	0
T4	45149	146	0	0
T5	3763	5	0	0
T9	32960	470	0	0
T13	110346	1015	0	0
T14	2654	33	0	0
T15	108346	2597	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1418099	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1418099	0	0
T1	2891	42	0	0
T2	450	6	0	0
T3	597	3	0	0
T4	45149	356	0	0
T5	3763	51	0	0
T9	32960	411	0	0
T13	110346	661	0	0
T14	2654	26	0	0
T15	108346	588	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2490363	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2490363	0	0
T1	2891	24	0	0
T2	450	6	0	0
T3	597	3	0	0
T4	45149	189	0	0
T5	3763	6	0	0
T9	32960	411	0	0
T13	110346	792	0	0
T14	2654	26	0	0
T15	108346	1	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1439421	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1439421	0	0
T1	2891	10	0	0
T2	450	2	0	0
T3	597	5	0	0
T4	45149	325	0	0
T5	3763	63	0	0
T9	32960	613	0	0
T13	110346	868	0	0
T14	2654	26	0	0
T15	108346	1312	0	0
T16	352	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3026444	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3026444	0	0
T1	2891	2	0	0
T2	450	2	0	0
T3	597	5	0	0
T4	45149	96	0	0
T5	3763	13	0	0
T9	32960	613	0	0
T13	110346	727	0	0
T14	2654	26	0	0
T15	108346	614	0	0
T16	352	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1376713	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1376713	0	0
T1	2891	24	0	0
T2	450	5	0	0
T3	597	3	0	0
T4	45149	472	0	0
T5	3763	36	0	0
T9	32960	375	0	0
T13	110346	922	0	0
T14	2654	22	0	0
T15	108346	1832	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2613622	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2613622	0	0
T1	2891	19	0	0
T2	450	5	0	0
T3	597	3	0	0
T4	45149	190	0	0
T5	3763	21	0	0
T9	32960	375	0	0
T13	110346	882	0	0
T14	2654	22	0	0
T15	108346	872	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1460329	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1460329	0	0
T1	2891	33	0	0
T2	450	2	0	0
T3	597	6	0	0
T4	45149	453	0	0
T5	3763	35	0	0
T9	32960	437	0	0
T13	110346	736	0	0
T14	2654	29	0	0
T15	108346	1471	0	0
T16	352	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3221581	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3221581	0	0
T1	2891	13	0	0
T2	450	2	0	0
T3	597	6	0	0
T4	45149	175	0	0
T5	3763	26	0	0
T9	32960	437	0	0
T13	110346	700	0	0
T14	2654	29	0	0
T15	108346	728	0	0
T16	352	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1427237	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1427237	0	0
T1	2891	32	0	0
T2	450	3	0	0
T3	597	12	0	0
T4	45149	239	0	0
T5	3763	35	0	0
T9	32960	652	0	0
T13	110346	781	0	0
T14	2654	19	0	0
T15	108346	2227	0	0
T16	352	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3921555	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3921555	0	0
T1	2891	8	0	0
T2	450	3	0	0
T3	597	12	0	0
T4	45149	62	0	0
T5	3763	18	0	0
T9	32960	652	0	0
T13	110346	847	0	0
T14	2654	19	0	0
T15	108346	486	0	0
T16	352	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1427960	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1427960	0	0
T1	2891	24	0	0
T2	450	5	0	0
T3	597	7	0	0
T4	45149	270	0	0
T5	3763	47	0	0
T9	32960	420	0	0
T13	110346	833	0	0
T14	2654	21	0	0
T15	108346	1982	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3659760	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3659760	0	0
T1	2891	8	0	0
T2	450	5	0	0
T3	597	7	0	0
T4	45149	98	0	0
T5	3763	6	0	0
T9	32960	420	0	0
T13	110346	923	0	0
T14	2654	21	0	0
T15	108346	957	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1426231	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1426231	0	0
T1	2891	17	0	0
T2	450	4	0	0
T3	597	5	0	0
T4	45149	342	0	0
T5	3763	33	0	0
T9	32960	407	0	0
T13	110346	836	0	0
T14	2654	12	0	0
T15	108346	2383	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2673238	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2673238	0	0
T1	2891	9	0	0
T2	450	4	0	0
T3	597	5	0	0
T4	45149	139	0	0
T5	3763	8	0	0
T9	32960	407	0	0
T13	110346	887	0	0
T14	2654	12	0	0
T15	108346	679	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1450808	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1450808	0	0
T1	2891	62	0	0
T2	450	4	0	0
T3	597	8	0	0
T4	45149	359	0	0
T5	3763	31	0	0
T9	32960	373	0	0
T13	110346	975	0	0
T14	2654	20	0	0
T15	108346	835	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2479263	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2479263	0	0
T1	2891	45	0	0
T2	450	4	0	0
T3	597	8	0	0
T4	45149	144	0	0
T5	3763	10	0	0
T9	32960	373	0	0
T13	110346	1064	0	0
T14	2654	20	0	0
T15	108346	306	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1449893	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1449893	0	0
T1	2891	19	0	0
T2	450	4	0	0
T3	597	3	0	0
T4	45149	385	0	0
T5	3763	39	0	0
T9	32960	718	0	0
T13	110346	788	0	0
T14	2654	19	0	0
T15	108346	330	0	0
T16	352	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3786344	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3786344	0	0
T1	2891	10	0	0
T2	450	4	0	0
T3	597	3	0	0
T4	45149	231	0	0
T5	3763	9	0	0
T9	32960	716	0	0
T13	110346	697	0	0
T14	2654	19	0	0
T15	108346	449	0	0
T16	352	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1423147	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1423147	0	0
T1	2891	42	0	0
T2	450	3	0	0
T3	597	8	0	0
T4	45149	384	0	0
T5	3763	56	0	0
T9	32960	698	0	0
T13	110346	1025	0	0
T14	2654	22	0	0
T15	108346	1242	0	0
T16	352	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3736583	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3736583	0	0
T1	2891	4	0	0
T2	450	3	0	0
T3	597	8	0	0
T4	45149	152	0	0
T5	3763	25	0	0
T9	32960	698	0	0
T13	110346	963	0	0
T14	2654	22	0	0
T15	108346	290	0	0
T16	352	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1428111	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1428111	0	0
T1	2891	58	0	0
T2	450	4	0	0
T3	597	4	0	0
T4	45149	303	0	0
T5	3763	24	0	0
T9	32960	520	0	0
T13	110346	759	0	0
T14	2654	25	0	0
T15	108346	231	0	0
T16	352	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3473494	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3473494	0	0
T1	2891	22	0	0
T2	450	4	0	0
T3	597	4	0	0
T4	45149	111	0	0
T5	3763	10	0	0
T9	32960	520	0	0
T13	110346	755	0	0
T14	2654	25	0	0
T15	108346	201	0	0
T16	352	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1419232	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1419232	0	0
T1	2891	57	0	0
T2	450	5	0	0
T3	597	2	0	0
T4	45149	442	0	0
T5	3763	97	0	0
T9	32960	372	0	0
T13	110346	895	0	0
T14	2654	27	0	0
T15	108346	585	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2746961	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2746961	0	0
T1	2891	18	0	0
T2	450	5	0	0
T3	597	2	0	0
T4	45149	132	0	0
T5	3763	29	0	0
T9	32960	372	0	0
T13	110346	904	0	0
T14	2654	27	0	0
T15	108346	300	0	0
T16	352	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1415384	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1415384	0	0
T1	2891	30	0	0
T2	450	5	0	0
T3	597	2	0	0
T4	45149	364	0	0
T5	3763	56	0	0
T9	32960	847	0	0
T13	110346	972	0	0
T14	2654	23	0	0
T15	108346	933	0	0
T16	352	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2904878	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2904878	0	0
T1	2891	16	0	0
T2	450	5	0	0
T3	597	2	0	0
T4	45149	159	0	0
T5	3763	7	0	0
T9	32960	847	0	0
T13	110346	982	0	0
T14	2654	23	0	0
T15	108346	291	0	0
T16	352	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1449684	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1449684	0	0
T1	2891	33	0	0
T2	450	6	0	0
T3	597	3	0	0
T4	45149	409	0	0
T5	3763	49	0	0
T9	32960	640	0	0
T13	110346	726	0	0
T14	2654	30	0	0
T15	108346	173	0	0
T16	352	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2921089	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2921089	0	0
T1	2891	16	0	0
T2	450	6	0	0
T3	597	3	0	0
T4	45149	172	0	0
T5	3763	18	0	0
T9	32960	639	0	0
T13	110346	817	0	0
T14	2654	30	0	0
T15	108346	229	0	0
T16	352	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1494257	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1494257	0	0
T1	2891	24	0	0
T2	450	2	0	0
T3	597	8	0	0
T4	45149	328	0	0
T5	3763	69	0	0
T9	32960	644	0	0
T13	110346	737	0	0
T14	2654	24	0	0
T15	108346	643	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3659883	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3659883	0	0
T1	2891	32	0	0
T2	450	2	0	0
T3	597	8	0	0
T4	45149	184	0	0
T5	3763	38	0	0
T9	32960	644	0	0
T13	110346	794	0	0
T14	2654	24	0	0
T15	108346	204	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1432828	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1432828	0	0
T1	2891	73	0	0
T2	450	4	0	0
T3	597	1	0	0
T4	45149	392	0	0
T5	3763	33	0	0
T9	32960	623	0	0
T13	110346	855	0	0
T14	2654	19	0	0
T15	108346	1381	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3219979	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3219979	0	0
T1	2891	13	0	0
T2	450	4	0	0
T3	597	1	0	0
T4	45149	149	0	0
T5	3763	15	0	0
T9	32960	623	0	0
T13	110346	922	0	0
T14	2654	19	0	0
T15	108346	342	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1437677	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1437677	0	0
T1	2891	20	0	0
T2	450	9	0	0
T3	597	3	0	0
T4	45149	393	0	0
T5	3763	32	0	0
T9	32960	397	0	0
T13	110346	869	0	0
T14	2654	24	0	0
T15	108346	643	0	0
T16	352	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2891075	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2891075	0	0
T1	2891	9	0	0
T2	450	9	0	0
T3	597	3	0	0
T4	45149	116	0	0
T5	3763	24	0	0
T9	32960	397	0	0
T13	110346	903	0	0
T14	2654	24	0	0
T15	108346	347	0	0
T16	352	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1422435	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1422435	0	0
T1	2891	9	0	0
T2	450	3	0	0
T3	597	4	0	0
T4	45149	410	0	0
T5	3763	88	0	0
T9	32960	678	0	0
T13	110346	813	0	0
T14	2654	22	0	0
T15	108346	2499	0	0
T16	352	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2947731	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2947731	0	0
T1	2891	1	0	0
T2	450	3	0	0
T3	597	4	0	0
T4	45149	175	0	0
T5	3763	28	0	0
T9	32960	678	0	0
T13	110346	897	0	0
T14	2654	22	0	0
T15	108346	778	0	0
T16	352	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1450589	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1450589	0	0
T1	2891	36	0	0
T2	450	5	0	0
T3	597	4	0	0
T4	45149	396	0	0
T5	3763	6	0	0
T9	32960	399	0	0
T13	110346	1013	0	0
T14	2654	30	0	0
T15	108346	2140	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	2760318	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	2760318	0	0
T1	2891	8	0	0
T2	450	5	0	0
T3	597	4	0	0
T4	45149	200	0	0
T5	3763	9	0	0
T9	32960	399	0	0
T13	110346	985	0	0
T14	2654	30	0	0
T15	108346	1136	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1438599	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1438599	0	0
T1	2891	23	0	0
T2	450	2	0	0
T3	597	7	0	0
T4	45149	255	0	0
T5	3763	33	0	0
T9	32960	402	0	0
T13	110346	810	0	0
T14	2654	20	0	0
T15	108346	797	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3168674	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3168674	0	0
T1	2891	3	0	0
T2	450	2	0	0
T3	597	7	0	0
T4	45149	108	0	0
T5	3763	29	0	0
T9	32960	401	0	0
T13	110346	836	0	0
T14	2654	20	0	0
T15	108346	3	0	0
T16	352	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	1405759	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	1405759	0	0
T1	2891	26	0	0
T2	450	3	0	0
T3	597	1	0	0
T4	45149	401	0	0
T5	3763	25	0	0
T9	32960	417	0	0
T13	110346	892	0	0
T14	2654	21	0	0
T15	108346	1421	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306836125	3567708	0	0
DepthKnown_A	306836125	306710055	0	0
RvalidKnown_A	306836125	306710055	0	0
WreadyKnown_A	306836125	306710055	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	3567708	0	0
T1	2891	12	0	0
T2	450	3	0	0
T3	597	1	0	0
T4	45149	139	0	0
T5	3763	8	0	0
T9	32960	417	0	0
T13	110346	920	0	0
T14	2654	21	0	0
T15	108346	134	0	0
T16	352	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306836125	306710055	0	0
T1	2891	2869	0	0
T2	450	412	0	0
T3	597	560	0	0
T4	45149	45118	0	0
T5	3763	3738	0	0
T9	32960	31993	0	0
T13	110346	110320	0	0
T14	2654	2586	0	0
T15	108346	108323	0	0
T16	352	331	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0