Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1814866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

286075

1

T1

19

T2

316

T4

323

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	709902	1			T1	43		T2	826		T4	787
values[0x0]	680585	1			T1	41		T2	797		T4	795
values[0x1]	710454	1			T1	36		T2	763		T4	854

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1407170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

693771

1

T1

37

T2

743

T4

795

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8267	1			T2	10		T4	16		T3	54
valid_sources[0x01]	7581	1			T4	10		T3	47		T5	27
valid_sources[0x02]	8711	1			T4	44		T3	75		T5	30
valid_sources[0x03]	8488	1			T4	16		T3	94		T5	20
valid_sources[0x04]	8464	1			T4	17		T3	27		T5	14
valid_sources[0x05]	7443	1			T3	123		T5	29		T13	14
valid_sources[0x06]	8474	1			T2	67		T4	8		T3	21
valid_sources[0x07]	7507	1			T4	9		T3	9		T5	35
valid_sources[0x08]	8057	1			T4	65		T3	38		T5	32
valid_sources[0x09]	8561	1			T3	56		T5	29		T10	2
valid_sources[0x0a]	9673	1			T4	17		T3	86		T5	28
valid_sources[0x0b]	7019	1			T3	148		T5	39		T12	6
valid_sources[0x0c]	7279	1			T4	15		T3	15		T5	20
valid_sources[0x0d]	8427	1			T4	23		T3	89		T5	28
valid_sources[0x0e]	8261	1			T1	5		T3	113		T5	28
valid_sources[0x0f]	8625	1			T1	6		T4	11		T3	98
valid_sources[0x10]	7873	1			T4	15		T3	46		T5	22
valid_sources[0x11]	7915	1			T4	27		T3	73		T5	33
valid_sources[0x12]	7339	1			T3	28		T5	29		T12	4
valid_sources[0x13]	9428	1			T4	37		T3	34		T5	37
valid_sources[0x14]	8755	1			T4	29		T3	17		T5	21
valid_sources[0x15]	7619	1			T1	2		T2	53		T3	17
valid_sources[0x16]	7883	1			T2	65		T3	107		T5	22
valid_sources[0x17]	7911	1			T2	180		T3	66		T5	30
valid_sources[0x18]	8057	1			T4	15		T3	67		T5	45
valid_sources[0x19]	7896	1			T3	94		T5	45		T10	1
valid_sources[0x1a]	7511	1			T2	25		T4	23		T3	22
valid_sources[0x1b]	7189	1			T2	29		T4	14		T3	22
valid_sources[0x1c]	8143	1			T3	95		T5	46		T12	4
valid_sources[0x1d]	8386	1			T3	54		T5	32		T13	10
valid_sources[0x1e]	8307	1			T1	6		T3	58		T5	62
valid_sources[0x1f]	8643	1			T4	10		T3	133		T5	61
valid_sources[0x20]	8238	1			T4	11		T3	272		T5	31
valid_sources[0x21]	7923	1			T2	91		T3	56		T5	32
valid_sources[0x22]	7790	1			T3	48		T5	33		T12	1
valid_sources[0x23]	8248	1			T1	1		T3	21		T5	26
valid_sources[0x24]	8428	1			T3	50		T5	27		T10	2
valid_sources[0x25]	8503	1			T4	9		T3	25		T5	32
valid_sources[0x26]	8572	1			T3	48		T5	23		T10	4
valid_sources[0x27]	8076	1			T3	9		T5	20		T12	3
valid_sources[0x28]	9426	1			T4	10		T3	16		T5	21
valid_sources[0x29]	7202	1			T2	10		T3	91		T5	35
valid_sources[0x2a]	7878	1			T2	7		T4	24		T3	65
valid_sources[0x2b]	7309	1			T3	14		T5	54		T12	1
valid_sources[0x2c]	7636	1			T2	86		T4	7		T3	88
valid_sources[0x2d]	8548	1			T1	1		T3	29		T5	25
valid_sources[0x2e]	8333	1			T4	16		T3	20		T5	37
valid_sources[0x2f]	7455	1			T3	120		T5	25		T13	14
valid_sources[0x30]	7420	1			T4	18		T3	61		T5	24
valid_sources[0x31]	7895	1			T4	25		T3	48		T5	34
valid_sources[0x32]	7302	1			T2	88		T4	11		T3	56
valid_sources[0x33]	8612	1			T4	14		T3	84		T5	31
valid_sources[0x34]	8678	1			T4	29		T3	110		T5	23
valid_sources[0x35]	8702	1			T4	28		T3	34		T5	33
valid_sources[0x36]	9493	1			T2	17		T3	13		T5	33
valid_sources[0x37]	7302	1			T3	74		T5	20		T12	6
valid_sources[0x38]	9607	1			T2	1		T4	22		T3	11
valid_sources[0x39]	8046	1			T4	17		T3	65		T5	34
valid_sources[0x3a]	8810	1			T3	26		T5	35		T10	6
valid_sources[0x3b]	9629	1			T4	12		T3	12		T5	60
valid_sources[0x3c]	8739	1			T2	30		T4	10		T3	18
valid_sources[0x3d]	7814	1			T2	85		T4	10		T3	17
valid_sources[0x3e]	8622	1			T2	78		T4	26		T3	13
valid_sources[0x3f]	8389	1			T4	7		T3	15		T5	31
valid_sources[0x40]	7282	1			T3	37		T5	33		T12	16
valid_sources[0x41]	7359	1			T2	121		T3	22		T5	24
valid_sources[0x42]	8329	1			T4	29		T3	12		T5	42
valid_sources[0x43]	8641	1			T4	13		T3	14		T5	32
valid_sources[0x44]	7823	1			T2	5		T4	18		T3	11
valid_sources[0x45]	9442	1			T1	1		T2	11		T3	28
valid_sources[0x46]	8155	1			T3	30		T5	55		T13	10
valid_sources[0x47]	8265	1			T3	92		T5	43		T10	1
valid_sources[0x48]	7808	1			T1	3		T4	36		T3	15
valid_sources[0x49]	8974	1			T3	48		T5	22		T13	8
valid_sources[0x4a]	6788	1			T4	44		T3	23		T5	18
valid_sources[0x4b]	8693	1			T2	58		T3	64		T5	42
valid_sources[0x4c]	8217	1			T4	12		T3	12		T5	25
valid_sources[0x4d]	8442	1			T3	27		T5	32		T12	4
valid_sources[0x4e]	7660	1			T1	3		T3	17		T5	41
valid_sources[0x4f]	9022	1			T4	18		T3	52		T5	57
valid_sources[0x50]	7801	1			T4	13		T3	59		T5	26
valid_sources[0x51]	8801	1			T4	25		T3	10		T5	26
valid_sources[0x52]	7336	1			T1	2		T3	36		T5	14
valid_sources[0x53]	8665	1			T3	59		T5	37		T12	4
valid_sources[0x54]	7566	1			T4	18		T3	66		T5	22
valid_sources[0x55]	7764	1			T1	3		T4	13		T3	65
valid_sources[0x56]	7368	1			T1	6		T2	25		T4	15
valid_sources[0x57]	8064	1			T4	16		T3	39		T5	24
valid_sources[0x58]	8516	1			T4	18		T3	36		T5	21
valid_sources[0x59]	8261	1			T2	11		T4	25		T3	84
valid_sources[0x5a]	7327	1			T4	49		T3	28		T5	36
valid_sources[0x5b]	10708	1			T1	8		T2	20		T4	16
valid_sources[0x5c]	8553	1			T3	62		T5	23		T12	2
valid_sources[0x5d]	7550	1			T2	51		T3	53		T5	20
valid_sources[0x5e]	8071	1			T2	9		T4	19		T3	62
valid_sources[0x5f]	8316	1			T2	24		T4	14		T3	87
valid_sources[0x60]	7252	1			T3	49		T5	31		T12	5
valid_sources[0x61]	7384	1			T4	37		T3	155		T5	19
valid_sources[0x62]	7984	1			T3	87		T5	20		T10	1
valid_sources[0x63]	7524	1			T3	11		T5	22		T12	20
valid_sources[0x64]	7270	1			T4	11		T3	75		T5	47
valid_sources[0x65]	7863	1			T1	2		T3	80		T5	52
valid_sources[0x66]	8074	1			T4	12		T3	9		T5	40
valid_sources[0x67]	8386	1			T4	11		T3	83		T5	53
valid_sources[0x68]	7895	1			T3	21		T5	68		T10	3
valid_sources[0x69]	7133	1			T3	125		T5	21		T12	6
valid_sources[0x6a]	8319	1			T4	5		T3	30		T5	36
valid_sources[0x6b]	8414	1			T4	7		T3	68		T5	19
valid_sources[0x6c]	8000	1			T1	1		T4	27		T3	71
valid_sources[0x6d]	7743	1			T2	9		T4	12		T3	35
valid_sources[0x6e]	7561	1			T3	64		T5	20		T12	3
valid_sources[0x6f]	8858	1			T3	64		T5	26		T10	1
valid_sources[0x70]	8052	1			T3	24		T5	23		T13	8
valid_sources[0x71]	6938	1			T4	5		T3	23		T5	28
valid_sources[0x72]	8127	1			T2	58		T3	74		T5	16
valid_sources[0x73]	7466	1			T3	126		T5	31		T12	6
valid_sources[0x74]	8584	1			T1	4		T4	6		T3	50
valid_sources[0x75]	7942	1			T3	96		T5	21		T12	11
valid_sources[0x76]	7691	1			T3	34		T5	29		T10	1
valid_sources[0x77]	7552	1			T1	2		T4	18		T3	17
valid_sources[0x78]	8048	1			T2	54		T3	15		T5	19
valid_sources[0x79]	8039	1			T3	33		T5	47		T10	3
valid_sources[0x7a]	9197	1			T4	18		T3	82		T5	41
valid_sources[0x7b]	7802	1			T2	22		T4	14		T3	28
valid_sources[0x7c]	8677	1			T4	19		T3	54		T5	33
valid_sources[0x7d]	7713	1			T1	5		T4	33		T3	10
valid_sources[0x7e]	7685	1			T2	68		T3	87		T5	46
valid_sources[0x7f]	9052	1			T4	21		T3	29		T5	40
valid_sources[0x80]	7595	1			T3	27		T5	13		T12	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30283

1

T1

4

T2

30

T4

27

values[0x0]

all_enables

biggest_size

225774

1

T1

10

T2

258

T4

268

values[0x1]

all_enables

biggest_size

30018

1

T1

5

T2

28

T4

28