Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	376490021	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	376490021	0	0
T1	227136	4536	0	0
T2	3131072	65751	0	0
T3	15816360	370228	0	0
T4	283472	9722	0	0
T5	10489808	198157	0	0
T10	863576	32717	0	0
T12	1000776	18470	0	0
T13	254464	10990	0	0
T14	1600200	33620	0	0
T15	113680	4161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	227136	225568	0	0
T2	3131072	3128944	0	0
T3	15816360	15807960	0	0
T4	283472	281792	0	0
T5	10489808	10486056	0	0
T10	863576	806904	0	0
T12	1000776	997864	0	0
T13	254464	253176	0	0
T14	1600200	1599248	0	0
T15	113680	113008	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	227136	225568	0	0
T2	3131072	3128944	0	0
T3	15816360	15807960	0	0
T4	283472	281792	0	0
T5	10489808	10486056	0	0
T10	863576	806904	0	0
T12	1000776	997864	0	0
T13	254464	253176	0	0
T14	1600200	1599248	0	0
T15	113680	113008	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	227136	225568	0	0
T2	3131072	3128944	0	0
T3	15816360	15807960	0	0
T4	283472	281792	0	0
T5	10489808	10486056	0	0
T10	863576	806904	0	0
T12	1000776	997864	0	0
T13	254464	253176	0	0
T14	1600200	1599248	0	0
T15	113680	113008	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T10	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	136149371	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	136149371	0	0
T1	4056	1874	0	0
T2	55912	25367	0	0
T3	282435	137787	0	0
T4	5062	2436	0	0
T5	187318	86190	0	0
T10	15421	13652	0	0
T12	17871	8205	0	0
T13	4544	4273	0	0
T14	28575	12665	0	0
T15	2030	1904	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	100904602	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	100904602	0	0
T1	4056	827	0	0
T2	55912	20971	0	0
T3	282435	78591	0	0
T4	5062	2436	0	0
T5	187318	27746	0	0
T10	15421	7218	0	0
T12	17871	2435	0	0
T13	4544	2239	0	0
T14	28575	10708	0	0
T15	2030	1103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1437879	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1437879	0	0
T1	4056	5	0	0
T2	55912	318	0	0
T3	282435	1693	0	0
T4	5062	88	0	0
T5	187318	2236	0	0
T10	15421	138	0	0
T12	17871	198	0	0
T13	4544	83	0	0
T14	28575	229	0	0
T15	2030	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3226159	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3226159	0	0
T1	4056	25	0	0
T2	55912	402	0	0
T3	282435	1586	0	0
T4	5062	88	0	0
T5	187318	920	0	0
T10	15421	138	0	0
T12	17871	110	0	0
T13	4544	83	0	0
T14	28575	185	0	0
T15	2030	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1477525	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1477525	0	0
T1	4056	25	0	0
T2	55912	444	0	0
T3	282435	1658	0	0
T4	5062	102	0	0
T5	187318	1850	0	0
T10	15421	133	0	0
T12	17871	152	0	0
T13	4544	94	0	0
T14	28575	235	0	0
T15	2030	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	4105454	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	4105454	0	0
T1	4056	7	0	0
T2	55912	325	0	0
T3	282435	1525	0	0
T4	5062	102	0	0
T5	187318	789	0	0
T10	15421	133	0	0
T12	17871	54	0	0
T13	4544	94	0	0
T14	28575	140	0	0
T15	2030	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1494736	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1494736	0	0
T1	4056	12	0	0
T2	55912	340	0	0
T3	282435	4011	0	0
T4	5062	89	0	0
T5	187318	2177	0	0
T10	15421	645	0	0
T12	17871	157	0	0
T13	4544	83	0	0
T14	28575	207	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	4095086	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	4095086	0	0
T1	4056	2	0	0
T2	55912	341	0	0
T3	282435	2890	0	0
T4	5062	89	0	0
T5	187318	1033	0	0
T10	15421	644	0	0
T12	17871	59	0	0
T13	4544	83	0	0
T14	28575	254	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1512705	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1512705	0	0
T1	4056	58	0	0
T2	55912	511	0	0
T3	282435	5338	0	0
T4	5062	76	0	0
T5	187318	2133	0	0
T10	15421	142	0	0
T12	17871	109	0	0
T13	4544	85	0	0
T14	28575	244	0	0
T15	2030	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3646370	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3646370	0	0
T1	4056	52	0	0
T2	55912	399	0	0
T3	282435	4246	0	0
T4	5062	76	0	0
T5	187318	1009	0	0
T10	15421	142	0	0
T12	17871	50	0	0
T13	4544	85	0	0
T14	28575	186	0	0
T15	2030	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1492360	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1492360	0	0
T1	4056	98	0	0
T2	55912	444	0	0
T3	282435	1848	0	0
T4	5062	97	0	0
T5	187318	2122	0	0
T10	15421	367	0	0
T12	17871	286	0	0
T13	4544	90	0	0
T14	28575	195	0	0
T15	2030	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3824223	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3824223	0	0
T1	4056	71	0	0
T2	55912	374	0	0
T3	282435	1606	0	0
T4	5062	97	0	0
T5	187318	1072	0	0
T10	15421	367	0	0
T12	17871	178	0	0
T13	4544	90	0	0
T14	28575	139	0	0
T15	2030	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1404243	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1404243	0	0
T1	4056	40	0	0
T2	55912	311	0	0
T3	282435	1475	0	0
T4	5062	103	0	0
T5	187318	1856	0	0
T10	15421	153	0	0
T12	17871	210	0	0
T13	4544	87	0	0
T14	28575	96	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3433230	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3433230	0	0
T1	4056	45	0	0
T2	55912	370	0	0
T3	282435	1260	0	0
T4	5062	103	0	0
T5	187318	830	0	0
T10	15421	153	0	0
T12	17871	64	0	0
T13	4544	87	0	0
T14	28575	108	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1435420	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1435420	0	0
T1	4056	68	0	0
T2	55912	392	0	0
T3	282435	5685	0	0
T4	5062	76	0	0
T5	187318	2394	0	0
T10	15421	126	0	0
T12	17871	142	0	0
T13	4544	78	0	0
T14	28575	158	0	0
T15	2030	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3639739	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3639739	0	0
T1	4056	12	0	0
T2	55912	365	0	0
T3	282435	4344	0	0
T4	5062	76	0	0
T5	187318	1089	0	0
T10	15421	126	0	0
T12	17871	51	0	0
T13	4544	78	0	0
T14	28575	132	0	0
T15	2030	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1440828	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1440828	0	0
T1	4056	16	0	0
T2	55912	450	0	0
T3	282435	1745	0	0
T4	5062	97	0	0
T5	187318	1961	0	0
T10	15421	247	0	0
T12	17871	279	0	0
T13	4544	71	0	0
T14	28575	204	0	0
T15	2030	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3796000	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3796000	0	0
T1	4056	32	0	0
T2	55912	433	0	0
T3	282435	1558	0	0
T4	5062	97	0	0
T5	187318	1001	0	0
T10	15421	246	0	0
T12	17871	162	0	0
T13	4544	71	0	0
T14	28575	182	0	0
T15	2030	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1446990	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1446990	0	0
T1	4056	42	0	0
T2	55912	361	0	0
T3	282435	3597	0	0
T4	5062	90	0	0
T5	187318	1838	0	0
T10	15421	138	0	0
T12	17871	147	0	0
T13	4544	94	0	0
T14	28575	309	0	0
T15	2030	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3533913	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3533913	0	0
T1	4056	70	0	0
T2	55912	369	0	0
T3	282435	2778	0	0
T4	5062	90	0	0
T5	187318	1017	0	0
T10	15421	138	0	0
T12	17871	70	0	0
T13	4544	94	0	0
T14	28575	247	0	0
T15	2030	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1451836	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1451836	0	0
T1	4056	92	0	0
T2	55912	334	0	0
T3	282435	1657	0	0
T4	5062	89	0	0
T5	187318	2332	0	0
T10	15421	201	0	0
T12	17871	298	0	0
T13	4544	75	0	0
T14	28575	165	0	0
T15	2030	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	4223207	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	4223207	0	0
T1	4056	47	0	0
T2	55912	349	0	0
T3	282435	1526	0	0
T4	5062	89	0	0
T5	187318	1068	0	0
T10	15421	201	0	0
T12	17871	111	0	0
T13	4544	75	0	0
T14	28575	162	0	0
T15	2030	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1497260	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1497260	0	0
T1	4056	40	0	0
T2	55912	355	0	0
T3	282435	1795	0	0
T4	5062	107	0	0
T5	187318	2038	0	0
T10	15421	123	0	0
T12	17871	254	0	0
T13	4544	76	0	0
T14	28575	216	0	0
T15	2030	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3841454	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3841454	0	0
T1	4056	57	0	0
T2	55912	381	0	0
T3	282435	1778	0	0
T4	5062	107	0	0
T5	187318	954	0	0
T10	15421	123	0	0
T12	17871	65	0	0
T13	4544	76	0	0
T14	28575	235	0	0
T15	2030	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1475939	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1475939	0	0
T1	4056	18	0	0
T2	55912	332	0	0
T3	282435	1675	0	0
T4	5062	69	0	0
T5	187318	2117	0	0
T10	15421	413	0	0
T12	17871	227	0	0
T13	4544	74	0	0
T14	28575	184	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3916516	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3916516	0	0
T1	4056	45	0	0
T2	55912	332	0	0
T3	282435	1664	0	0
T4	5062	69	0	0
T5	187318	1039	0	0
T10	15421	412	0	0
T12	17871	98	0	0
T13	4544	74	0	0
T14	28575	195	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1462083	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1462083	0	0
T1	4056	25	0	0
T2	55912	259	0	0
T3	282435	5207	0	0
T4	5062	84	0	0
T5	187318	2358	0	0
T10	15421	148	0	0
T12	17871	234	0	0
T13	4544	87	0	0
T14	28575	111	0	0
T15	2030	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	4345382	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	4345382	0	0
T1	4056	25	0	0
T2	55912	325	0	0
T3	282435	4266	0	0
T4	5062	84	0	0
T5	187318	1193	0	0
T10	15421	148	0	0
T12	17871	96	0	0
T13	4544	87	0	0
T14	28575	112	0	0
T15	2030	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1442800	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1442800	0	0
T1	4056	31	0	0
T2	55912	375	0	0
T3	282435	1856	0	0
T4	5062	96	0	0
T5	187318	1924	0	0
T10	15421	435	0	0
T12	17871	301	0	0
T13	4544	68	0	0
T14	28575	267	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3112271	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3112271	0	0
T1	4056	16	0	0
T2	55912	386	0	0
T3	282435	1683	0	0
T4	5062	96	0	0
T5	187318	957	0	0
T10	15421	435	0	0
T12	17871	111	0	0
T13	4544	68	0	0
T14	28575	258	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1434801	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1434801	0	0
T1	4056	61	0	0
T2	55912	371	0	0
T3	282435	3445	0	0
T4	5062	77	0	0
T5	187318	2065	0	0
T10	15421	163	0	0
T12	17871	144	0	0
T13	4544	92	0	0
T14	28575	138	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3455783	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3455783	0	0
T1	4056	32	0	0
T2	55912	412	0	0
T3	282435	3157	0	0
T4	5062	77	0	0
T5	187318	990	0	0
T10	15421	163	0	0
T12	17871	67	0	0
T13	4544	92	0	0
T14	28575	193	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1517350	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1517350	0	0
T1	4056	21	0	0
T2	55912	333	0	0
T3	282435	3462	0	0
T4	5062	88	0	0
T5	187318	2489	0	0
T10	15421	335	0	0
T12	17871	159	0	0
T13	4544	84	0	0
T14	28575	164	0	0
T15	2030	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	4094881	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	4094881	0	0
T1	4056	18	0	0
T2	55912	295	0	0
T3	282435	2953	0	0
T4	5062	88	0	0
T5	187318	1060	0	0
T10	15421	335	0	0
T12	17871	66	0	0
T13	4544	84	0	0
T14	28575	112	0	0
T15	2030	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1460869	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1460869	0	0
T1	4056	24	0	0
T2	55912	310	0	0
T3	282435	3474	0	0
T4	5062	102	0	0
T5	187318	2047	0	0
T10	15421	150	0	0
T12	17871	193	0	0
T13	4544	96	0	0
T14	28575	324	0	0
T15	2030	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3397105	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3397105	0	0
T1	4056	12	0	0
T2	55912	338	0	0
T3	282435	2999	0	0
T4	5062	102	0	0
T5	187318	1009	0	0
T10	15421	150	0	0
T12	17871	91	0	0
T13	4544	96	0	0
T14	28575	264	0	0
T15	2030	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1457316	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1457316	0	0
T1	4056	7	0	0
T2	55912	356	0	0
T3	282435	3808	0	0
T4	5062	111	0	0
T5	187318	2276	0	0
T10	15421	149	0	0
T12	17871	121	0	0
T13	4544	82	0	0
T14	28575	148	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3548847	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3548847	0	0
T1	4056	14	0	0
T2	55912	312	0	0
T3	282435	3369	0	0
T4	5062	111	0	0
T5	187318	1036	0	0
T10	15421	148	0	0
T12	17871	90	0	0
T13	4544	82	0	0
T14	28575	109	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1473034	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1473034	0	0
T1	4056	32	0	0
T2	55912	386	0	0
T3	282435	1562	0	0
T4	5062	112	0	0
T5	187318	2607	0	0
T10	15421	170	0	0
T12	17871	183	0	0
T13	4544	89	0	0
T14	28575	199	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	4182902	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	4182902	0	0
T1	4056	34	0	0
T2	55912	289	0	0
T3	282435	1575	0	0
T4	5062	112	0	0
T5	187318	1200	0	0
T10	15421	170	0	0
T12	17871	138	0	0
T13	4544	89	0	0
T14	28575	176	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1487549	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1487549	0	0
T1	4056	30	0	0
T2	55912	427	0	0
T3	282435	4204	0	0
T4	5062	78	0	0
T5	187318	1932	0	0
T10	15421	363	0	0
T12	17871	191	0	0
T13	4544	86	0	0
T14	28575	197	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3407650	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3407650	0	0
T1	4056	33	0	0
T2	55912	341	0	0
T3	282435	3474	0	0
T4	5062	78	0	0
T5	187318	983	0	0
T10	15421	362	0	0
T12	17871	75	0	0
T13	4544	86	0	0
T14	28575	182	0	0
T15	2030	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1473041	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1473041	0	0
T1	4056	2	0	0
T2	55912	404	0	0
T3	282435	1865	0	0
T4	5062	88	0	0
T5	187318	1953	0	0
T10	15421	134	0	0
T12	17871	189	0	0
T13	4544	92	0	0
T14	28575	204	0	0
T15	2030	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3608119	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3608119	0	0
T1	4056	2	0	0
T2	55912	310	0	0
T3	282435	1853	0	0
T4	5062	88	0	0
T5	187318	898	0	0
T10	15421	134	0	0
T12	17871	110	0	0
T13	4544	92	0	0
T14	28575	183	0	0
T15	2030	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1490080	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1490080	0	0
T1	4056	54	0	0
T2	55912	417	0	0
T3	282435	4402	0	0
T4	5062	75	0	0
T5	187318	2457	0	0
T10	15421	146	0	0
T12	17871	200	0	0
T13	4544	68	0	0
T14	28575	137	0	0
T15	2030	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3991780	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3991780	0	0
T1	4056	29	0	0
T2	55912	340	0	0
T3	282435	3425	0	0
T4	5062	75	0	0
T5	187318	1010	0	0
T10	15421	146	0	0
T12	17871	94	0	0
T13	4544	68	0	0
T14	28575	160	0	0
T15	2030	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1415218	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1415218	0	0
T1	4056	31	0	0
T2	55912	333	0	0
T3	282435	3773	0	0
T4	5062	98	0	0
T5	187318	2129	0	0
T10	15421	128	0	0
T12	17871	185	0	0
T13	4544	76	0	0
T14	28575	199	0	0
T15	2030	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3148060	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3148060	0	0
T1	4056	29	0	0
T2	55912	346	0	0
T3	282435	2926	0	0
T4	5062	98	0	0
T5	187318	905	0	0
T10	15421	128	0	0
T12	17871	54	0	0
T13	4544	76	0	0
T14	28575	223	0	0
T15	2030	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1446798	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1446798	0	0
T1	4056	52	0	0
T2	55912	457	0	0
T3	282435	5825	0	0
T4	5062	91	0	0
T5	187318	1991	0	0
T10	15421	134	0	0
T12	17871	179	0	0
T13	4544	80	0	0
T14	28575	184	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3663381	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3663381	0	0
T1	4056	27	0	0
T2	55912	421	0	0
T3	282435	4590	0	0
T4	5062	91	0	0
T5	187318	1021	0	0
T10	15421	134	0	0
T12	17871	100	0	0
T13	4544	80	0	0
T14	28575	206	0	0
T15	2030	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1470932	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1470932	0	0
T1	4056	1	0	0
T2	55912	219	0	0
T3	282435	4982	0	0
T4	5062	92	0	0
T5	187318	1918	0	0
T10	15421	155	0	0
T12	17871	242	0	0
T13	4544	87	0	0
T14	28575	210	0	0
T15	2030	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3564179	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3564179	0	0
T1	4056	11	0	0
T2	55912	278	0	0
T3	282435	4074	0	0
T4	5062	92	0	0
T5	187318	976	0	0
T10	15421	155	0	0
T12	17871	98	0	0
T13	4544	87	0	0
T14	28575	205	0	0
T15	2030	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1415728	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1415728	0	0
T1	4056	72	0	0
T2	55912	332	0	0
T3	282435	1643	0	0
T4	5062	75	0	0
T5	187318	2074	0	0
T10	15421	147	0	0
T12	17871	236	0	0
T13	4544	75	0	0
T14	28575	186	0	0
T15	2030	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3393268	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3393268	0	0
T1	4056	58	0	0
T2	55912	428	0	0
T3	282435	1590	0	0
T4	5062	75	0	0
T5	187318	954	0	0
T10	15421	147	0	0
T12	17871	82	0	0
T13	4544	75	0	0
T14	28575	214	0	0
T15	2030	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	1465446	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	1465446	0	0
T1	4056	51	0	0
T2	55912	271	0	0
T3	282435	1812	0	0
T4	5062	75	0	0
T5	187318	1972	0	0
T10	15421	343	0	0
T12	17871	179	0	0
T13	4544	87	0	0
T14	28575	205	0	0
T15	2030	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334197731	3760323	0	0
DepthKnown_A	334197731	334072509	0	0
RvalidKnown_A	334197731	334072509	0	0
WreadyKnown_A	334197731	334072509	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	3760323	0	0
T1	4056	22	0	0
T2	55912	310	0	0
T3	282435	1658	0	0
T4	5062	75	0	0
T5	187318	962	0	0
T10	15421	343	0	0
T12	17871	91	0	0
T13	4544	87	0	0
T14	28575	170	0	0
T15	2030	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334197731	334072509	0	0
T1	4056	4028	0	0
T2	55912	55874	0	0
T3	282435	282285	0	0
T4	5062	5032	0	0
T5	187318	187251	0	0
T10	15421	14409	0	0
T12	17871	17819	0	0
T13	4544	4521	0	0
T14	28575	28558	0	0
T15	2030	2018	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0