Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1715317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

270182

1

T1

25

T2

15

T3

230

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	671360	1			T1	47		T2	75		T3	577
values[0x0]	641107	1			T1	57		T2	11		T3	529
values[0x1]	673032	1			T1	67		T2	76		T3	587

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1329334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

656165

1

T1

53

T2

59

T3

575

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7618	1			T3	4		T18	10		T17	16
valid_sources[0x01]	8117	1			T4	2		T18	11		T17	15
valid_sources[0x02]	6708	1			T3	11		T14	1		T18	5
valid_sources[0x03]	7537	1			T14	1		T18	5		T19	1
valid_sources[0x04]	7807	1			T3	6		T4	1		T18	3
valid_sources[0x05]	7981	1			T3	7		T4	1		T14	1
valid_sources[0x06]	7346	1			T3	13		T4	1		T18	4
valid_sources[0x07]	7668	1			T2	1		T3	4		T14	2
valid_sources[0x08]	7501	1			T3	11		T14	1		T18	5
valid_sources[0x09]	8694	1			T3	12		T4	1		T14	3
valid_sources[0x0a]	7583	1			T1	2		T3	15		T4	1
valid_sources[0x0b]	7189	1			T3	8		T18	4		T19	1
valid_sources[0x0c]	7709	1			T2	2		T3	1		T18	2
valid_sources[0x0d]	7242	1			T3	13		T4	1		T14	1
valid_sources[0x0e]	7684	1			T3	4		T4	1		T18	5
valid_sources[0x0f]	8513	1			T3	6		T18	9		T17	15
valid_sources[0x10]	6814	1			T3	6		T18	9		T17	15
valid_sources[0x11]	7658	1			T3	5		T4	3		T14	1
valid_sources[0x12]	7024	1			T3	7		T4	1		T14	1
valid_sources[0x13]	7208	1			T2	1		T3	12		T4	1
valid_sources[0x14]	7844	1			T1	1		T3	10		T4	1
valid_sources[0x15]	7958	1			T3	9		T4	1		T18	7
valid_sources[0x16]	8099	1			T3	3		T18	4		T17	16
valid_sources[0x17]	7206	1			T3	10		T14	1		T18	3
valid_sources[0x18]	8232	1			T2	4		T3	7		T18	5
valid_sources[0x19]	7604	1			T3	17		T4	1		T14	1
valid_sources[0x1a]	7907	1			T2	2		T3	2		T4	3
valid_sources[0x1b]	7303	1			T3	4		T14	1		T18	4
valid_sources[0x1c]	7581	1			T3	7		T14	1		T18	5
valid_sources[0x1d]	7109	1			T3	3		T14	1		T18	9
valid_sources[0x1e]	7717	1			T2	2		T18	5		T17	17
valid_sources[0x1f]	7433	1			T2	2		T3	5		T14	1
valid_sources[0x20]	7407	1			T2	5		T3	4		T14	1
valid_sources[0x21]	8407	1			T3	21		T4	1		T18	8
valid_sources[0x22]	8115	1			T2	1		T3	14		T14	1
valid_sources[0x23]	7396	1			T2	2		T3	3		T4	1
valid_sources[0x24]	7262	1			T3	4		T14	1		T18	5
valid_sources[0x25]	8709	1			T3	1		T4	1		T18	3
valid_sources[0x26]	7406	1			T3	7		T18	6		T17	18
valid_sources[0x27]	7513	1			T3	1		T18	9		T17	17
valid_sources[0x28]	7348	1			T1	15		T2	1		T3	4
valid_sources[0x29]	7731	1			T3	4		T14	1		T18	4
valid_sources[0x2a]	8197	1			T3	13		T18	4		T17	17
valid_sources[0x2b]	9283	1			T4	1		T18	19		T17	15
valid_sources[0x2c]	7339	1			T3	4		T14	1		T18	2
valid_sources[0x2d]	7715	1			T2	1		T3	16		T18	5
valid_sources[0x2e]	6884	1			T1	20		T3	5		T4	2
valid_sources[0x2f]	8251	1			T3	4		T18	1		T17	15
valid_sources[0x30]	7053	1			T3	6		T4	5		T14	1
valid_sources[0x31]	6925	1			T3	11		T18	8		T17	18
valid_sources[0x32]	7199	1			T3	2		T4	1		T18	4
valid_sources[0x33]	7248	1			T2	2		T3	2		T18	13
valid_sources[0x34]	7515	1			T1	11		T3	1		T4	1
valid_sources[0x35]	7690	1			T2	7		T3	7		T4	1
valid_sources[0x36]	6968	1			T3	4		T18	6		T17	17
valid_sources[0x37]	7999	1			T2	1		T3	2		T14	1
valid_sources[0x38]	7161	1			T2	15		T3	1		T4	2
valid_sources[0x39]	6766	1			T3	1		T4	1		T18	6
valid_sources[0x3a]	7925	1			T3	14		T14	1		T18	6
valid_sources[0x3b]	7855	1			T3	8		T4	1		T14	1
valid_sources[0x3c]	7221	1			T4	1		T18	9		T17	16
valid_sources[0x3d]	8416	1			T3	7		T4	1		T18	6
valid_sources[0x3e]	7707	1			T3	8		T18	12		T17	17
valid_sources[0x3f]	8623	1			T3	6		T14	1		T18	3
valid_sources[0x40]	7238	1			T3	1		T14	1		T18	4
valid_sources[0x41]	8190	1			T2	1		T3	17		T18	6
valid_sources[0x42]	7577	1			T3	10		T4	1		T18	6
valid_sources[0x43]	8577	1			T3	3		T4	2		T18	16
valid_sources[0x44]	8119	1			T3	14		T4	1		T18	6
valid_sources[0x45]	7767	1			T3	6		T18	4		T17	16
valid_sources[0x46]	7340	1			T3	2		T14	1		T18	4
valid_sources[0x47]	7307	1			T3	5		T18	3		T17	17
valid_sources[0x48]	7984	1			T3	8		T4	2		T18	8
valid_sources[0x49]	7438	1			T4	4		T18	5		T17	17
valid_sources[0x4a]	8344	1			T3	2		T18	5		T17	14
valid_sources[0x4b]	7547	1			T2	1		T3	11		T4	1
valid_sources[0x4c]	7107	1			T3	15		T14	1		T18	1
valid_sources[0x4d]	8220	1			T2	24		T3	6		T4	3
valid_sources[0x4e]	8224	1			T2	1		T3	3		T4	3
valid_sources[0x4f]	8011	1			T3	5		T14	1		T18	9
valid_sources[0x50]	9091	1			T18	8		T17	14		T20	61
valid_sources[0x51]	8222	1			T2	2		T3	14		T4	1
valid_sources[0x52]	7281	1			T3	10		T4	1		T14	1
valid_sources[0x53]	8228	1			T3	4		T14	1		T18	3
valid_sources[0x54]	8983	1			T2	1		T3	9		T4	1
valid_sources[0x55]	7842	1			T3	6		T4	1		T14	2
valid_sources[0x56]	7961	1			T2	1		T3	3		T4	1
valid_sources[0x57]	7147	1			T3	2		T18	7		T17	13
valid_sources[0x58]	7505	1			T3	6		T4	1		T18	3
valid_sources[0x59]	6832	1			T3	14		T4	3		T14	2
valid_sources[0x5a]	6805	1			T3	6		T4	1		T18	10
valid_sources[0x5b]	7972	1			T3	8		T18	6		T17	17
valid_sources[0x5c]	7124	1			T3	6		T4	1		T18	3
valid_sources[0x5d]	7867	1			T3	4		T4	2		T14	1
valid_sources[0x5e]	7637	1			T3	8		T18	4		T17	16
valid_sources[0x5f]	9968	1			T3	7		T4	1		T18	4
valid_sources[0x60]	6707	1			T3	8		T18	5		T17	16
valid_sources[0x61]	7901	1			T2	2		T3	4		T18	17
valid_sources[0x62]	7381	1			T3	5		T18	2		T19	4
valid_sources[0x63]	7629	1			T3	6		T18	5		T17	17
valid_sources[0x64]	8066	1			T2	3		T3	3		T14	1
valid_sources[0x65]	8300	1			T3	12		T18	14		T17	16
valid_sources[0x66]	8039	1			T3	8		T18	5		T17	14
valid_sources[0x67]	8502	1			T3	15		T18	10		T19	1
valid_sources[0x68]	8271	1			T2	1		T3	3		T18	8
valid_sources[0x69]	10580	1			T3	6		T4	1		T14	1
valid_sources[0x6a]	7871	1			T3	7		T14	1		T18	13
valid_sources[0x6b]	7491	1			T3	10		T4	2		T18	4
valid_sources[0x6c]	7013	1			T3	5		T18	8		T17	17
valid_sources[0x6d]	7249	1			T3	14		T18	4		T17	16
valid_sources[0x6e]	7660	1			T3	7		T4	3		T18	11
valid_sources[0x6f]	7977	1			T3	7		T4	1		T18	4
valid_sources[0x70]	7053	1			T3	8		T18	7		T17	18
valid_sources[0x71]	7981	1			T3	8		T18	4		T17	16
valid_sources[0x72]	8361	1			T3	7		T4	1		T18	4
valid_sources[0x73]	8209	1			T4	2		T14	1		T18	6
valid_sources[0x74]	7547	1			T18	7		T17	17		T5	49
valid_sources[0x75]	8674	1			T3	4		T18	9		T17	17
valid_sources[0x76]	8463	1			T3	6		T4	3		T18	6
valid_sources[0x77]	7079	1			T2	2		T3	2		T18	2
valid_sources[0x78]	8537	1			T1	2		T2	2		T3	8
valid_sources[0x79]	7173	1			T3	15		T4	1		T14	1
valid_sources[0x7a]	7418	1			T3	5		T18	5		T17	15
valid_sources[0x7b]	7571	1			T1	14		T3	1		T4	1
valid_sources[0x7c]	7886	1			T3	13		T18	4		T17	16
valid_sources[0x7d]	7623	1			T2	1		T4	1		T18	5
valid_sources[0x7e]	7881	1			T2	16		T3	2		T4	2
valid_sources[0x7f]	8654	1			T3	8		T4	1		T14	2
valid_sources[0x80]	8484	1			T17	17		T5	65		T23	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28578

1

T1

1

T2

2

T3

19

values[0x0]

all_enables

biggest_size

213107

1

T1

22

T2

8

T3

176

values[0x1]

all_enables

biggest_size

28497

1

T1

2

T2

5

T3

35